platform.c 12 KB

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  1. /*
  2. * Platform device support for Au1x00 SoCs.
  3. *
  4. * Copyright 2004, Matt Porter <[email protected]>
  5. *
  6. * (C) Copyright Embedded Alley Solutions, Inc 2005
  7. * Author: Pantelis Antoniou <[email protected]>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/serial_8250.h>
  19. #include <linux/slab.h>
  20. #include <linux/usb/ehci_pdriver.h>
  21. #include <linux/usb/ohci_pdriver.h>
  22. #include <asm/mach-au1x00/au1000.h>
  23. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  24. #include <asm/mach-au1x00/au1100_mmc.h>
  25. #include <asm/mach-au1x00/au1xxx_eth.h>
  26. #include <prom.h>
  27. static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
  28. unsigned int old_state)
  29. {
  30. #ifdef CONFIG_SERIAL_8250
  31. switch (state) {
  32. case 0:
  33. alchemy_uart_enable(CPHYSADDR(port->membase));
  34. serial8250_do_pm(port, state, old_state);
  35. break;
  36. case 3: /* power off */
  37. serial8250_do_pm(port, state, old_state);
  38. alchemy_uart_disable(CPHYSADDR(port->membase));
  39. break;
  40. default:
  41. serial8250_do_pm(port, state, old_state);
  42. break;
  43. }
  44. #endif
  45. }
  46. #define PORT(_base, _irq) \
  47. { \
  48. .mapbase = _base, \
  49. .irq = _irq, \
  50. .regshift = 2, \
  51. .iotype = UPIO_AU, \
  52. .flags = UPF_SKIP_TEST | UPF_IOREMAP | \
  53. UPF_FIXED_TYPE, \
  54. .type = PORT_16550A, \
  55. .pm = alchemy_8250_pm, \
  56. }
  57. static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
  58. [ALCHEMY_CPU_AU1000] = {
  59. PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
  60. PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
  61. PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
  62. PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
  63. },
  64. [ALCHEMY_CPU_AU1500] = {
  65. PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
  66. PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
  67. },
  68. [ALCHEMY_CPU_AU1100] = {
  69. PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
  70. PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
  71. PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
  72. },
  73. [ALCHEMY_CPU_AU1550] = {
  74. PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
  75. PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
  76. PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
  77. },
  78. [ALCHEMY_CPU_AU1200] = {
  79. PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
  80. PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
  81. },
  82. [ALCHEMY_CPU_AU1300] = {
  83. PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT),
  84. PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT),
  85. PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT),
  86. PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT),
  87. },
  88. };
  89. static struct platform_device au1xx0_uart_device = {
  90. .name = "serial8250",
  91. .id = PLAT8250_DEV_AU1X00,
  92. };
  93. static void __init alchemy_setup_uarts(int ctype)
  94. {
  95. long uartclk;
  96. int s = sizeof(struct plat_serial8250_port);
  97. int c = alchemy_get_uarts(ctype);
  98. struct plat_serial8250_port *ports;
  99. struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK);
  100. if (IS_ERR(clk))
  101. return;
  102. if (clk_prepare_enable(clk)) {
  103. clk_put(clk);
  104. return;
  105. }
  106. uartclk = clk_get_rate(clk);
  107. clk_put(clk);
  108. ports = kcalloc(s, (c + 1), GFP_KERNEL);
  109. if (!ports) {
  110. printk(KERN_INFO "Alchemy: no memory for UART data\n");
  111. return;
  112. }
  113. memcpy(ports, au1x00_uart_data[ctype], s * c);
  114. au1xx0_uart_device.dev.platform_data = ports;
  115. /* Fill up uartclk. */
  116. for (s = 0; s < c; s++)
  117. ports[s].uartclk = uartclk;
  118. if (platform_device_register(&au1xx0_uart_device))
  119. printk(KERN_INFO "Alchemy: failed to register UARTs\n");
  120. }
  121. static u64 alchemy_all_dmamask = DMA_BIT_MASK(32);
  122. /* Power on callback for the ehci platform driver */
  123. static int alchemy_ehci_power_on(struct platform_device *pdev)
  124. {
  125. return alchemy_usb_control(ALCHEMY_USB_EHCI0, 1);
  126. }
  127. /* Power off/suspend callback for the ehci platform driver */
  128. static void alchemy_ehci_power_off(struct platform_device *pdev)
  129. {
  130. alchemy_usb_control(ALCHEMY_USB_EHCI0, 0);
  131. }
  132. static struct usb_ehci_pdata alchemy_ehci_pdata = {
  133. .no_io_watchdog = 1,
  134. .power_on = alchemy_ehci_power_on,
  135. .power_off = alchemy_ehci_power_off,
  136. .power_suspend = alchemy_ehci_power_off,
  137. };
  138. /* Power on callback for the ohci platform driver */
  139. static int alchemy_ohci_power_on(struct platform_device *pdev)
  140. {
  141. int unit;
  142. unit = (pdev->id == 1) ?
  143. ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
  144. return alchemy_usb_control(unit, 1);
  145. }
  146. /* Power off/suspend callback for the ohci platform driver */
  147. static void alchemy_ohci_power_off(struct platform_device *pdev)
  148. {
  149. int unit;
  150. unit = (pdev->id == 1) ?
  151. ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
  152. alchemy_usb_control(unit, 0);
  153. }
  154. static struct usb_ohci_pdata alchemy_ohci_pdata = {
  155. .power_on = alchemy_ohci_power_on,
  156. .power_off = alchemy_ohci_power_off,
  157. .power_suspend = alchemy_ohci_power_off,
  158. };
  159. static unsigned long alchemy_ohci_data[][2] __initdata = {
  160. [ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
  161. [ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
  162. [ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
  163. [ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
  164. [ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
  165. [ALCHEMY_CPU_AU1300] = { AU1300_USB_OHCI0_PHYS_ADDR, AU1300_USB_INT },
  166. };
  167. static unsigned long alchemy_ehci_data[][2] __initdata = {
  168. [ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
  169. [ALCHEMY_CPU_AU1300] = { AU1300_USB_EHCI_PHYS_ADDR, AU1300_USB_INT },
  170. };
  171. static int __init _new_usbres(struct resource **r, struct platform_device **d)
  172. {
  173. *r = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
  174. if (!*r)
  175. return -ENOMEM;
  176. *d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
  177. if (!*d) {
  178. kfree(*r);
  179. return -ENOMEM;
  180. }
  181. (*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  182. (*d)->num_resources = 2;
  183. (*d)->resource = *r;
  184. return 0;
  185. }
  186. static void __init alchemy_setup_usb(int ctype)
  187. {
  188. struct resource *res;
  189. struct platform_device *pdev;
  190. /* setup OHCI0. Every variant has one */
  191. if (_new_usbres(&res, &pdev))
  192. return;
  193. res[0].start = alchemy_ohci_data[ctype][0];
  194. res[0].end = res[0].start + 0x100 - 1;
  195. res[0].flags = IORESOURCE_MEM;
  196. res[1].start = alchemy_ohci_data[ctype][1];
  197. res[1].end = res[1].start;
  198. res[1].flags = IORESOURCE_IRQ;
  199. pdev->name = "ohci-platform";
  200. pdev->id = 0;
  201. pdev->dev.dma_mask = &alchemy_all_dmamask;
  202. pdev->dev.platform_data = &alchemy_ohci_pdata;
  203. if (platform_device_register(pdev))
  204. printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
  205. /* setup EHCI0: Au1200/Au1300 */
  206. if ((ctype == ALCHEMY_CPU_AU1200) || (ctype == ALCHEMY_CPU_AU1300)) {
  207. if (_new_usbres(&res, &pdev))
  208. return;
  209. res[0].start = alchemy_ehci_data[ctype][0];
  210. res[0].end = res[0].start + 0x100 - 1;
  211. res[0].flags = IORESOURCE_MEM;
  212. res[1].start = alchemy_ehci_data[ctype][1];
  213. res[1].end = res[1].start;
  214. res[1].flags = IORESOURCE_IRQ;
  215. pdev->name = "ehci-platform";
  216. pdev->id = 0;
  217. pdev->dev.dma_mask = &alchemy_all_dmamask;
  218. pdev->dev.platform_data = &alchemy_ehci_pdata;
  219. if (platform_device_register(pdev))
  220. printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
  221. }
  222. /* Au1300: OHCI1 */
  223. if (ctype == ALCHEMY_CPU_AU1300) {
  224. if (_new_usbres(&res, &pdev))
  225. return;
  226. res[0].start = AU1300_USB_OHCI1_PHYS_ADDR;
  227. res[0].end = res[0].start + 0x100 - 1;
  228. res[0].flags = IORESOURCE_MEM;
  229. res[1].start = AU1300_USB_INT;
  230. res[1].end = res[1].start;
  231. res[1].flags = IORESOURCE_IRQ;
  232. pdev->name = "ohci-platform";
  233. pdev->id = 1;
  234. pdev->dev.dma_mask = &alchemy_all_dmamask;
  235. pdev->dev.platform_data = &alchemy_ohci_pdata;
  236. if (platform_device_register(pdev))
  237. printk(KERN_INFO "Alchemy USB: cannot add OHCI1\n");
  238. }
  239. }
  240. /* Macro to help defining the Ethernet MAC resources */
  241. #define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
  242. #define MAC_RES(_base, _enable, _irq, _macdma) \
  243. { \
  244. .start = _base, \
  245. .end = _base + 0xffff, \
  246. .flags = IORESOURCE_MEM, \
  247. }, \
  248. { \
  249. .start = _enable, \
  250. .end = _enable + 0x3, \
  251. .flags = IORESOURCE_MEM, \
  252. }, \
  253. { \
  254. .start = _irq, \
  255. .end = _irq, \
  256. .flags = IORESOURCE_IRQ \
  257. }, \
  258. { \
  259. .start = _macdma, \
  260. .end = _macdma + 0x1ff, \
  261. .flags = IORESOURCE_MEM, \
  262. }
  263. static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
  264. [ALCHEMY_CPU_AU1000] = {
  265. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  266. AU1000_MACEN_PHYS_ADDR,
  267. AU1000_MAC0_DMA_INT,
  268. AU1000_MACDMA0_PHYS_ADDR)
  269. },
  270. [ALCHEMY_CPU_AU1500] = {
  271. MAC_RES(AU1500_MAC0_PHYS_ADDR,
  272. AU1500_MACEN_PHYS_ADDR,
  273. AU1500_MAC0_DMA_INT,
  274. AU1000_MACDMA0_PHYS_ADDR)
  275. },
  276. [ALCHEMY_CPU_AU1100] = {
  277. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  278. AU1000_MACEN_PHYS_ADDR,
  279. AU1100_MAC0_DMA_INT,
  280. AU1000_MACDMA0_PHYS_ADDR)
  281. },
  282. [ALCHEMY_CPU_AU1550] = {
  283. MAC_RES(AU1000_MAC0_PHYS_ADDR,
  284. AU1000_MACEN_PHYS_ADDR,
  285. AU1550_MAC0_DMA_INT,
  286. AU1000_MACDMA0_PHYS_ADDR)
  287. },
  288. };
  289. static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
  290. .phy1_search_mac0 = 1,
  291. };
  292. static struct platform_device au1xxx_eth0_device = {
  293. .name = "au1000-eth",
  294. .id = 0,
  295. .num_resources = MAC_RES_COUNT,
  296. .dev = {
  297. .dma_mask = &alchemy_all_dmamask,
  298. .coherent_dma_mask = DMA_BIT_MASK(32),
  299. .platform_data = &au1xxx_eth0_platform_data,
  300. },
  301. };
  302. static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
  303. [ALCHEMY_CPU_AU1000] = {
  304. MAC_RES(AU1000_MAC1_PHYS_ADDR,
  305. AU1000_MACEN_PHYS_ADDR + 4,
  306. AU1000_MAC1_DMA_INT,
  307. AU1000_MACDMA1_PHYS_ADDR)
  308. },
  309. [ALCHEMY_CPU_AU1500] = {
  310. MAC_RES(AU1500_MAC1_PHYS_ADDR,
  311. AU1500_MACEN_PHYS_ADDR + 4,
  312. AU1500_MAC1_DMA_INT,
  313. AU1000_MACDMA1_PHYS_ADDR)
  314. },
  315. [ALCHEMY_CPU_AU1550] = {
  316. MAC_RES(AU1000_MAC1_PHYS_ADDR,
  317. AU1000_MACEN_PHYS_ADDR + 4,
  318. AU1550_MAC1_DMA_INT,
  319. AU1000_MACDMA1_PHYS_ADDR)
  320. },
  321. };
  322. static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
  323. .phy1_search_mac0 = 1,
  324. };
  325. static struct platform_device au1xxx_eth1_device = {
  326. .name = "au1000-eth",
  327. .id = 1,
  328. .num_resources = MAC_RES_COUNT,
  329. .dev = {
  330. .dma_mask = &alchemy_all_dmamask,
  331. .coherent_dma_mask = DMA_BIT_MASK(32),
  332. .platform_data = &au1xxx_eth1_platform_data,
  333. },
  334. };
  335. void __init au1xxx_override_eth_cfg(unsigned int port,
  336. struct au1000_eth_platform_data *eth_data)
  337. {
  338. if (!eth_data || port > 1)
  339. return;
  340. if (port == 0)
  341. memcpy(&au1xxx_eth0_platform_data, eth_data,
  342. sizeof(struct au1000_eth_platform_data));
  343. else
  344. memcpy(&au1xxx_eth1_platform_data, eth_data,
  345. sizeof(struct au1000_eth_platform_data));
  346. }
  347. static void __init alchemy_setup_macs(int ctype)
  348. {
  349. int ret, i;
  350. unsigned char ethaddr[6];
  351. struct resource *macres;
  352. /* Handle 1st MAC */
  353. if (alchemy_get_macs(ctype) < 1)
  354. return;
  355. macres = kmemdup(au1xxx_eth0_resources[ctype],
  356. sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
  357. if (!macres) {
  358. printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
  359. return;
  360. }
  361. au1xxx_eth0_device.resource = macres;
  362. i = prom_get_ethernet_addr(ethaddr);
  363. if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
  364. memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
  365. ret = platform_device_register(&au1xxx_eth0_device);
  366. if (ret)
  367. printk(KERN_INFO "Alchemy: failed to register MAC0\n");
  368. /* Handle 2nd MAC */
  369. if (alchemy_get_macs(ctype) < 2)
  370. return;
  371. macres = kmemdup(au1xxx_eth1_resources[ctype],
  372. sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
  373. if (!macres) {
  374. printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
  375. return;
  376. }
  377. au1xxx_eth1_device.resource = macres;
  378. ethaddr[5] += 1; /* next addr for 2nd MAC */
  379. if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
  380. memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
  381. /* Register second MAC if enabled in pinfunc */
  382. if (!(alchemy_rdsys(AU1000_SYS_PINFUNC) & SYS_PF_NI2)) {
  383. ret = platform_device_register(&au1xxx_eth1_device);
  384. if (ret)
  385. printk(KERN_INFO "Alchemy: failed to register MAC1\n");
  386. }
  387. }
  388. static int __init au1xxx_platform_init(void)
  389. {
  390. int ctype = alchemy_get_cputype();
  391. alchemy_setup_uarts(ctype);
  392. alchemy_setup_macs(ctype);
  393. alchemy_setup_usb(ctype);
  394. return 0;
  395. }
  396. arch_initcall(au1xxx_platform_init);