board-gpr.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * GPR board platform device registration (Au1550)
  4. *
  5. * Copyright (C) 2010 Wolfgang Grandegger <[email protected]>
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/init.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/kernel.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/pm.h>
  13. #include <linux/mtd/partitions.h>
  14. #include <linux/mtd/physmap.h>
  15. #include <linux/leds.h>
  16. #include <linux/gpio.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/i2c-gpio.h>
  19. #include <linux/gpio/machine.h>
  20. #include <asm/bootinfo.h>
  21. #include <asm/idle.h>
  22. #include <asm/reboot.h>
  23. #include <asm/setup.h>
  24. #include <asm/mach-au1x00/au1000.h>
  25. #include <asm/mach-au1x00/gpio-au1000.h>
  26. #include <prom.h>
  27. const char *get_system_type(void)
  28. {
  29. return "GPR";
  30. }
  31. void prom_putchar(char c)
  32. {
  33. alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
  34. }
  35. static void gpr_reset(char *c)
  36. {
  37. /* switch System-LED to orange (red# and green# on) */
  38. alchemy_gpio_direction_output(4, 0);
  39. alchemy_gpio_direction_output(5, 0);
  40. /* trigger watchdog to reset board in 200ms */
  41. printk(KERN_EMERG "Triggering watchdog soft reset...\n");
  42. raw_local_irq_disable();
  43. alchemy_gpio_direction_output(1, 0);
  44. udelay(1);
  45. alchemy_gpio_set_value(1, 1);
  46. while (1)
  47. cpu_wait();
  48. }
  49. static void gpr_power_off(void)
  50. {
  51. while (1)
  52. cpu_wait();
  53. }
  54. void __init board_setup(void)
  55. {
  56. printk(KERN_INFO "Trapeze ITS GPR board\n");
  57. pm_power_off = gpr_power_off;
  58. _machine_halt = gpr_power_off;
  59. _machine_restart = gpr_reset;
  60. /* Enable UART1/3 */
  61. alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
  62. alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
  63. /* Take away Reset of UMTS-card */
  64. alchemy_gpio_direction_output(215, 1);
  65. }
  66. /*
  67. * Watchdog
  68. */
  69. static struct resource gpr_wdt_resource[] = {
  70. [0] = {
  71. .start = 1,
  72. .end = 1,
  73. .name = "gpr-adm6320-wdt",
  74. .flags = IORESOURCE_IRQ,
  75. }
  76. };
  77. static struct platform_device gpr_wdt_device = {
  78. .name = "adm6320-wdt",
  79. .id = 0,
  80. .num_resources = ARRAY_SIZE(gpr_wdt_resource),
  81. .resource = gpr_wdt_resource,
  82. };
  83. /*
  84. * FLASH
  85. *
  86. * 0x00000000-0x00200000 : "kernel"
  87. * 0x00200000-0x00a00000 : "rootfs"
  88. * 0x01d00000-0x01f00000 : "config"
  89. * 0x01c00000-0x01d00000 : "yamon"
  90. * 0x01d00000-0x01d40000 : "yamon env vars"
  91. * 0x00000000-0x00a00000 : "kernel+rootfs"
  92. */
  93. static struct mtd_partition gpr_mtd_partitions[] = {
  94. {
  95. .name = "kernel",
  96. .size = 0x00200000,
  97. .offset = 0,
  98. },
  99. {
  100. .name = "rootfs",
  101. .size = 0x00800000,
  102. .offset = MTDPART_OFS_APPEND,
  103. .mask_flags = MTD_WRITEABLE,
  104. },
  105. {
  106. .name = "config",
  107. .size = 0x00200000,
  108. .offset = 0x01d00000,
  109. },
  110. {
  111. .name = "yamon",
  112. .size = 0x00100000,
  113. .offset = 0x01c00000,
  114. },
  115. {
  116. .name = "yamon env vars",
  117. .size = 0x00040000,
  118. .offset = MTDPART_OFS_APPEND,
  119. },
  120. {
  121. .name = "kernel+rootfs",
  122. .size = 0x00a00000,
  123. .offset = 0,
  124. },
  125. };
  126. static struct physmap_flash_data gpr_flash_data = {
  127. .width = 4,
  128. .nr_parts = ARRAY_SIZE(gpr_mtd_partitions),
  129. .parts = gpr_mtd_partitions,
  130. };
  131. static struct resource gpr_mtd_resource = {
  132. .start = 0x1e000000,
  133. .end = 0x1fffffff,
  134. .flags = IORESOURCE_MEM,
  135. };
  136. static struct platform_device gpr_mtd_device = {
  137. .name = "physmap-flash",
  138. .dev = {
  139. .platform_data = &gpr_flash_data,
  140. },
  141. .num_resources = 1,
  142. .resource = &gpr_mtd_resource,
  143. };
  144. /*
  145. * LEDs
  146. */
  147. static const struct gpio_led gpr_gpio_leds[] = {
  148. { /* green */
  149. .name = "gpr:green",
  150. .gpio = 4,
  151. .active_low = 1,
  152. },
  153. { /* red */
  154. .name = "gpr:red",
  155. .gpio = 5,
  156. .active_low = 1,
  157. }
  158. };
  159. static struct gpio_led_platform_data gpr_led_data = {
  160. .num_leds = ARRAY_SIZE(gpr_gpio_leds),
  161. .leds = gpr_gpio_leds,
  162. };
  163. static struct platform_device gpr_led_devices = {
  164. .name = "leds-gpio",
  165. .id = -1,
  166. .dev = {
  167. .platform_data = &gpr_led_data,
  168. }
  169. };
  170. /*
  171. * I2C
  172. */
  173. static struct gpiod_lookup_table gpr_i2c_gpiod_table = {
  174. .dev_id = "i2c-gpio",
  175. .table = {
  176. /*
  177. * This should be on "GPIO2" which has base at 200 so
  178. * the global numbers 209 and 210 should correspond to
  179. * local offsets 9 and 10.
  180. */
  181. GPIO_LOOKUP_IDX("alchemy-gpio2", 9, NULL, 0,
  182. GPIO_ACTIVE_HIGH),
  183. GPIO_LOOKUP_IDX("alchemy-gpio2", 10, NULL, 1,
  184. GPIO_ACTIVE_HIGH),
  185. },
  186. };
  187. static struct i2c_gpio_platform_data gpr_i2c_data = {
  188. /*
  189. * The open drain mode is hardwired somewhere or an electrical
  190. * property of the alchemy GPIO controller.
  191. */
  192. .sda_is_open_drain = 1,
  193. .scl_is_open_drain = 1,
  194. .udelay = 2, /* ~100 kHz */
  195. .timeout = HZ,
  196. };
  197. static struct platform_device gpr_i2c_device = {
  198. .name = "i2c-gpio",
  199. .id = -1,
  200. .dev.platform_data = &gpr_i2c_data,
  201. };
  202. static struct i2c_board_info gpr_i2c_info[] __initdata = {
  203. {
  204. I2C_BOARD_INFO("lm83", 0x18),
  205. }
  206. };
  207. static struct resource alchemy_pci_host_res[] = {
  208. [0] = {
  209. .start = AU1500_PCI_PHYS_ADDR,
  210. .end = AU1500_PCI_PHYS_ADDR + 0xfff,
  211. .flags = IORESOURCE_MEM,
  212. },
  213. };
  214. static int gpr_map_pci_irq(const struct pci_dev *d, u8 slot, u8 pin)
  215. {
  216. if ((slot == 0) && (pin == 1))
  217. return AU1550_PCI_INTA;
  218. else if ((slot == 0) && (pin == 2))
  219. return AU1550_PCI_INTB;
  220. return 0xff;
  221. }
  222. static struct alchemy_pci_platdata gpr_pci_pd = {
  223. .board_map_irq = gpr_map_pci_irq,
  224. .pci_cfg_set = PCI_CONFIG_AEN | PCI_CONFIG_R2H | PCI_CONFIG_R1H |
  225. PCI_CONFIG_CH |
  226. #if defined(__MIPSEB__)
  227. PCI_CONFIG_SIC_HWA_DAT | PCI_CONFIG_SM,
  228. #else
  229. 0,
  230. #endif
  231. };
  232. static struct platform_device gpr_pci_host_dev = {
  233. .dev.platform_data = &gpr_pci_pd,
  234. .name = "alchemy-pci",
  235. .id = 0,
  236. .num_resources = ARRAY_SIZE(alchemy_pci_host_res),
  237. .resource = alchemy_pci_host_res,
  238. };
  239. static struct platform_device *gpr_devices[] __initdata = {
  240. &gpr_wdt_device,
  241. &gpr_mtd_device,
  242. &gpr_i2c_device,
  243. &gpr_led_devices,
  244. };
  245. static int __init gpr_pci_init(void)
  246. {
  247. return platform_device_register(&gpr_pci_host_dev);
  248. }
  249. /* must be arch_initcall; MIPS PCI scans busses in a subsys_initcall */
  250. arch_initcall(gpr_pci_init);
  251. static int __init gpr_dev_init(void)
  252. {
  253. gpiod_add_lookup_table(&gpr_i2c_gpiod_table);
  254. i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
  255. return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
  256. }
  257. device_initcall(gpr_dev_init);