pci.c 6.3 KB

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  1. /*
  2. * pci.c -- PCI bus support for ColdFire processors
  3. *
  4. * (C) Copyright 2012, Greg Ungerer <[email protected]>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/types.h>
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/kernel.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irq.h>
  16. #include <linux/io.h>
  17. #include <linux/pci.h>
  18. #include <linux/delay.h>
  19. #include <asm/coldfire.h>
  20. #include <asm/mcfsim.h>
  21. #include <asm/m54xxpci.h>
  22. /*
  23. * Memory and IO mappings. We use a 1:1 mapping for local host memory to
  24. * PCI bus memory (no reason not to really). IO space is mapped in its own
  25. * separate address region. The device configuration space is mapped over
  26. * the IO map space when we enable it in the PCICAR register.
  27. */
  28. static struct pci_bus *rootbus;
  29. static unsigned long iospace;
  30. /*
  31. * We need to be careful probing on bus 0 (directly connected to host
  32. * bridge). We should only access the well defined possible devices in
  33. * use, ignore aliases and the like.
  34. */
  35. static unsigned char mcf_host_slot2sid[32] = {
  36. 0, 0, 0, 0, 0, 0, 0, 0,
  37. 0, 0, 0, 0, 0, 0, 0, 0,
  38. 0, 1, 2, 0, 3, 4, 0, 0,
  39. 0, 0, 0, 0, 0, 0, 0, 0,
  40. };
  41. static unsigned char mcf_host_irq[] = {
  42. 0, 69, 69, 71, 71,
  43. };
  44. /*
  45. * Configuration space access functions. Configuration space access is
  46. * through the IO mapping window, enabling it via the PCICAR register.
  47. */
  48. static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
  49. {
  50. return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
  51. }
  52. static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
  53. int where, int size, u32 *value)
  54. {
  55. unsigned long addr;
  56. *value = 0xffffffff;
  57. if (bus->number == 0) {
  58. if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
  59. return PCIBIOS_SUCCESSFUL;
  60. }
  61. addr = mcf_mk_pcicar(bus->number, devfn, where);
  62. __raw_writel(PCICAR_E | addr, PCICAR);
  63. __raw_readl(PCICAR);
  64. addr = iospace + (where & 0x3);
  65. switch (size) {
  66. case 1:
  67. *value = __raw_readb(addr);
  68. break;
  69. case 2:
  70. *value = le16_to_cpu(__raw_readw(addr));
  71. break;
  72. default:
  73. *value = le32_to_cpu(__raw_readl(addr));
  74. break;
  75. }
  76. __raw_writel(0, PCICAR);
  77. __raw_readl(PCICAR);
  78. return PCIBIOS_SUCCESSFUL;
  79. }
  80. static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
  81. int where, int size, u32 value)
  82. {
  83. unsigned long addr;
  84. if (bus->number == 0) {
  85. if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
  86. return PCIBIOS_SUCCESSFUL;
  87. }
  88. addr = mcf_mk_pcicar(bus->number, devfn, where);
  89. __raw_writel(PCICAR_E | addr, PCICAR);
  90. __raw_readl(PCICAR);
  91. addr = iospace + (where & 0x3);
  92. switch (size) {
  93. case 1:
  94. __raw_writeb(value, addr);
  95. break;
  96. case 2:
  97. __raw_writew(cpu_to_le16(value), addr);
  98. break;
  99. default:
  100. __raw_writel(cpu_to_le32(value), addr);
  101. break;
  102. }
  103. __raw_writel(0, PCICAR);
  104. __raw_readl(PCICAR);
  105. return PCIBIOS_SUCCESSFUL;
  106. }
  107. static struct pci_ops mcf_pci_ops = {
  108. .read = mcf_pci_readconfig,
  109. .write = mcf_pci_writeconfig,
  110. };
  111. /*
  112. * Initialize the PCI bus registers, and scan the bus.
  113. */
  114. static struct resource mcf_pci_mem = {
  115. .name = "PCI Memory space",
  116. .start = PCI_MEM_PA,
  117. .end = PCI_MEM_PA + PCI_MEM_SIZE - 1,
  118. .flags = IORESOURCE_MEM,
  119. };
  120. static struct resource mcf_pci_io = {
  121. .name = "PCI IO space",
  122. .start = 0x400,
  123. .end = 0x10000 - 1,
  124. .flags = IORESOURCE_IO,
  125. };
  126. static struct resource busn_resource = {
  127. .name = "PCI busn",
  128. .start = 0,
  129. .end = 255,
  130. .flags = IORESOURCE_BUS,
  131. };
  132. /*
  133. * Interrupt mapping and setting.
  134. */
  135. static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  136. {
  137. int sid;
  138. sid = mcf_host_slot2sid[slot];
  139. if (sid)
  140. return mcf_host_irq[sid];
  141. return 0;
  142. }
  143. static int __init mcf_pci_init(void)
  144. {
  145. struct pci_host_bridge *bridge;
  146. int ret;
  147. bridge = pci_alloc_host_bridge(0);
  148. if (!bridge)
  149. return -ENOMEM;
  150. pr_info("ColdFire: PCI bus initialization...\n");
  151. /* Reset the external PCI bus */
  152. __raw_writel(PCIGSCR_RESET, PCIGSCR);
  153. __raw_writel(0, PCITCR);
  154. request_resource(&iomem_resource, &mcf_pci_mem);
  155. request_resource(&iomem_resource, &mcf_pci_io);
  156. /* Configure PCI arbiter */
  157. __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
  158. PACR_EXTMINTE(0x1f), PACR);
  159. /* Set required multi-function pins for PCI bus use */
  160. __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
  161. __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
  162. /* Set up config space for local host bus controller */
  163. __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
  164. PCI_COMMAND_INVALIDATE, PCISCR);
  165. __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
  166. __raw_writel(0, PCICR2);
  167. /*
  168. * Set up the initiator windows for memory and IO mapping.
  169. * These give the CPU bus access onto the PCI bus. One for each of
  170. * PCI memory and IO address spaces.
  171. */
  172. __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
  173. PCIIW0BTAR);
  174. __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
  175. PCIIW1BTAR);
  176. __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
  177. PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
  178. /*
  179. * Set up the target windows for access from the PCI bus back to the
  180. * CPU bus. All we need is access to system RAM (for mastering).
  181. */
  182. __raw_writel(CONFIG_RAMBASE, PCIBAR1);
  183. __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
  184. /* Keep a virtual mapping to IO/config space active */
  185. iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
  186. if (iospace == 0) {
  187. pci_free_host_bridge(bridge);
  188. return -ENODEV;
  189. }
  190. pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
  191. (u32) iospace);
  192. /* Turn of PCI reset, and wait for devices to settle */
  193. __raw_writel(0, PCIGSCR);
  194. set_current_state(TASK_UNINTERRUPTIBLE);
  195. schedule_timeout(msecs_to_jiffies(200));
  196. pci_add_resource(&bridge->windows, &ioport_resource);
  197. pci_add_resource(&bridge->windows, &iomem_resource);
  198. pci_add_resource(&bridge->windows, &busn_resource);
  199. bridge->dev.parent = NULL;
  200. bridge->sysdata = NULL;
  201. bridge->busnr = 0;
  202. bridge->ops = &mcf_pci_ops;
  203. bridge->swizzle_irq = pci_common_swizzle;
  204. bridge->map_irq = mcf_pci_map_irq;
  205. ret = pci_scan_root_bus_bridge(bridge);
  206. if (ret) {
  207. pci_free_host_bridge(bridge);
  208. return ret;
  209. }
  210. rootbus = bridge->bus;
  211. rootbus->resource[0] = &mcf_pci_io;
  212. rootbus->resource[1] = &mcf_pci_mem;
  213. pci_bus_size_bridges(rootbus);
  214. pci_bus_assign_resources(rootbus);
  215. pci_bus_add_devices(rootbus);
  216. return 0;
  217. }
  218. subsys_initcall(mcf_pci_init);