m54xx.c 2.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100
  1. // SPDX-License-Identifier: GPL-2.0
  2. /***************************************************************************/
  3. /*
  4. * m54xx.c -- platform support for ColdFire 54xx based boards
  5. *
  6. * Copyright (C) 2010, Philippe De Muyter <[email protected]>
  7. */
  8. /***************************************************************************/
  9. #include <linux/clkdev.h>
  10. #include <linux/kernel.h>
  11. #include <linux/param.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/mm.h>
  16. #include <linux/clk.h>
  17. #include <linux/memblock.h>
  18. #include <asm/pgalloc.h>
  19. #include <asm/machdep.h>
  20. #include <asm/coldfire.h>
  21. #include <asm/m54xxsim.h>
  22. #include <asm/mcfuart.h>
  23. #include <asm/mcfclk.h>
  24. #include <asm/m54xxgpt.h>
  25. #ifdef CONFIG_MMU
  26. #include <asm/mmu_context.h>
  27. #endif
  28. /***************************************************************************/
  29. DEFINE_CLK(pll, "pll.0", MCF_CLK);
  30. DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  31. static struct clk_lookup m54xx_clk_lookup[] = {
  32. CLKDEV_INIT(NULL, "pll.0", &clk_pll),
  33. CLKDEV_INIT(NULL, "sys.0", &clk_sys),
  34. CLKDEV_INIT("mcfslt.0", NULL, &clk_sys),
  35. CLKDEV_INIT("mcfslt.1", NULL, &clk_sys),
  36. CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
  37. CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
  38. CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
  39. CLKDEV_INIT("mcfuart.3", NULL, &clk_sys),
  40. CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
  41. };
  42. /***************************************************************************/
  43. static void __init m54xx_uarts_init(void)
  44. {
  45. /* enable io pins */
  46. __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
  47. __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
  48. MCFGPIO_PAR_PSC1);
  49. __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
  50. MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
  51. __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
  52. }
  53. /***************************************************************************/
  54. static void __init m54xx_i2c_init(void)
  55. {
  56. #if IS_ENABLED(CONFIG_I2C_IMX)
  57. u32 r;
  58. /* set the fec/i2c/irq pin assignment register for i2c */
  59. r = readl(MCF_PAR_FECI2CIRQ);
  60. r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
  61. writel(r, MCF_PAR_FECI2CIRQ);
  62. #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  63. }
  64. /***************************************************************************/
  65. static void mcf54xx_reset(void)
  66. {
  67. /* disable interrupts and enable the watchdog */
  68. asm("movew #0x2700, %sr\n");
  69. __raw_writel(0, MCF_GPT_GMS0);
  70. __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
  71. __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
  72. MCF_GPT_GMS0);
  73. }
  74. /***************************************************************************/
  75. void __init config_BSP(char *commandp, int size)
  76. {
  77. mach_reset = mcf54xx_reset;
  78. mach_sched_init = hw_timer_init;
  79. m54xx_uarts_init();
  80. m54xx_i2c_init();
  81. clkdev_add_table(m54xx_clk_lookup, ARRAY_SIZE(m54xx_clk_lookup));
  82. }
  83. /***************************************************************************/