m527x.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /***************************************************************************/
  3. /*
  4. * m527x.c -- platform support for ColdFire 527x based boards
  5. *
  6. * Sub-architcture dependent initialization code for the Freescale
  7. * 5270/5271 and 5274/5275 CPUs.
  8. *
  9. * Copyright (C) 1999-2004, Greg Ungerer ([email protected])
  10. * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
  11. */
  12. /***************************************************************************/
  13. #include <linux/clkdev.h>
  14. #include <linux/kernel.h>
  15. #include <linux/param.h>
  16. #include <linux/init.h>
  17. #include <linux/io.h>
  18. #include <asm/machdep.h>
  19. #include <asm/coldfire.h>
  20. #include <asm/mcfsim.h>
  21. #include <asm/mcfuart.h>
  22. #include <asm/mcfclk.h>
  23. /***************************************************************************/
  24. DEFINE_CLK(pll, "pll.0", MCF_CLK);
  25. DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  26. static struct clk_lookup m527x_clk_lookup[] = {
  27. CLKDEV_INIT(NULL, "pll.0", &clk_pll),
  28. CLKDEV_INIT(NULL, "sys.0", &clk_sys),
  29. CLKDEV_INIT("mcfpit.0", NULL, &clk_pll),
  30. CLKDEV_INIT("mcfpit.1", NULL, &clk_pll),
  31. CLKDEV_INIT("mcfpit.2", NULL, &clk_pll),
  32. CLKDEV_INIT("mcfpit.3", NULL, &clk_pll),
  33. CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
  34. CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
  35. CLKDEV_INIT("mcfuart.2", NULL, &clk_sys),
  36. CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
  37. CLKDEV_INIT("fec.0", NULL, &clk_sys),
  38. CLKDEV_INIT("fec.1", NULL, &clk_sys),
  39. CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
  40. };
  41. /***************************************************************************/
  42. static void __init m527x_qspi_init(void)
  43. {
  44. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  45. #if defined(CONFIG_M5271)
  46. u16 par;
  47. /* setup QSPS pins for QSPI with gpio CS control */
  48. writeb(0x1f, MCFGPIO_PAR_QSPI);
  49. /* and CS2 & CS3 as gpio */
  50. par = readw(MCFGPIO_PAR_TIMER);
  51. par &= 0x3f3f;
  52. writew(par, MCFGPIO_PAR_TIMER);
  53. #elif defined(CONFIG_M5275)
  54. /* setup QSPS pins for QSPI with gpio CS control */
  55. writew(0x003e, MCFGPIO_PAR_QSPI);
  56. #endif
  57. #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  58. }
  59. /***************************************************************************/
  60. static void __init m527x_i2c_init(void)
  61. {
  62. #if IS_ENABLED(CONFIG_I2C_IMX)
  63. #if defined(CONFIG_M5271)
  64. u8 par;
  65. /* setup Port FECI2C Pin Assignment Register for I2C */
  66. /* set PAR_SCL to SCL and PAR_SDA to SDA */
  67. par = readb(MCFGPIO_PAR_FECI2C);
  68. par |= 0x0f;
  69. writeb(par, MCFGPIO_PAR_FECI2C);
  70. #elif defined(CONFIG_M5275)
  71. u16 par;
  72. /* setup Port FECI2C Pin Assignment Register for I2C */
  73. /* set PAR_SCL to SCL and PAR_SDA to SDA */
  74. par = readw(MCFGPIO_PAR_FECI2C);
  75. par |= 0x0f;
  76. writew(par, MCFGPIO_PAR_FECI2C);
  77. #endif
  78. #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  79. }
  80. /***************************************************************************/
  81. static void __init m527x_uarts_init(void)
  82. {
  83. u16 sepmask;
  84. /*
  85. * External Pin Mask Setting & Enable External Pin for Interface
  86. */
  87. sepmask = readw(MCFGPIO_PAR_UART);
  88. sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
  89. writew(sepmask, MCFGPIO_PAR_UART);
  90. }
  91. /***************************************************************************/
  92. static void __init m527x_fec_init(void)
  93. {
  94. u8 v;
  95. /* Set multi-function pins to ethernet mode for fec0 */
  96. #if defined(CONFIG_M5271)
  97. v = readb(MCFGPIO_PAR_FECI2C);
  98. writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
  99. #else
  100. u16 par;
  101. par = readw(MCFGPIO_PAR_FECI2C);
  102. writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
  103. v = readb(MCFGPIO_PAR_FEC0HL);
  104. writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
  105. /* Set multi-function pins to ethernet mode for fec1 */
  106. par = readw(MCFGPIO_PAR_FECI2C);
  107. writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
  108. v = readb(MCFGPIO_PAR_FEC1HL);
  109. writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
  110. #endif
  111. }
  112. /***************************************************************************/
  113. void __init config_BSP(char *commandp, int size)
  114. {
  115. mach_sched_init = hw_timer_init;
  116. m527x_uarts_init();
  117. m527x_fec_init();
  118. m527x_qspi_init();
  119. m527x_i2c_init();
  120. clkdev_add_table(m527x_clk_lookup, ARRAY_SIZE(m527x_clk_lookup));
  121. }
  122. /***************************************************************************/