m525x.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /***************************************************************************/
  3. /*
  4. * 525x.c -- platform support for ColdFire 525x based boards
  5. *
  6. * Copyright (C) 2012, Steven King <[email protected]>
  7. */
  8. /***************************************************************************/
  9. #include <linux/clkdev.h>
  10. #include <linux/kernel.h>
  11. #include <linux/param.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <asm/machdep.h>
  16. #include <asm/coldfire.h>
  17. #include <asm/mcfsim.h>
  18. #include <asm/mcfclk.h>
  19. /***************************************************************************/
  20. DEFINE_CLK(pll, "pll.0", MCF_CLK);
  21. DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
  22. static struct clk_lookup m525x_clk_lookup[] = {
  23. CLKDEV_INIT(NULL, "pll.0", &clk_pll),
  24. CLKDEV_INIT(NULL, "sys.0", &clk_sys),
  25. CLKDEV_INIT("mcftmr.0", NULL, &clk_sys),
  26. CLKDEV_INIT("mcftmr.1", NULL, &clk_sys),
  27. CLKDEV_INIT("mcfuart.0", NULL, &clk_sys),
  28. CLKDEV_INIT("mcfuart.1", NULL, &clk_sys),
  29. CLKDEV_INIT("mcfqspi.0", NULL, &clk_sys),
  30. CLKDEV_INIT("imx1-i2c.0", NULL, &clk_sys),
  31. CLKDEV_INIT("imx1-i2c.1", NULL, &clk_sys),
  32. };
  33. /***************************************************************************/
  34. static void __init m525x_qspi_init(void)
  35. {
  36. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  37. /* set the GPIO function for the qspi cs gpios */
  38. /* FIXME: replace with pinmux/pinctl support */
  39. u32 f = readl(MCFSIM2_GPIOFUNC);
  40. f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
  41. writel(f, MCFSIM2_GPIOFUNC);
  42. /* QSPI irq setup */
  43. writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
  44. MCFSIM_QSPIICR);
  45. mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
  46. #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  47. }
  48. static void __init m525x_i2c_init(void)
  49. {
  50. #if IS_ENABLED(CONFIG_I2C_IMX)
  51. u32 r;
  52. /* first I2C controller uses regular irq setup */
  53. writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
  54. MCFSIM_I2CICR);
  55. mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
  56. /* second I2C controller is completely different */
  57. r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  58. r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
  59. r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
  60. writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
  61. #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  62. }
  63. /***************************************************************************/
  64. void __init config_BSP(char *commandp, int size)
  65. {
  66. mach_sched_init = hw_timer_init;
  67. m525x_qspi_init();
  68. m525x_i2c_init();
  69. clkdev_add_table(m525x_clk_lookup, ARRAY_SIZE(m525x_clk_lookup));
  70. }
  71. /***************************************************************************/