m520x.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /***************************************************************************/
  3. /*
  4. * m520x.c -- platform support for ColdFire 520x based boards
  5. *
  6. * Copyright (C) 2005, Freescale (www.freescale.com)
  7. * Copyright (C) 2005, Intec Automation ([email protected])
  8. * Copyright (C) 1999-2007, Greg Ungerer ([email protected])
  9. * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
  10. */
  11. /***************************************************************************/
  12. #include <linux/clkdev.h>
  13. #include <linux/kernel.h>
  14. #include <linux/param.h>
  15. #include <linux/init.h>
  16. #include <linux/io.h>
  17. #include <asm/machdep.h>
  18. #include <asm/coldfire.h>
  19. #include <asm/mcfsim.h>
  20. #include <asm/mcfuart.h>
  21. #include <asm/mcfclk.h>
  22. /***************************************************************************/
  23. DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
  24. DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
  25. DEFINE_CLK(0, "edma", 17, MCF_CLK);
  26. DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
  27. DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
  28. DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
  29. DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
  30. DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
  31. DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
  32. DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
  33. DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
  34. DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
  35. DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
  36. DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
  37. DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
  38. DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
  39. DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
  40. DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
  41. DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
  42. DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
  43. DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
  44. DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
  45. static struct clk_lookup m520x_clk_lookup[] = {
  46. CLKDEV_INIT(NULL, "flexbus", &__clk_0_2),
  47. CLKDEV_INIT("fec.0", NULL, &__clk_0_12),
  48. CLKDEV_INIT("edma", NULL, &__clk_0_17),
  49. CLKDEV_INIT("intc.0", NULL, &__clk_0_18),
  50. CLKDEV_INIT("iack.0", NULL, &__clk_0_21),
  51. CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
  52. CLKDEV_INIT("mcfqspi.0", NULL, &__clk_0_23),
  53. CLKDEV_INIT("mcfuart.0", NULL, &__clk_0_24),
  54. CLKDEV_INIT("mcfuart.1", NULL, &__clk_0_25),
  55. CLKDEV_INIT("mcfuart.2", NULL, &__clk_0_26),
  56. CLKDEV_INIT("mcftmr.0", NULL, &__clk_0_28),
  57. CLKDEV_INIT("mcftmr.1", NULL, &__clk_0_29),
  58. CLKDEV_INIT("mcftmr.2", NULL, &__clk_0_30),
  59. CLKDEV_INIT("mcftmr.3", NULL, &__clk_0_31),
  60. CLKDEV_INIT("mcfpit.0", NULL, &__clk_0_32),
  61. CLKDEV_INIT("mcfpit.1", NULL, &__clk_0_33),
  62. CLKDEV_INIT("mcfeport.0", NULL, &__clk_0_34),
  63. CLKDEV_INIT("mcfwdt.0", NULL, &__clk_0_35),
  64. CLKDEV_INIT(NULL, "pll.0", &__clk_0_36),
  65. CLKDEV_INIT(NULL, "sys.0", &__clk_0_40),
  66. CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
  67. CLKDEV_INIT("sdram.0", NULL, &__clk_0_42),
  68. };
  69. static struct clk * const enable_clks[] __initconst = {
  70. &__clk_0_2, /* flexbus */
  71. &__clk_0_18, /* intc.0 */
  72. &__clk_0_21, /* iack.0 */
  73. &__clk_0_24, /* mcfuart.0 */
  74. &__clk_0_25, /* mcfuart.1 */
  75. &__clk_0_26, /* mcfuart.2 */
  76. &__clk_0_32, /* mcfpit.0 */
  77. &__clk_0_33, /* mcfpit.1 */
  78. &__clk_0_34, /* mcfeport.0 */
  79. &__clk_0_36, /* pll.0 */
  80. &__clk_0_40, /* sys.0 */
  81. &__clk_0_41, /* gpio.0 */
  82. &__clk_0_42, /* sdram.0 */
  83. };
  84. static struct clk * const disable_clks[] __initconst = {
  85. &__clk_0_12, /* fec.0 */
  86. &__clk_0_17, /* edma */
  87. &__clk_0_22, /* imx1-i2c.0 */
  88. &__clk_0_23, /* mcfqspi.0 */
  89. &__clk_0_28, /* mcftmr.0 */
  90. &__clk_0_29, /* mcftmr.1 */
  91. &__clk_0_30, /* mcftmr.2 */
  92. &__clk_0_31, /* mcftmr.3 */
  93. &__clk_0_35, /* mcfwdt.0 */
  94. };
  95. static void __init m520x_clk_init(void)
  96. {
  97. unsigned i;
  98. /* make sure these clocks are enabled */
  99. for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
  100. __clk_init_enabled(enable_clks[i]);
  101. /* make sure these clocks are disabled */
  102. for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
  103. __clk_init_disabled(disable_clks[i]);
  104. clkdev_add_table(m520x_clk_lookup, ARRAY_SIZE(m520x_clk_lookup));
  105. }
  106. /***************************************************************************/
  107. static void __init m520x_qspi_init(void)
  108. {
  109. #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
  110. u16 par;
  111. /* setup Port QS for QSPI with gpio CS control */
  112. writeb(0x3f, MCF_GPIO_PAR_QSPI);
  113. /* make U1CTS and U2RTS gpio for cs_control */
  114. par = readw(MCF_GPIO_PAR_UART);
  115. par &= 0x00ff;
  116. writew(par, MCF_GPIO_PAR_UART);
  117. #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
  118. }
  119. /***************************************************************************/
  120. static void __init m520x_i2c_init(void)
  121. {
  122. #if IS_ENABLED(CONFIG_I2C_IMX)
  123. u8 par;
  124. /* setup Port FECI2C Pin Assignment Register for I2C */
  125. /* set PAR_SCL to SCL and PAR_SDA to SDA */
  126. par = readb(MCF_GPIO_PAR_FECI2C);
  127. par |= 0x0f;
  128. writeb(par, MCF_GPIO_PAR_FECI2C);
  129. #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
  130. }
  131. /***************************************************************************/
  132. static void __init m520x_uarts_init(void)
  133. {
  134. u16 par;
  135. u8 par2;
  136. /* UART0 and UART1 GPIO pin setup */
  137. par = readw(MCF_GPIO_PAR_UART);
  138. par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
  139. par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
  140. writew(par, MCF_GPIO_PAR_UART);
  141. /* UART1 GPIO pin setup */
  142. par2 = readb(MCF_GPIO_PAR_FECI2C);
  143. par2 &= ~0x0F;
  144. par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
  145. MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
  146. writeb(par2, MCF_GPIO_PAR_FECI2C);
  147. }
  148. /***************************************************************************/
  149. static void __init m520x_fec_init(void)
  150. {
  151. u8 v;
  152. /* Set multi-function pins to ethernet mode */
  153. v = readb(MCF_GPIO_PAR_FEC);
  154. writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
  155. v = readb(MCF_GPIO_PAR_FECI2C);
  156. writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
  157. }
  158. /***************************************************************************/
  159. void __init config_BSP(char *commandp, int size)
  160. {
  161. mach_sched_init = hw_timer_init;
  162. m520x_clk_init();
  163. m520x_uarts_init();
  164. m520x_fec_init();
  165. m520x_qspi_init();
  166. m520x_i2c_init();
  167. }
  168. /***************************************************************************/