clk.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /***************************************************************************/
  3. /*
  4. * clk.c -- general ColdFire CPU kernel clk handling
  5. *
  6. * Copyright (C) 2009, Greg Ungerer ([email protected])
  7. */
  8. /***************************************************************************/
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/mutex.h>
  13. #include <linux/clk.h>
  14. #include <linux/io.h>
  15. #include <linux/err.h>
  16. #include <asm/coldfire.h>
  17. #include <asm/mcfsim.h>
  18. #include <asm/mcfclk.h>
  19. static DEFINE_SPINLOCK(clk_lock);
  20. #ifdef MCFPM_PPMCR0
  21. /*
  22. * For more advanced ColdFire parts that have clocks that can be enabled
  23. * we supply enable/disable functions. These must properly define their
  24. * clocks in their platform specific code.
  25. */
  26. void __clk_init_enabled(struct clk *clk)
  27. {
  28. clk->enabled = 1;
  29. clk->clk_ops->enable(clk);
  30. }
  31. void __clk_init_disabled(struct clk *clk)
  32. {
  33. clk->enabled = 0;
  34. clk->clk_ops->disable(clk);
  35. }
  36. static void __clk_enable0(struct clk *clk)
  37. {
  38. __raw_writeb(clk->slot, MCFPM_PPMCR0);
  39. }
  40. static void __clk_disable0(struct clk *clk)
  41. {
  42. __raw_writeb(clk->slot, MCFPM_PPMSR0);
  43. }
  44. struct clk_ops clk_ops0 = {
  45. .enable = __clk_enable0,
  46. .disable = __clk_disable0,
  47. };
  48. #ifdef MCFPM_PPMCR1
  49. static void __clk_enable1(struct clk *clk)
  50. {
  51. __raw_writeb(clk->slot, MCFPM_PPMCR1);
  52. }
  53. static void __clk_disable1(struct clk *clk)
  54. {
  55. __raw_writeb(clk->slot, MCFPM_PPMSR1);
  56. }
  57. struct clk_ops clk_ops1 = {
  58. .enable = __clk_enable1,
  59. .disable = __clk_disable1,
  60. };
  61. #endif /* MCFPM_PPMCR1 */
  62. #endif /* MCFPM_PPMCR0 */
  63. int clk_enable(struct clk *clk)
  64. {
  65. unsigned long flags;
  66. if (!clk)
  67. return 0;
  68. spin_lock_irqsave(&clk_lock, flags);
  69. if ((clk->enabled++ == 0) && clk->clk_ops)
  70. clk->clk_ops->enable(clk);
  71. spin_unlock_irqrestore(&clk_lock, flags);
  72. return 0;
  73. }
  74. EXPORT_SYMBOL(clk_enable);
  75. void clk_disable(struct clk *clk)
  76. {
  77. unsigned long flags;
  78. if (!clk)
  79. return;
  80. spin_lock_irqsave(&clk_lock, flags);
  81. if ((--clk->enabled == 0) && clk->clk_ops)
  82. clk->clk_ops->disable(clk);
  83. spin_unlock_irqrestore(&clk_lock, flags);
  84. }
  85. EXPORT_SYMBOL(clk_disable);
  86. unsigned long clk_get_rate(struct clk *clk)
  87. {
  88. if (!clk)
  89. return 0;
  90. return clk->rate;
  91. }
  92. EXPORT_SYMBOL(clk_get_rate);
  93. /* dummy functions, should not be called */
  94. long clk_round_rate(struct clk *clk, unsigned long rate)
  95. {
  96. WARN_ON(clk);
  97. return 0;
  98. }
  99. EXPORT_SYMBOL(clk_round_rate);
  100. int clk_set_rate(struct clk *clk, unsigned long rate)
  101. {
  102. WARN_ON(clk);
  103. return 0;
  104. }
  105. EXPORT_SYMBOL(clk_set_rate);
  106. int clk_set_parent(struct clk *clk, struct clk *parent)
  107. {
  108. WARN_ON(clk);
  109. return 0;
  110. }
  111. EXPORT_SYMBOL(clk_set_parent);
  112. struct clk *clk_get_parent(struct clk *clk)
  113. {
  114. WARN_ON(clk);
  115. return NULL;
  116. }
  117. EXPORT_SYMBOL(clk_get_parent);
  118. /***************************************************************************/