dragen2.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 1993 Hamish Macdonald
  4. * Copyright (C) 1999 D. Jeff Dionne
  5. * Copyright (C) 2001 Georges Menie, Ken Desmet
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive
  9. * for more details.
  10. */
  11. #include <linux/init.h>
  12. #include <asm/machdep.h>
  13. #include <asm/MC68VZ328.h>
  14. #include "m68328.h"
  15. #include "screen.h"
  16. /***************************************************************************/
  17. /* Init Drangon Engine hardware */
  18. /***************************************************************************/
  19. static void dragen2_reset(void)
  20. {
  21. local_irq_disable();
  22. #ifdef CONFIG_INIT_LCD
  23. PBDATA |= 0x20; /* disable CCFL light */
  24. PKDATA |= 0x4; /* disable LCD controller */
  25. LCKCON = 0;
  26. #endif
  27. __asm__ __volatile__(
  28. "reset\n\t"
  29. "moveal #0x04000000, %a0\n\t"
  30. "moveal 0(%a0), %sp\n\t"
  31. "moveal 4(%a0), %a0\n\t"
  32. "jmp (%a0)"
  33. );
  34. }
  35. void __init init_dragen2(char *command, int size)
  36. {
  37. mach_reset = dragen2_reset;
  38. #ifdef CONFIG_DIRECT_IO_ACCESS
  39. SCR = 0x10; /* allow user access to internal registers */
  40. #endif
  41. /* CSGB Init */
  42. CSGBB = 0x4000;
  43. CSB = 0x1a1;
  44. /* CS8900 init */
  45. /* PK3: hardware sleep function pin, active low */
  46. PKSEL |= PK(3); /* select pin as I/O */
  47. PKDIR |= PK(3); /* select pin as output */
  48. PKDATA |= PK(3); /* set pin high */
  49. /* PF5: hardware reset function pin, active high */
  50. PFSEL |= PF(5); /* select pin as I/O */
  51. PFDIR |= PF(5); /* select pin as output */
  52. PFDATA &= ~PF(5); /* set pin low */
  53. /* cs8900 hardware reset */
  54. PFDATA |= PF(5);
  55. { int i; for (i = 0; i < 32000; ++i); }
  56. PFDATA &= ~PF(5);
  57. /* INT1 enable (cs8900 IRQ) */
  58. PDPOL &= ~PD(1); /* active high signal */
  59. PDIQEG &= ~PD(1);
  60. PDIRQEN |= PD(1); /* IRQ enabled */
  61. #ifdef CONFIG_INIT_LCD
  62. /* initialize LCD controller */
  63. LSSA = (long) screen_bits;
  64. LVPW = 0x14;
  65. LXMAX = 0x140;
  66. LYMAX = 0xef;
  67. LRRA = 0;
  68. LPXCD = 3;
  69. LPICF = 0x08;
  70. LPOLCF = 0;
  71. LCKCON = 0x80;
  72. PCPDEN = 0xff;
  73. PCSEL = 0;
  74. /* Enable LCD controller */
  75. PKDIR |= 0x4;
  76. PKSEL |= 0x4;
  77. PKDATA &= ~0x4;
  78. /* Enable CCFL backlighting circuit */
  79. PBDIR |= 0x20;
  80. PBSEL |= 0x20;
  81. PBDATA &= ~0x20;
  82. /* contrast control register */
  83. PFDIR |= 0x1;
  84. PFSEL &= ~0x1;
  85. PWMR = 0x037F;
  86. #endif
  87. }