smpboot.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * SMP boot-related support
  4. *
  5. * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
  6. * David Mosberger-Tang <[email protected]>
  7. * Copyright (C) 2001, 2004-2005 Intel Corp
  8. * Rohit Seth <[email protected]>
  9. * Suresh Siddha <[email protected]>
  10. * Gordon Jin <[email protected]>
  11. * Ashok Raj <[email protected]>
  12. *
  13. * 01/05/16 Rohit Seth <[email protected]> Moved SMP booting functions from smp.c to here.
  14. * 01/04/27 David Mosberger <[email protected]> Added ITC synching code.
  15. * 02/07/31 David Mosberger <[email protected]> Switch over to hotplug-CPU boot-sequence.
  16. * smp_boot_cpus()/smp_commence() is replaced by
  17. * smp_prepare_cpus()/__cpu_up()/smp_cpus_done().
  18. * 04/06/21 Ashok Raj <[email protected]> Added CPU Hotplug Support
  19. * 04/12/26 Jin Gordon <[email protected]>
  20. * 04/12/26 Rohit Seth <[email protected]>
  21. * Add multi-threading and multi-core detection
  22. * 05/01/30 Suresh Siddha <[email protected]>
  23. * Setup cpu_sibling_map and cpu_core_map
  24. */
  25. #include <linux/module.h>
  26. #include <linux/acpi.h>
  27. #include <linux/memblock.h>
  28. #include <linux/cpu.h>
  29. #include <linux/delay.h>
  30. #include <linux/init.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/irq.h>
  33. #include <linux/kernel.h>
  34. #include <linux/kernel_stat.h>
  35. #include <linux/mm.h>
  36. #include <linux/notifier.h>
  37. #include <linux/smp.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/efi.h>
  40. #include <linux/percpu.h>
  41. #include <linux/bitops.h>
  42. #include <linux/atomic.h>
  43. #include <asm/cache.h>
  44. #include <asm/current.h>
  45. #include <asm/delay.h>
  46. #include <asm/efi.h>
  47. #include <asm/io.h>
  48. #include <asm/irq.h>
  49. #include <asm/mca.h>
  50. #include <asm/page.h>
  51. #include <asm/processor.h>
  52. #include <asm/ptrace.h>
  53. #include <asm/sal.h>
  54. #include <asm/tlbflush.h>
  55. #include <asm/unistd.h>
  56. #define SMP_DEBUG 0
  57. #if SMP_DEBUG
  58. #define Dprintk(x...) printk(x)
  59. #else
  60. #define Dprintk(x...)
  61. #endif
  62. #ifdef CONFIG_HOTPLUG_CPU
  63. #ifdef CONFIG_PERMIT_BSP_REMOVE
  64. #define bsp_remove_ok 1
  65. #else
  66. #define bsp_remove_ok 0
  67. #endif
  68. /*
  69. * Global array allocated for NR_CPUS at boot time
  70. */
  71. struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
  72. /*
  73. * start_ap in head.S uses this to store current booting cpu
  74. * info.
  75. */
  76. struct sal_to_os_boot *sal_state_for_booting_cpu = &sal_boot_rendez_state[0];
  77. #define set_brendez_area(x) (sal_state_for_booting_cpu = &sal_boot_rendez_state[(x)]);
  78. #else
  79. #define set_brendez_area(x)
  80. #endif
  81. /*
  82. * ITC synchronization related stuff:
  83. */
  84. #define MASTER (0)
  85. #define SLAVE (SMP_CACHE_BYTES/8)
  86. #define NUM_ROUNDS 64 /* magic value */
  87. #define NUM_ITERS 5 /* likewise */
  88. static DEFINE_SPINLOCK(itc_sync_lock);
  89. static volatile unsigned long go[SLAVE + 1];
  90. #define DEBUG_ITC_SYNC 0
  91. extern void start_ap (void);
  92. extern unsigned long ia64_iobase;
  93. struct task_struct *task_for_booting_cpu;
  94. /*
  95. * State for each CPU
  96. */
  97. DEFINE_PER_CPU(int, cpu_state);
  98. cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
  99. EXPORT_SYMBOL(cpu_core_map);
  100. DEFINE_PER_CPU_SHARED_ALIGNED(cpumask_t, cpu_sibling_map);
  101. EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  102. int smp_num_siblings = 1;
  103. /* which logical CPU number maps to which CPU (physical APIC ID) */
  104. volatile int ia64_cpu_to_sapicid[NR_CPUS];
  105. EXPORT_SYMBOL(ia64_cpu_to_sapicid);
  106. static cpumask_t cpu_callin_map;
  107. struct smp_boot_data smp_boot_data __initdata;
  108. unsigned long ap_wakeup_vector = -1; /* External Int use to wakeup APs */
  109. char __initdata no_int_routing;
  110. unsigned char smp_int_redirect; /* are INT and IPI redirectable by the chipset? */
  111. #ifdef CONFIG_FORCE_CPEI_RETARGET
  112. #define CPEI_OVERRIDE_DEFAULT (1)
  113. #else
  114. #define CPEI_OVERRIDE_DEFAULT (0)
  115. #endif
  116. unsigned int force_cpei_retarget = CPEI_OVERRIDE_DEFAULT;
  117. static int __init
  118. cmdl_force_cpei(char *str)
  119. {
  120. int value=0;
  121. get_option (&str, &value);
  122. force_cpei_retarget = value;
  123. return 1;
  124. }
  125. __setup("force_cpei=", cmdl_force_cpei);
  126. static int __init
  127. nointroute (char *str)
  128. {
  129. no_int_routing = 1;
  130. printk ("no_int_routing on\n");
  131. return 1;
  132. }
  133. __setup("nointroute", nointroute);
  134. static void fix_b0_for_bsp(void)
  135. {
  136. #ifdef CONFIG_HOTPLUG_CPU
  137. int cpuid;
  138. static int fix_bsp_b0 = 1;
  139. cpuid = smp_processor_id();
  140. /*
  141. * Cache the b0 value on the first AP that comes up
  142. */
  143. if (!(fix_bsp_b0 && cpuid))
  144. return;
  145. sal_boot_rendez_state[0].br[0] = sal_boot_rendez_state[cpuid].br[0];
  146. printk ("Fixed BSP b0 value from CPU %d\n", cpuid);
  147. fix_bsp_b0 = 0;
  148. #endif
  149. }
  150. void
  151. sync_master (void *arg)
  152. {
  153. unsigned long flags, i;
  154. go[MASTER] = 0;
  155. local_irq_save(flags);
  156. {
  157. for (i = 0; i < NUM_ROUNDS*NUM_ITERS; ++i) {
  158. while (!go[MASTER])
  159. cpu_relax();
  160. go[MASTER] = 0;
  161. go[SLAVE] = ia64_get_itc();
  162. }
  163. }
  164. local_irq_restore(flags);
  165. }
  166. /*
  167. * Return the number of cycles by which our itc differs from the itc on the master
  168. * (time-keeper) CPU. A positive number indicates our itc is ahead of the master,
  169. * negative that it is behind.
  170. */
  171. static inline long
  172. get_delta (long *rt, long *master)
  173. {
  174. unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
  175. unsigned long tcenter, t0, t1, tm;
  176. long i;
  177. for (i = 0; i < NUM_ITERS; ++i) {
  178. t0 = ia64_get_itc();
  179. go[MASTER] = 1;
  180. while (!(tm = go[SLAVE]))
  181. cpu_relax();
  182. go[SLAVE] = 0;
  183. t1 = ia64_get_itc();
  184. if (t1 - t0 < best_t1 - best_t0)
  185. best_t0 = t0, best_t1 = t1, best_tm = tm;
  186. }
  187. *rt = best_t1 - best_t0;
  188. *master = best_tm - best_t0;
  189. /* average best_t0 and best_t1 without overflow: */
  190. tcenter = (best_t0/2 + best_t1/2);
  191. if (best_t0 % 2 + best_t1 % 2 == 2)
  192. ++tcenter;
  193. return tcenter - best_tm;
  194. }
  195. /*
  196. * Synchronize ar.itc of the current (slave) CPU with the ar.itc of the MASTER CPU
  197. * (normally the time-keeper CPU). We use a closed loop to eliminate the possibility of
  198. * unaccounted-for errors (such as getting a machine check in the middle of a calibration
  199. * step). The basic idea is for the slave to ask the master what itc value it has and to
  200. * read its own itc before and after the master responds. Each iteration gives us three
  201. * timestamps:
  202. *
  203. * slave master
  204. *
  205. * t0 ---\
  206. * ---\
  207. * --->
  208. * tm
  209. * /---
  210. * /---
  211. * t1 <---
  212. *
  213. *
  214. * The goal is to adjust the slave's ar.itc such that tm falls exactly half-way between t0
  215. * and t1. If we achieve this, the clocks are synchronized provided the interconnect
  216. * between the slave and the master is symmetric. Even if the interconnect were
  217. * asymmetric, we would still know that the synchronization error is smaller than the
  218. * roundtrip latency (t0 - t1).
  219. *
  220. * When the interconnect is quiet and symmetric, this lets us synchronize the itc to
  221. * within one or two cycles. However, we can only *guarantee* that the synchronization is
  222. * accurate to within a round-trip time, which is typically in the range of several
  223. * hundred cycles (e.g., ~500 cycles). In practice, this means that the itc's are usually
  224. * almost perfectly synchronized, but we shouldn't assume that the accuracy is much better
  225. * than half a micro second or so.
  226. */
  227. void
  228. ia64_sync_itc (unsigned int master)
  229. {
  230. long i, delta, adj, adjust_latency = 0, done = 0;
  231. unsigned long flags, rt, master_time_stamp, bound;
  232. #if DEBUG_ITC_SYNC
  233. struct {
  234. long rt; /* roundtrip time */
  235. long master; /* master's timestamp */
  236. long diff; /* difference between midpoint and master's timestamp */
  237. long lat; /* estimate of itc adjustment latency */
  238. } t[NUM_ROUNDS];
  239. #endif
  240. /*
  241. * Make sure local timer ticks are disabled while we sync. If
  242. * they were enabled, we'd have to worry about nasty issues
  243. * like setting the ITC ahead of (or a long time before) the
  244. * next scheduled tick.
  245. */
  246. BUG_ON((ia64_get_itv() & (1 << 16)) == 0);
  247. go[MASTER] = 1;
  248. if (smp_call_function_single(master, sync_master, NULL, 0) < 0) {
  249. printk(KERN_ERR "sync_itc: failed to get attention of CPU %u!\n", master);
  250. return;
  251. }
  252. while (go[MASTER])
  253. cpu_relax(); /* wait for master to be ready */
  254. spin_lock_irqsave(&itc_sync_lock, flags);
  255. {
  256. for (i = 0; i < NUM_ROUNDS; ++i) {
  257. delta = get_delta(&rt, &master_time_stamp);
  258. if (delta == 0) {
  259. done = 1; /* let's lock on to this... */
  260. bound = rt;
  261. }
  262. if (!done) {
  263. if (i > 0) {
  264. adjust_latency += -delta;
  265. adj = -delta + adjust_latency/4;
  266. } else
  267. adj = -delta;
  268. ia64_set_itc(ia64_get_itc() + adj);
  269. }
  270. #if DEBUG_ITC_SYNC
  271. t[i].rt = rt;
  272. t[i].master = master_time_stamp;
  273. t[i].diff = delta;
  274. t[i].lat = adjust_latency/4;
  275. #endif
  276. }
  277. }
  278. spin_unlock_irqrestore(&itc_sync_lock, flags);
  279. #if DEBUG_ITC_SYNC
  280. for (i = 0; i < NUM_ROUNDS; ++i)
  281. printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
  282. t[i].rt, t[i].master, t[i].diff, t[i].lat);
  283. #endif
  284. printk(KERN_INFO "CPU %d: synchronized ITC with CPU %u (last diff %ld cycles, "
  285. "maxerr %lu cycles)\n", smp_processor_id(), master, delta, rt);
  286. }
  287. /*
  288. * Ideally sets up per-cpu profiling hooks. Doesn't do much now...
  289. */
  290. static inline void smp_setup_percpu_timer(void)
  291. {
  292. }
  293. static void
  294. smp_callin (void)
  295. {
  296. int cpuid, phys_id, itc_master;
  297. struct cpuinfo_ia64 *last_cpuinfo, *this_cpuinfo;
  298. extern void ia64_init_itm(void);
  299. extern volatile int time_keeper_id;
  300. cpuid = smp_processor_id();
  301. phys_id = hard_smp_processor_id();
  302. itc_master = time_keeper_id;
  303. if (cpu_online(cpuid)) {
  304. printk(KERN_ERR "huh, phys CPU#0x%x, CPU#0x%x already present??\n",
  305. phys_id, cpuid);
  306. BUG();
  307. }
  308. fix_b0_for_bsp();
  309. /*
  310. * numa_node_id() works after this.
  311. */
  312. set_numa_node(cpu_to_node_map[cpuid]);
  313. set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
  314. spin_lock(&vector_lock);
  315. /* Setup the per cpu irq handling data structures */
  316. __setup_vector_irq(cpuid);
  317. notify_cpu_starting(cpuid);
  318. set_cpu_online(cpuid, true);
  319. per_cpu(cpu_state, cpuid) = CPU_ONLINE;
  320. spin_unlock(&vector_lock);
  321. smp_setup_percpu_timer();
  322. ia64_mca_cmc_vector_setup(); /* Setup vector on AP */
  323. local_irq_enable();
  324. if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
  325. /*
  326. * Synchronize the ITC with the BP. Need to do this after irqs are
  327. * enabled because ia64_sync_itc() calls smp_call_function_single(), which
  328. * calls spin_unlock_bh(), which calls spin_unlock_bh(), which calls
  329. * local_bh_enable(), which bugs out if irqs are not enabled...
  330. */
  331. Dprintk("Going to syncup ITC with ITC Master.\n");
  332. ia64_sync_itc(itc_master);
  333. }
  334. /*
  335. * Get our bogomips.
  336. */
  337. ia64_init_itm();
  338. /*
  339. * Delay calibration can be skipped if new processor is identical to the
  340. * previous processor.
  341. */
  342. last_cpuinfo = cpu_data(cpuid - 1);
  343. this_cpuinfo = local_cpu_data;
  344. if (last_cpuinfo->itc_freq != this_cpuinfo->itc_freq ||
  345. last_cpuinfo->proc_freq != this_cpuinfo->proc_freq ||
  346. last_cpuinfo->features != this_cpuinfo->features ||
  347. last_cpuinfo->revision != this_cpuinfo->revision ||
  348. last_cpuinfo->family != this_cpuinfo->family ||
  349. last_cpuinfo->archrev != this_cpuinfo->archrev ||
  350. last_cpuinfo->model != this_cpuinfo->model)
  351. calibrate_delay();
  352. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  353. /*
  354. * Allow the master to continue.
  355. */
  356. cpumask_set_cpu(cpuid, &cpu_callin_map);
  357. Dprintk("Stack on CPU %d at about %p\n",cpuid, &cpuid);
  358. }
  359. /*
  360. * Activate a secondary processor. head.S calls this.
  361. */
  362. int
  363. start_secondary (void *unused)
  364. {
  365. /* Early console may use I/O ports */
  366. ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
  367. #ifndef CONFIG_PRINTK_TIME
  368. Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
  369. #endif
  370. efi_map_pal_code();
  371. cpu_init();
  372. smp_callin();
  373. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  374. return 0;
  375. }
  376. static int
  377. do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
  378. {
  379. int timeout;
  380. task_for_booting_cpu = idle;
  381. Dprintk("Sending wakeup vector %lu to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
  382. set_brendez_area(cpu);
  383. ia64_send_ipi(cpu, ap_wakeup_vector, IA64_IPI_DM_INT, 0);
  384. /*
  385. * Wait 10s total for the AP to start
  386. */
  387. Dprintk("Waiting on callin_map ...");
  388. for (timeout = 0; timeout < 100000; timeout++) {
  389. if (cpumask_test_cpu(cpu, &cpu_callin_map))
  390. break; /* It has booted */
  391. barrier(); /* Make sure we re-read cpu_callin_map */
  392. udelay(100);
  393. }
  394. Dprintk("\n");
  395. if (!cpumask_test_cpu(cpu, &cpu_callin_map)) {
  396. printk(KERN_ERR "Processor 0x%x/0x%x is stuck.\n", cpu, sapicid);
  397. ia64_cpu_to_sapicid[cpu] = -1;
  398. set_cpu_online(cpu, false); /* was set in smp_callin() */
  399. return -EINVAL;
  400. }
  401. return 0;
  402. }
  403. static int __init
  404. decay (char *str)
  405. {
  406. int ticks;
  407. get_option (&str, &ticks);
  408. return 1;
  409. }
  410. __setup("decay=", decay);
  411. /*
  412. * Initialize the logical CPU number to SAPICID mapping
  413. */
  414. void __init
  415. smp_build_cpu_map (void)
  416. {
  417. int sapicid, cpu, i;
  418. int boot_cpu_id = hard_smp_processor_id();
  419. for (cpu = 0; cpu < NR_CPUS; cpu++) {
  420. ia64_cpu_to_sapicid[cpu] = -1;
  421. }
  422. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  423. init_cpu_present(cpumask_of(0));
  424. set_cpu_possible(0, true);
  425. for (cpu = 1, i = 0; i < smp_boot_data.cpu_count; i++) {
  426. sapicid = smp_boot_data.cpu_phys_id[i];
  427. if (sapicid == boot_cpu_id)
  428. continue;
  429. set_cpu_present(cpu, true);
  430. set_cpu_possible(cpu, true);
  431. ia64_cpu_to_sapicid[cpu] = sapicid;
  432. cpu++;
  433. }
  434. }
  435. /*
  436. * Cycle through the APs sending Wakeup IPIs to boot each.
  437. */
  438. void __init
  439. smp_prepare_cpus (unsigned int max_cpus)
  440. {
  441. int boot_cpu_id = hard_smp_processor_id();
  442. /*
  443. * Initialize the per-CPU profiling counter/multiplier
  444. */
  445. smp_setup_percpu_timer();
  446. cpumask_set_cpu(0, &cpu_callin_map);
  447. local_cpu_data->loops_per_jiffy = loops_per_jiffy;
  448. ia64_cpu_to_sapicid[0] = boot_cpu_id;
  449. printk(KERN_INFO "Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
  450. current_thread_info()->cpu = 0;
  451. /*
  452. * If SMP should be disabled, then really disable it!
  453. */
  454. if (!max_cpus) {
  455. printk(KERN_INFO "SMP mode deactivated.\n");
  456. init_cpu_online(cpumask_of(0));
  457. init_cpu_present(cpumask_of(0));
  458. init_cpu_possible(cpumask_of(0));
  459. return;
  460. }
  461. }
  462. void smp_prepare_boot_cpu(void)
  463. {
  464. set_cpu_online(smp_processor_id(), true);
  465. cpumask_set_cpu(smp_processor_id(), &cpu_callin_map);
  466. set_numa_node(cpu_to_node_map[smp_processor_id()]);
  467. per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
  468. }
  469. #ifdef CONFIG_HOTPLUG_CPU
  470. static inline void
  471. clear_cpu_sibling_map(int cpu)
  472. {
  473. int i;
  474. for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
  475. cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
  476. for_each_cpu(i, &cpu_core_map[cpu])
  477. cpumask_clear_cpu(cpu, &cpu_core_map[i]);
  478. per_cpu(cpu_sibling_map, cpu) = cpu_core_map[cpu] = CPU_MASK_NONE;
  479. }
  480. static void
  481. remove_siblinginfo(int cpu)
  482. {
  483. if (cpu_data(cpu)->threads_per_core == 1 &&
  484. cpu_data(cpu)->cores_per_socket == 1) {
  485. cpumask_clear_cpu(cpu, &cpu_core_map[cpu]);
  486. cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, cpu));
  487. return;
  488. }
  489. /* remove it from all sibling map's */
  490. clear_cpu_sibling_map(cpu);
  491. }
  492. extern void fixup_irqs(void);
  493. int migrate_platform_irqs(unsigned int cpu)
  494. {
  495. int new_cpei_cpu;
  496. struct irq_data *data = NULL;
  497. const struct cpumask *mask;
  498. int retval = 0;
  499. /*
  500. * dont permit CPEI target to removed.
  501. */
  502. if (cpe_vector > 0 && is_cpu_cpei_target(cpu)) {
  503. printk ("CPU (%d) is CPEI Target\n", cpu);
  504. if (can_cpei_retarget()) {
  505. /*
  506. * Now re-target the CPEI to a different processor
  507. */
  508. new_cpei_cpu = cpumask_any(cpu_online_mask);
  509. mask = cpumask_of(new_cpei_cpu);
  510. set_cpei_target_cpu(new_cpei_cpu);
  511. data = irq_get_irq_data(ia64_cpe_irq);
  512. /*
  513. * Switch for now, immediately, we need to do fake intr
  514. * as other interrupts, but need to study CPEI behaviour with
  515. * polling before making changes.
  516. */
  517. if (data && data->chip) {
  518. data->chip->irq_disable(data);
  519. data->chip->irq_set_affinity(data, mask, false);
  520. data->chip->irq_enable(data);
  521. printk ("Re-targeting CPEI to cpu %d\n", new_cpei_cpu);
  522. }
  523. }
  524. if (!data) {
  525. printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
  526. retval = -EBUSY;
  527. }
  528. }
  529. return retval;
  530. }
  531. /* must be called with cpucontrol mutex held */
  532. int __cpu_disable(void)
  533. {
  534. int cpu = smp_processor_id();
  535. /*
  536. * dont permit boot processor for now
  537. */
  538. if (cpu == 0 && !bsp_remove_ok) {
  539. printk ("Your platform does not support removal of BSP\n");
  540. return (-EBUSY);
  541. }
  542. set_cpu_online(cpu, false);
  543. if (migrate_platform_irqs(cpu)) {
  544. set_cpu_online(cpu, true);
  545. return -EBUSY;
  546. }
  547. remove_siblinginfo(cpu);
  548. fixup_irqs();
  549. local_flush_tlb_all();
  550. cpumask_clear_cpu(cpu, &cpu_callin_map);
  551. return 0;
  552. }
  553. void __cpu_die(unsigned int cpu)
  554. {
  555. unsigned int i;
  556. for (i = 0; i < 100; i++) {
  557. /* They ack this in play_dead by setting CPU_DEAD */
  558. if (per_cpu(cpu_state, cpu) == CPU_DEAD)
  559. {
  560. printk ("CPU %d is now offline\n", cpu);
  561. return;
  562. }
  563. msleep(100);
  564. }
  565. printk(KERN_ERR "CPU %u didn't die...\n", cpu);
  566. }
  567. #endif /* CONFIG_HOTPLUG_CPU */
  568. void
  569. smp_cpus_done (unsigned int dummy)
  570. {
  571. int cpu;
  572. unsigned long bogosum = 0;
  573. /*
  574. * Allow the user to impress friends.
  575. */
  576. for_each_online_cpu(cpu) {
  577. bogosum += cpu_data(cpu)->loops_per_jiffy;
  578. }
  579. printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
  580. (int)num_online_cpus(), bogosum/(500000/HZ), (bogosum/(5000/HZ))%100);
  581. }
  582. static inline void set_cpu_sibling_map(int cpu)
  583. {
  584. int i;
  585. for_each_online_cpu(i) {
  586. if ((cpu_data(cpu)->socket_id == cpu_data(i)->socket_id)) {
  587. cpumask_set_cpu(i, &cpu_core_map[cpu]);
  588. cpumask_set_cpu(cpu, &cpu_core_map[i]);
  589. if (cpu_data(cpu)->core_id == cpu_data(i)->core_id) {
  590. cpumask_set_cpu(i,
  591. &per_cpu(cpu_sibling_map, cpu));
  592. cpumask_set_cpu(cpu,
  593. &per_cpu(cpu_sibling_map, i));
  594. }
  595. }
  596. }
  597. }
  598. int
  599. __cpu_up(unsigned int cpu, struct task_struct *tidle)
  600. {
  601. int ret;
  602. int sapicid;
  603. sapicid = ia64_cpu_to_sapicid[cpu];
  604. if (sapicid == -1)
  605. return -EINVAL;
  606. /*
  607. * Already booted cpu? not valid anymore since we dont
  608. * do idle loop tightspin anymore.
  609. */
  610. if (cpumask_test_cpu(cpu, &cpu_callin_map))
  611. return -EINVAL;
  612. per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
  613. /* Processor goes to start_secondary(), sets online flag */
  614. ret = do_boot_cpu(sapicid, cpu, tidle);
  615. if (ret < 0)
  616. return ret;
  617. if (cpu_data(cpu)->threads_per_core == 1 &&
  618. cpu_data(cpu)->cores_per_socket == 1) {
  619. cpumask_set_cpu(cpu, &per_cpu(cpu_sibling_map, cpu));
  620. cpumask_set_cpu(cpu, &cpu_core_map[cpu]);
  621. return 0;
  622. }
  623. set_cpu_sibling_map(cpu);
  624. return 0;
  625. }
  626. /*
  627. * Assume that CPUs have been discovered by some platform-dependent interface. For
  628. * SoftSDV/Lion, that would be ACPI.
  629. *
  630. * Setup of the IPI irq handler is done in irq.c:init_IRQ_SMP().
  631. */
  632. void __init
  633. init_smp_config(void)
  634. {
  635. struct fptr {
  636. unsigned long fp;
  637. unsigned long gp;
  638. } *ap_startup;
  639. long sal_ret;
  640. /* Tell SAL where to drop the APs. */
  641. ap_startup = (struct fptr *) start_ap;
  642. sal_ret = ia64_sal_set_vectors(SAL_VECTOR_OS_BOOT_RENDEZ,
  643. ia64_tpa(ap_startup->fp), ia64_tpa(ap_startup->gp), 0, 0, 0, 0);
  644. if (sal_ret < 0)
  645. printk(KERN_ERR "SMP: Can't set SAL AP Boot Rendezvous: %s\n",
  646. ia64_sal_strerror(sal_ret));
  647. }
  648. /*
  649. * identify_siblings(cpu) gets called from identify_cpu. This populates the
  650. * information related to logical execution units in per_cpu_data structure.
  651. */
  652. void identify_siblings(struct cpuinfo_ia64 *c)
  653. {
  654. long status;
  655. u16 pltid;
  656. pal_logical_to_physical_t info;
  657. status = ia64_pal_logical_to_phys(-1, &info);
  658. if (status != PAL_STATUS_SUCCESS) {
  659. if (status != PAL_STATUS_UNIMPLEMENTED) {
  660. printk(KERN_ERR
  661. "ia64_pal_logical_to_phys failed with %ld\n",
  662. status);
  663. return;
  664. }
  665. info.overview_ppid = 0;
  666. info.overview_cpp = 1;
  667. info.overview_tpc = 1;
  668. }
  669. status = ia64_sal_physical_id_info(&pltid);
  670. if (status != PAL_STATUS_SUCCESS) {
  671. if (status != PAL_STATUS_UNIMPLEMENTED)
  672. printk(KERN_ERR
  673. "ia64_sal_pltid failed with %ld\n",
  674. status);
  675. return;
  676. }
  677. c->socket_id = (pltid << 8) | info.overview_ppid;
  678. if (info.overview_cpp == 1 && info.overview_tpc == 1)
  679. return;
  680. c->cores_per_socket = info.overview_cpp;
  681. c->threads_per_core = info.overview_tpc;
  682. c->num_log = info.overview_num_log;
  683. c->core_id = info.log1_cid;
  684. c->thread_id = info.log1_tid;
  685. }
  686. /*
  687. * returns non zero, if multi-threading is enabled
  688. * on at least one physical package. Due to hotplug cpu
  689. * and (maxcpus=), all threads may not necessarily be enabled
  690. * even though the processor supports multi-threading.
  691. */
  692. int is_multithreading_enabled(void)
  693. {
  694. int i, j;
  695. for_each_present_cpu(i) {
  696. for_each_present_cpu(j) {
  697. if (j == i)
  698. continue;
  699. if ((cpu_data(j)->socket_id == cpu_data(i)->socket_id)) {
  700. if (cpu_data(j)->core_id == cpu_data(i)->core_id)
  701. return 1;
  702. }
  703. }
  704. }
  705. return 0;
  706. }
  707. EXPORT_SYMBOL_GPL(is_multithreading_enabled);