entry.S 38 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * arch/ia64/kernel/entry.S
  4. *
  5. * Kernel entry points.
  6. *
  7. * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
  8. * David Mosberger-Tang <[email protected]>
  9. * Copyright (C) 1999, 2002-2003
  10. * Asit Mallick <[email protected]>
  11. * Don Dugger <[email protected]>
  12. * Suresh Siddha <[email protected]>
  13. * Fenghua Yu <[email protected]>
  14. * Copyright (C) 1999 VA Linux Systems
  15. * Copyright (C) 1999 Walt Drummond <[email protected]>
  16. */
  17. /*
  18. * ia64_switch_to now places correct virtual mapping in in TR2 for
  19. * kernel stack. This allows us to handle interrupts without changing
  20. * to physical mode.
  21. *
  22. * Jonathan Nicklin <[email protected]>
  23. * Patrick O'Rourke <[email protected]>
  24. * 11/07/2000
  25. */
  26. /*
  27. * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
  28. * VA Linux Systems Japan K.K.
  29. * pv_ops.
  30. */
  31. /*
  32. * Global (preserved) predicate usage on syscall entry/exit path:
  33. *
  34. * pKStk: See entry.h.
  35. * pUStk: See entry.h.
  36. * pSys: See entry.h.
  37. * pNonSys: !pSys
  38. */
  39. #include <linux/pgtable.h>
  40. #include <asm/asmmacro.h>
  41. #include <asm/cache.h>
  42. #include <asm/errno.h>
  43. #include <asm/kregs.h>
  44. #include <asm/asm-offsets.h>
  45. #include <asm/percpu.h>
  46. #include <asm/processor.h>
  47. #include <asm/thread_info.h>
  48. #include <asm/unistd.h>
  49. #include <asm/ftrace.h>
  50. #include <asm/export.h>
  51. #include "minstate.h"
  52. /*
  53. * execve() is special because in case of success, we need to
  54. * setup a null register window frame.
  55. */
  56. ENTRY(ia64_execve)
  57. /*
  58. * Allocate 8 input registers since ptrace() may clobber them
  59. */
  60. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  61. alloc loc1=ar.pfs,8,2,3,0
  62. mov loc0=rp
  63. .body
  64. mov out0=in0 // filename
  65. ;; // stop bit between alloc and call
  66. mov out1=in1 // argv
  67. mov out2=in2 // envp
  68. br.call.sptk.many rp=sys_execve
  69. .ret0:
  70. cmp4.ge p6,p7=r8,r0
  71. mov ar.pfs=loc1 // restore ar.pfs
  72. sxt4 r8=r8 // return 64-bit result
  73. ;;
  74. stf.spill [sp]=f0
  75. mov rp=loc0
  76. (p6) mov ar.pfs=r0 // clear ar.pfs on success
  77. (p7) br.ret.sptk.many rp
  78. /*
  79. * In theory, we'd have to zap this state only to prevent leaking of
  80. * security sensitive state (e.g., if current->mm->dumpable is zero). However,
  81. * this executes in less than 20 cycles even on Itanium, so it's not worth
  82. * optimizing for...).
  83. */
  84. mov ar.unat=0; mov ar.lc=0
  85. mov r4=0; mov f2=f0; mov b1=r0
  86. mov r5=0; mov f3=f0; mov b2=r0
  87. mov r6=0; mov f4=f0; mov b3=r0
  88. mov r7=0; mov f5=f0; mov b4=r0
  89. ldf.fill f12=[sp]; mov f13=f0; mov b5=r0
  90. ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
  91. ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0
  92. ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0
  93. ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
  94. ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0
  95. ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0
  96. br.ret.sptk.many rp
  97. END(ia64_execve)
  98. /*
  99. * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
  100. * u64 tls)
  101. */
  102. GLOBAL_ENTRY(sys_clone2)
  103. /*
  104. * Allocate 8 input registers since ptrace() may clobber them
  105. */
  106. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  107. alloc r16=ar.pfs,8,2,6,0
  108. DO_SAVE_SWITCH_STACK
  109. mov loc0=rp
  110. mov loc1=r16 // save ar.pfs across ia64_clone
  111. .body
  112. mov out0=in0
  113. mov out1=in1
  114. mov out2=in2
  115. mov out3=in3
  116. mov out4=in4
  117. mov out5=in5
  118. br.call.sptk.many rp=ia64_clone
  119. .ret1: .restore sp
  120. adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
  121. mov ar.pfs=loc1
  122. mov rp=loc0
  123. br.ret.sptk.many rp
  124. END(sys_clone2)
  125. /*
  126. * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
  127. * Deprecated. Use sys_clone2() instead.
  128. */
  129. GLOBAL_ENTRY(sys_clone)
  130. /*
  131. * Allocate 8 input registers since ptrace() may clobber them
  132. */
  133. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  134. alloc r16=ar.pfs,8,2,6,0
  135. DO_SAVE_SWITCH_STACK
  136. mov loc0=rp
  137. mov loc1=r16 // save ar.pfs across ia64_clone
  138. .body
  139. mov out0=in0
  140. mov out1=in1
  141. mov out2=16 // stacksize (compensates for 16-byte scratch area)
  142. mov out3=in3
  143. mov out4=in4
  144. mov out5=in5
  145. br.call.sptk.many rp=ia64_clone
  146. .ret2: .restore sp
  147. adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
  148. mov ar.pfs=loc1
  149. mov rp=loc0
  150. br.ret.sptk.many rp
  151. END(sys_clone)
  152. /*
  153. * prev_task <- ia64_switch_to(struct task_struct *next)
  154. * With Ingo's new scheduler, interrupts are disabled when this routine gets
  155. * called. The code starting at .map relies on this. The rest of the code
  156. * doesn't care about the interrupt masking status.
  157. */
  158. GLOBAL_ENTRY(ia64_switch_to)
  159. .prologue
  160. alloc r16=ar.pfs,1,0,0,0
  161. DO_SAVE_SWITCH_STACK
  162. .body
  163. adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
  164. movl r25=init_task
  165. mov r27=IA64_KR(CURRENT_STACK)
  166. adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
  167. dep r20=0,in0,61,3 // physical address of "next"
  168. ;;
  169. st8 [r22]=sp // save kernel stack pointer of old task
  170. shr.u r26=r20,IA64_GRANULE_SHIFT
  171. cmp.eq p7,p6=r25,in0
  172. ;;
  173. /*
  174. * If we've already mapped this task's page, we can skip doing it again.
  175. */
  176. (p6) cmp.eq p7,p6=r26,r27
  177. (p6) br.cond.dpnt .map
  178. ;;
  179. .done:
  180. ld8 sp=[r21] // load kernel stack pointer of new task
  181. MOV_TO_KR(CURRENT, in0, r8, r9) // update "current" application register
  182. mov r8=r13 // return pointer to previously running task
  183. mov r13=in0 // set "current" pointer
  184. ;;
  185. DO_LOAD_SWITCH_STACK
  186. #ifdef CONFIG_SMP
  187. sync.i // ensure "fc"s done by this CPU are visible on other CPUs
  188. #endif
  189. br.ret.sptk.many rp // boogie on out in new context
  190. .map:
  191. RSM_PSR_IC(r25) // interrupts (psr.i) are already disabled here
  192. movl r25=PAGE_KERNEL
  193. ;;
  194. srlz.d
  195. or r23=r25,r20 // construct PA | page properties
  196. mov r25=IA64_GRANULE_SHIFT<<2
  197. ;;
  198. MOV_TO_ITIR(p0, r25, r8)
  199. MOV_TO_IFA(in0, r8) // VA of next task...
  200. ;;
  201. mov r25=IA64_TR_CURRENT_STACK
  202. MOV_TO_KR(CURRENT_STACK, r26, r8, r9) // remember last page we mapped...
  203. ;;
  204. itr.d dtr[r25]=r23 // wire in new mapping...
  205. SSM_PSR_IC_AND_SRLZ_D(r8, r9) // reenable the psr.ic bit
  206. br.cond.sptk .done
  207. END(ia64_switch_to)
  208. /*
  209. * Note that interrupts are enabled during save_switch_stack and load_switch_stack. This
  210. * means that we may get an interrupt with "sp" pointing to the new kernel stack while
  211. * ar.bspstore is still pointing to the old kernel backing store area. Since ar.rsc,
  212. * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
  213. * problem. Also, we don't need to specify unwind information for preserved registers
  214. * that are not modified in save_switch_stack as the right unwind information is already
  215. * specified at the call-site of save_switch_stack.
  216. */
  217. /*
  218. * save_switch_stack:
  219. * - r16 holds ar.pfs
  220. * - b7 holds address to return to
  221. * - rp (b0) holds return address to save
  222. */
  223. GLOBAL_ENTRY(save_switch_stack)
  224. .prologue
  225. .altrp b7
  226. flushrs // flush dirty regs to backing store (must be first in insn group)
  227. .save @priunat,r17
  228. mov r17=ar.unat // preserve caller's
  229. .body
  230. #ifdef CONFIG_ITANIUM
  231. adds r2=16+128,sp
  232. adds r3=16+64,sp
  233. adds r14=SW(R4)+16,sp
  234. ;;
  235. st8.spill [r14]=r4,16 // spill r4
  236. lfetch.fault.excl.nt1 [r3],128
  237. ;;
  238. lfetch.fault.excl.nt1 [r2],128
  239. lfetch.fault.excl.nt1 [r3],128
  240. ;;
  241. lfetch.fault.excl [r2]
  242. lfetch.fault.excl [r3]
  243. adds r15=SW(R5)+16,sp
  244. #else
  245. add r2=16+3*128,sp
  246. add r3=16,sp
  247. add r14=SW(R4)+16,sp
  248. ;;
  249. st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
  250. lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
  251. ;;
  252. lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
  253. lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
  254. ;;
  255. lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
  256. lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
  257. adds r15=SW(R5)+16,sp
  258. #endif
  259. ;;
  260. st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
  261. mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0
  262. add r2=SW(F2)+16,sp // r2 = &sw->f2
  263. ;;
  264. st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
  265. mov.m r18=ar.fpsr // preserve fpsr
  266. add r3=SW(F3)+16,sp // r3 = &sw->f3
  267. ;;
  268. stf.spill [r2]=f2,32
  269. mov.m r19=ar.rnat
  270. mov r21=b0
  271. stf.spill [r3]=f3,32
  272. st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
  273. mov r22=b1
  274. ;;
  275. // since we're done with the spills, read and save ar.unat:
  276. mov.m r29=ar.unat
  277. mov.m r20=ar.bspstore
  278. mov r23=b2
  279. stf.spill [r2]=f4,32
  280. stf.spill [r3]=f5,32
  281. mov r24=b3
  282. ;;
  283. st8 [r14]=r21,SW(B1)-SW(B0) // save b0
  284. st8 [r15]=r23,SW(B3)-SW(B2) // save b2
  285. mov r25=b4
  286. mov r26=b5
  287. ;;
  288. st8 [r14]=r22,SW(B4)-SW(B1) // save b1
  289. st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3
  290. mov r21=ar.lc // I-unit
  291. stf.spill [r2]=f12,32
  292. stf.spill [r3]=f13,32
  293. ;;
  294. st8 [r14]=r25,SW(B5)-SW(B4) // save b4
  295. st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
  296. stf.spill [r2]=f14,32
  297. stf.spill [r3]=f15,32
  298. ;;
  299. st8 [r14]=r26 // save b5
  300. st8 [r15]=r21 // save ar.lc
  301. stf.spill [r2]=f16,32
  302. stf.spill [r3]=f17,32
  303. ;;
  304. stf.spill [r2]=f18,32
  305. stf.spill [r3]=f19,32
  306. ;;
  307. stf.spill [r2]=f20,32
  308. stf.spill [r3]=f21,32
  309. ;;
  310. stf.spill [r2]=f22,32
  311. stf.spill [r3]=f23,32
  312. ;;
  313. stf.spill [r2]=f24,32
  314. stf.spill [r3]=f25,32
  315. ;;
  316. stf.spill [r2]=f26,32
  317. stf.spill [r3]=f27,32
  318. ;;
  319. stf.spill [r2]=f28,32
  320. stf.spill [r3]=f29,32
  321. ;;
  322. stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
  323. stf.spill [r3]=f31,SW(PR)-SW(F31)
  324. add r14=SW(CALLER_UNAT)+16,sp
  325. ;;
  326. st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
  327. st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
  328. mov r21=pr
  329. ;;
  330. st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
  331. st8 [r3]=r21 // save predicate registers
  332. ;;
  333. st8 [r2]=r20 // save ar.bspstore
  334. st8 [r14]=r18 // save fpsr
  335. mov ar.rsc=3 // put RSE back into eager mode, pl 0
  336. br.cond.sptk.many b7
  337. END(save_switch_stack)
  338. /*
  339. * load_switch_stack:
  340. * - "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
  341. * - b7 holds address to return to
  342. * - must not touch r8-r11
  343. */
  344. GLOBAL_ENTRY(load_switch_stack)
  345. .prologue
  346. .altrp b7
  347. .body
  348. lfetch.fault.nt1 [sp]
  349. adds r2=SW(AR_BSPSTORE)+16,sp
  350. adds r3=SW(AR_UNAT)+16,sp
  351. mov ar.rsc=0 // put RSE into enforced lazy mode
  352. adds r14=SW(CALLER_UNAT)+16,sp
  353. adds r15=SW(AR_FPSR)+16,sp
  354. ;;
  355. ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
  356. ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
  357. ;;
  358. ld8 r21=[r2],16 // restore b0
  359. ld8 r22=[r3],16 // restore b1
  360. ;;
  361. ld8 r23=[r2],16 // restore b2
  362. ld8 r24=[r3],16 // restore b3
  363. ;;
  364. ld8 r25=[r2],16 // restore b4
  365. ld8 r26=[r3],16 // restore b5
  366. ;;
  367. ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
  368. ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
  369. ;;
  370. ld8 r28=[r2] // restore pr
  371. ld8 r30=[r3] // restore rnat
  372. ;;
  373. ld8 r18=[r14],16 // restore caller's unat
  374. ld8 r19=[r15],24 // restore fpsr
  375. ;;
  376. ldf.fill f2=[r14],32
  377. ldf.fill f3=[r15],32
  378. ;;
  379. ldf.fill f4=[r14],32
  380. ldf.fill f5=[r15],32
  381. ;;
  382. ldf.fill f12=[r14],32
  383. ldf.fill f13=[r15],32
  384. ;;
  385. ldf.fill f14=[r14],32
  386. ldf.fill f15=[r15],32
  387. ;;
  388. ldf.fill f16=[r14],32
  389. ldf.fill f17=[r15],32
  390. ;;
  391. ldf.fill f18=[r14],32
  392. ldf.fill f19=[r15],32
  393. mov b0=r21
  394. ;;
  395. ldf.fill f20=[r14],32
  396. ldf.fill f21=[r15],32
  397. mov b1=r22
  398. ;;
  399. ldf.fill f22=[r14],32
  400. ldf.fill f23=[r15],32
  401. mov b2=r23
  402. ;;
  403. mov ar.bspstore=r27
  404. mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7
  405. mov b3=r24
  406. ;;
  407. ldf.fill f24=[r14],32
  408. ldf.fill f25=[r15],32
  409. mov b4=r25
  410. ;;
  411. ldf.fill f26=[r14],32
  412. ldf.fill f27=[r15],32
  413. mov b5=r26
  414. ;;
  415. ldf.fill f28=[r14],32
  416. ldf.fill f29=[r15],32
  417. mov ar.pfs=r16
  418. ;;
  419. ldf.fill f30=[r14],32
  420. ldf.fill f31=[r15],24
  421. mov ar.lc=r17
  422. ;;
  423. ld8.fill r4=[r14],16
  424. ld8.fill r5=[r15],16
  425. mov pr=r28,-1
  426. ;;
  427. ld8.fill r6=[r14],16
  428. ld8.fill r7=[r15],16
  429. mov ar.unat=r18 // restore caller's unat
  430. mov ar.rnat=r30 // must restore after bspstore but before rsc!
  431. mov ar.fpsr=r19 // restore fpsr
  432. mov ar.rsc=3 // put RSE back into eager mode, pl 0
  433. br.cond.sptk.many b7
  434. END(load_switch_stack)
  435. /*
  436. * Invoke a system call, but do some tracing before and after the call.
  437. * We MUST preserve the current register frame throughout this routine
  438. * because some system calls (such as ia64_execve) directly
  439. * manipulate ar.pfs.
  440. */
  441. GLOBAL_ENTRY(ia64_trace_syscall)
  442. PT_REGS_UNWIND_INFO(0)
  443. /*
  444. * We need to preserve the scratch registers f6-f11 in case the system
  445. * call is sigreturn.
  446. */
  447. adds r16=PT(F6)+16,sp
  448. adds r17=PT(F7)+16,sp
  449. ;;
  450. stf.spill [r16]=f6,32
  451. stf.spill [r17]=f7,32
  452. ;;
  453. stf.spill [r16]=f8,32
  454. stf.spill [r17]=f9,32
  455. ;;
  456. stf.spill [r16]=f10
  457. stf.spill [r17]=f11
  458. br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
  459. cmp.lt p6,p0=r8,r0 // check tracehook
  460. adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
  461. adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
  462. mov r10=0
  463. (p6) br.cond.sptk strace_error // syscall failed ->
  464. adds r16=PT(F6)+16,sp
  465. adds r17=PT(F7)+16,sp
  466. ;;
  467. ldf.fill f6=[r16],32
  468. ldf.fill f7=[r17],32
  469. ;;
  470. ldf.fill f8=[r16],32
  471. ldf.fill f9=[r17],32
  472. ;;
  473. ldf.fill f10=[r16]
  474. ldf.fill f11=[r17]
  475. // the syscall number may have changed, so re-load it and re-calculate the
  476. // syscall entry-point:
  477. adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #)
  478. ;;
  479. ld8 r15=[r15]
  480. mov r3=NR_syscalls - 1
  481. ;;
  482. adds r15=-1024,r15
  483. movl r16=sys_call_table
  484. ;;
  485. shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
  486. cmp.leu p6,p7=r15,r3
  487. ;;
  488. (p6) ld8 r20=[r20] // load address of syscall entry point
  489. (p7) movl r20=sys_ni_syscall
  490. ;;
  491. mov b6=r20
  492. br.call.sptk.many rp=b6 // do the syscall
  493. .strace_check_retval:
  494. cmp.lt p6,p0=r8,r0 // syscall failed?
  495. adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
  496. adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
  497. mov r10=0
  498. (p6) br.cond.sptk strace_error // syscall failed ->
  499. ;; // avoid RAW on r10
  500. .strace_save_retval:
  501. .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
  502. .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
  503. br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
  504. .ret3:
  505. (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
  506. (pUStk) rsm psr.i // disable interrupts
  507. br.cond.sptk ia64_work_pending_syscall_end
  508. strace_error:
  509. ld8 r3=[r2] // load pt_regs.r8
  510. sub r9=0,r8 // negate return value to get errno value
  511. ;;
  512. cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
  513. adds r3=16,r2 // r3=&pt_regs.r10
  514. ;;
  515. (p6) mov r10=-1
  516. (p6) mov r8=r9
  517. br.cond.sptk .strace_save_retval
  518. END(ia64_trace_syscall)
  519. /*
  520. * When traced and returning from sigreturn, we invoke syscall_trace but then
  521. * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
  522. */
  523. GLOBAL_ENTRY(ia64_strace_leave_kernel)
  524. PT_REGS_UNWIND_INFO(0)
  525. { /*
  526. * Some versions of gas generate bad unwind info if the first instruction of a
  527. * procedure doesn't go into the first slot of a bundle. This is a workaround.
  528. */
  529. nop.m 0
  530. nop.i 0
  531. br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
  532. }
  533. .ret4: br.cond.sptk ia64_leave_kernel
  534. END(ia64_strace_leave_kernel)
  535. ENTRY(call_payload)
  536. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(0)
  537. /* call the kernel_thread payload; fn is in r4, arg - in r5 */
  538. alloc loc1=ar.pfs,0,3,1,0
  539. mov loc0=rp
  540. mov loc2=gp
  541. mov out0=r5 // arg
  542. ld8 r14 = [r4], 8 // fn.address
  543. ;;
  544. mov b6 = r14
  545. ld8 gp = [r4] // fn.gp
  546. ;;
  547. br.call.sptk.many rp=b6 // fn(arg)
  548. .ret12: mov gp=loc2
  549. mov rp=loc0
  550. mov ar.pfs=loc1
  551. /* ... and if it has returned, we are going to userland */
  552. cmp.ne pKStk,pUStk=r0,r0
  553. br.ret.sptk.many rp
  554. END(call_payload)
  555. GLOBAL_ENTRY(ia64_ret_from_clone)
  556. PT_REGS_UNWIND_INFO(0)
  557. { /*
  558. * Some versions of gas generate bad unwind info if the first instruction of a
  559. * procedure doesn't go into the first slot of a bundle. This is a workaround.
  560. */
  561. nop.m 0
  562. nop.i 0
  563. /*
  564. * We need to call schedule_tail() to complete the scheduling process.
  565. * Called by ia64_switch_to() after ia64_clone()->copy_thread(). r8 contains the
  566. * address of the previously executing task.
  567. */
  568. br.call.sptk.many rp=ia64_invoke_schedule_tail
  569. }
  570. .ret8:
  571. (pKStk) br.call.sptk.many rp=call_payload
  572. adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
  573. ;;
  574. ld4 r2=[r2]
  575. ;;
  576. mov r8=0
  577. and r2=_TIF_SYSCALL_TRACEAUDIT,r2
  578. ;;
  579. cmp.ne p6,p0=r2,r0
  580. (p6) br.cond.spnt .strace_check_retval
  581. ;; // added stop bits to prevent r8 dependency
  582. END(ia64_ret_from_clone)
  583. // fall through
  584. GLOBAL_ENTRY(ia64_ret_from_syscall)
  585. PT_REGS_UNWIND_INFO(0)
  586. cmp.ge p6,p7=r8,r0 // syscall executed successfully?
  587. adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
  588. mov r10=r0 // clear error indication in r10
  589. (p7) br.cond.spnt handle_syscall_error // handle potential syscall failure
  590. END(ia64_ret_from_syscall)
  591. // fall through
  592. /*
  593. * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
  594. * need to switch to bank 0 and doesn't restore the scratch registers.
  595. * To avoid leaking kernel bits, the scratch registers are set to
  596. * the following known-to-be-safe values:
  597. *
  598. * r1: restored (global pointer)
  599. * r2: cleared
  600. * r3: 1 (when returning to user-level)
  601. * r8-r11: restored (syscall return value(s))
  602. * r12: restored (user-level stack pointer)
  603. * r13: restored (user-level thread pointer)
  604. * r14: set to __kernel_syscall_via_epc
  605. * r15: restored (syscall #)
  606. * r16-r17: cleared
  607. * r18: user-level b6
  608. * r19: cleared
  609. * r20: user-level ar.fpsr
  610. * r21: user-level b0
  611. * r22: cleared
  612. * r23: user-level ar.bspstore
  613. * r24: user-level ar.rnat
  614. * r25: user-level ar.unat
  615. * r26: user-level ar.pfs
  616. * r27: user-level ar.rsc
  617. * r28: user-level ip
  618. * r29: user-level psr
  619. * r30: user-level cfm
  620. * r31: user-level pr
  621. * f6-f11: cleared
  622. * pr: restored (user-level pr)
  623. * b0: restored (user-level rp)
  624. * b6: restored
  625. * b7: set to __kernel_syscall_via_epc
  626. * ar.unat: restored (user-level ar.unat)
  627. * ar.pfs: restored (user-level ar.pfs)
  628. * ar.rsc: restored (user-level ar.rsc)
  629. * ar.rnat: restored (user-level ar.rnat)
  630. * ar.bspstore: restored (user-level ar.bspstore)
  631. * ar.fpsr: restored (user-level ar.fpsr)
  632. * ar.ccv: cleared
  633. * ar.csd: cleared
  634. * ar.ssd: cleared
  635. */
  636. GLOBAL_ENTRY(ia64_leave_syscall)
  637. PT_REGS_UNWIND_INFO(0)
  638. /*
  639. * work.need_resched etc. mustn't get changed by this CPU before it returns to
  640. * user- or fsys-mode, hence we disable interrupts early on.
  641. *
  642. * p6 controls whether current_thread_info()->flags needs to be check for
  643. * extra work. We always check for extra work when returning to user-level.
  644. * With CONFIG_PREEMPTION, we also check for extra work when the preempt_count
  645. * is 0. After extra work processing has been completed, execution
  646. * resumes at ia64_work_processed_syscall with p6 set to 1 if the extra-work-check
  647. * needs to be redone.
  648. */
  649. #ifdef CONFIG_PREEMPTION
  650. RSM_PSR_I(p0, r2, r18) // disable interrupts
  651. cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
  652. (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
  653. ;;
  654. .pred.rel.mutex pUStk,pKStk
  655. (pKStk) ld4 r21=[r20] // r21 <- preempt_count
  656. (pUStk) mov r21=0 // r21 <- 0
  657. ;;
  658. cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
  659. #else /* !CONFIG_PREEMPTION */
  660. RSM_PSR_I(pUStk, r2, r18)
  661. cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
  662. (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
  663. #endif
  664. .global ia64_work_processed_syscall;
  665. ia64_work_processed_syscall:
  666. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  667. adds r2=PT(LOADRS)+16,r12
  668. MOV_FROM_ITC(pUStk, p9, r22, r19) // fetch time at leave
  669. adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
  670. ;;
  671. (p6) ld4 r31=[r18] // load current_thread_info()->flags
  672. ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
  673. adds r3=PT(AR_BSPSTORE)+16,r12 // deferred
  674. ;;
  675. #else
  676. adds r2=PT(LOADRS)+16,r12
  677. adds r3=PT(AR_BSPSTORE)+16,r12
  678. adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
  679. ;;
  680. (p6) ld4 r31=[r18] // load current_thread_info()->flags
  681. ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
  682. nop.i 0
  683. ;;
  684. #endif
  685. mov r16=ar.bsp // M2 get existing backing store pointer
  686. ld8 r18=[r2],PT(R9)-PT(B6) // load b6
  687. (p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
  688. ;;
  689. ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
  690. (p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
  691. (p6) br.cond.spnt .work_pending_syscall
  692. ;;
  693. // start restoring the state saved on the kernel stack (struct pt_regs):
  694. ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
  695. ld8 r11=[r3],PT(CR_IIP)-PT(R11)
  696. (pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
  697. ;;
  698. invala // M0|1 invalidate ALAT
  699. RSM_PSR_I_IC(r28, r29, r30) // M2 turn off interrupts and interruption collection
  700. cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
  701. ld8 r29=[r2],16 // M0|1 load cr.ipsr
  702. ld8 r28=[r3],16 // M0|1 load cr.iip
  703. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  704. (pUStk) add r14=TI_AC_LEAVE+IA64_TASK_SIZE,r13
  705. ;;
  706. ld8 r30=[r2],16 // M0|1 load cr.ifs
  707. ld8 r25=[r3],16 // M0|1 load ar.unat
  708. (pUStk) add r15=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
  709. ;;
  710. #else
  711. mov r22=r0 // A clear r22
  712. ;;
  713. ld8 r30=[r2],16 // M0|1 load cr.ifs
  714. ld8 r25=[r3],16 // M0|1 load ar.unat
  715. (pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
  716. ;;
  717. #endif
  718. ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
  719. MOV_FROM_PSR(pKStk, r22, r21) // M2 read PSR now that interrupts are disabled
  720. nop 0
  721. ;;
  722. ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
  723. ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
  724. mov f6=f0 // F clear f6
  725. ;;
  726. ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
  727. ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
  728. mov f7=f0 // F clear f7
  729. ;;
  730. ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
  731. ld8.fill r1=[r3],16 // M0|1 load r1
  732. (pUStk) mov r17=1 // A
  733. ;;
  734. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  735. (pUStk) st1 [r15]=r17 // M2|3
  736. #else
  737. (pUStk) st1 [r14]=r17 // M2|3
  738. #endif
  739. ld8.fill r13=[r3],16 // M0|1
  740. mov f8=f0 // F clear f8
  741. ;;
  742. ld8.fill r12=[r2] // M0|1 restore r12 (sp)
  743. ld8.fill r15=[r3] // M0|1 restore r15
  744. mov b6=r18 // I0 restore b6
  745. LOAD_PHYS_STACK_REG_SIZE(r17)
  746. mov f9=f0 // F clear f9
  747. (pKStk) br.cond.dpnt.many skip_rbs_switch // B
  748. srlz.d // M0 ensure interruption collection is off (for cover)
  749. shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
  750. COVER // B add current frame into dirty partition & set cr.ifs
  751. ;;
  752. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  753. mov r19=ar.bsp // M2 get new backing store pointer
  754. st8 [r14]=r22 // M save time at leave
  755. mov f10=f0 // F clear f10
  756. mov r22=r0 // A clear r22
  757. movl r14=__kernel_syscall_via_epc // X
  758. ;;
  759. #else
  760. mov r19=ar.bsp // M2 get new backing store pointer
  761. mov f10=f0 // F clear f10
  762. nop.m 0
  763. movl r14=__kernel_syscall_via_epc // X
  764. ;;
  765. #endif
  766. mov.m ar.csd=r0 // M2 clear ar.csd
  767. mov.m ar.ccv=r0 // M2 clear ar.ccv
  768. mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
  769. mov.m ar.ssd=r0 // M2 clear ar.ssd
  770. mov f11=f0 // F clear f11
  771. br.cond.sptk.many rbs_switch // B
  772. END(ia64_leave_syscall)
  773. GLOBAL_ENTRY(ia64_leave_kernel)
  774. PT_REGS_UNWIND_INFO(0)
  775. /*
  776. * work.need_resched etc. mustn't get changed by this CPU before it returns to
  777. * user- or fsys-mode, hence we disable interrupts early on.
  778. *
  779. * p6 controls whether current_thread_info()->flags needs to be check for
  780. * extra work. We always check for extra work when returning to user-level.
  781. * With CONFIG_PREEMPTION, we also check for extra work when the preempt_count
  782. * is 0. After extra work processing has been completed, execution
  783. * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
  784. * needs to be redone.
  785. */
  786. #ifdef CONFIG_PREEMPTION
  787. RSM_PSR_I(p0, r17, r31) // disable interrupts
  788. cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
  789. (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
  790. ;;
  791. .pred.rel.mutex pUStk,pKStk
  792. (pKStk) ld4 r21=[r20] // r21 <- preempt_count
  793. (pUStk) mov r21=0 // r21 <- 0
  794. ;;
  795. cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
  796. #else
  797. RSM_PSR_I(pUStk, r17, r31)
  798. cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
  799. (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
  800. #endif
  801. .work_processed_kernel:
  802. adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
  803. ;;
  804. (p6) ld4 r31=[r17] // load current_thread_info()->flags
  805. adds r21=PT(PR)+16,r12
  806. ;;
  807. lfetch [r21],PT(CR_IPSR)-PT(PR)
  808. adds r2=PT(B6)+16,r12
  809. adds r3=PT(R16)+16,r12
  810. ;;
  811. lfetch [r21]
  812. ld8 r28=[r2],8 // load b6
  813. adds r29=PT(R24)+16,r12
  814. ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
  815. adds r30=PT(AR_CCV)+16,r12
  816. (p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
  817. ;;
  818. ld8.fill r24=[r29]
  819. ld8 r15=[r30] // load ar.ccv
  820. (p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending?
  821. ;;
  822. ld8 r29=[r2],16 // load b7
  823. ld8 r30=[r3],16 // load ar.csd
  824. (p6) br.cond.spnt .work_pending
  825. ;;
  826. ld8 r31=[r2],16 // load ar.ssd
  827. ld8.fill r8=[r3],16
  828. ;;
  829. ld8.fill r9=[r2],16
  830. ld8.fill r10=[r3],PT(R17)-PT(R10)
  831. ;;
  832. ld8.fill r11=[r2],PT(R18)-PT(R11)
  833. ld8.fill r17=[r3],16
  834. ;;
  835. ld8.fill r18=[r2],16
  836. ld8.fill r19=[r3],16
  837. ;;
  838. ld8.fill r20=[r2],16
  839. ld8.fill r21=[r3],16
  840. mov ar.csd=r30
  841. mov ar.ssd=r31
  842. ;;
  843. RSM_PSR_I_IC(r23, r22, r25) // initiate turning off of interrupt and interruption collection
  844. invala // invalidate ALAT
  845. ;;
  846. ld8.fill r22=[r2],24
  847. ld8.fill r23=[r3],24
  848. mov b6=r28
  849. ;;
  850. ld8.fill r25=[r2],16
  851. ld8.fill r26=[r3],16
  852. mov b7=r29
  853. ;;
  854. ld8.fill r27=[r2],16
  855. ld8.fill r28=[r3],16
  856. ;;
  857. ld8.fill r29=[r2],16
  858. ld8.fill r30=[r3],24
  859. ;;
  860. ld8.fill r31=[r2],PT(F9)-PT(R31)
  861. adds r3=PT(F10)-PT(F6),r3
  862. ;;
  863. ldf.fill f9=[r2],PT(F6)-PT(F9)
  864. ldf.fill f10=[r3],PT(F8)-PT(F10)
  865. ;;
  866. ldf.fill f6=[r2],PT(F7)-PT(F6)
  867. ;;
  868. ldf.fill f7=[r2],PT(F11)-PT(F7)
  869. ldf.fill f8=[r3],32
  870. ;;
  871. srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
  872. mov ar.ccv=r15
  873. ;;
  874. ldf.fill f11=[r2]
  875. BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
  876. ;;
  877. (pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency)
  878. adds r16=PT(CR_IPSR)+16,r12
  879. adds r17=PT(CR_IIP)+16,r12
  880. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  881. .pred.rel.mutex pUStk,pKStk
  882. MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
  883. MOV_FROM_ITC(pUStk, p9, r22, r29) // M fetch time at leave
  884. nop.i 0
  885. ;;
  886. #else
  887. MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
  888. nop.i 0
  889. nop.i 0
  890. ;;
  891. #endif
  892. ld8 r29=[r16],16 // load cr.ipsr
  893. ld8 r28=[r17],16 // load cr.iip
  894. ;;
  895. ld8 r30=[r16],16 // load cr.ifs
  896. ld8 r25=[r17],16 // load ar.unat
  897. ;;
  898. ld8 r26=[r16],16 // load ar.pfs
  899. ld8 r27=[r17],16 // load ar.rsc
  900. cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
  901. ;;
  902. ld8 r24=[r16],16 // load ar.rnat (may be garbage)
  903. ld8 r23=[r17],16 // load ar.bspstore (may be garbage)
  904. ;;
  905. ld8 r31=[r16],16 // load predicates
  906. ld8 r21=[r17],16 // load b0
  907. ;;
  908. ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
  909. ld8.fill r1=[r17],16 // load r1
  910. ;;
  911. ld8.fill r12=[r16],16
  912. ld8.fill r13=[r17],16
  913. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  914. (pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
  915. #else
  916. (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
  917. #endif
  918. ;;
  919. ld8 r20=[r16],16 // ar.fpsr
  920. ld8.fill r15=[r17],16
  921. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  922. (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18 // deferred
  923. #endif
  924. ;;
  925. ld8.fill r14=[r16],16
  926. ld8.fill r2=[r17]
  927. (pUStk) mov r17=1
  928. ;;
  929. #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
  930. // mmi_ : ld8 st1 shr;; mmi_ : st8 st1 shr;;
  931. // mib : mov add br -> mib : ld8 add br
  932. // bbb_ : br nop cover;; mbb_ : mov br cover;;
  933. //
  934. // no one require bsp in r16 if (pKStk) branch is selected.
  935. (pUStk) st8 [r3]=r22 // save time at leave
  936. (pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
  937. shr.u r18=r19,16 // get byte size of existing "dirty" partition
  938. ;;
  939. ld8.fill r3=[r16] // deferred
  940. LOAD_PHYS_STACK_REG_SIZE(r17)
  941. (pKStk) br.cond.dpnt skip_rbs_switch
  942. mov r16=ar.bsp // get existing backing store pointer
  943. #else
  944. ld8.fill r3=[r16]
  945. (pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
  946. shr.u r18=r19,16 // get byte size of existing "dirty" partition
  947. ;;
  948. mov r16=ar.bsp // get existing backing store pointer
  949. LOAD_PHYS_STACK_REG_SIZE(r17)
  950. (pKStk) br.cond.dpnt skip_rbs_switch
  951. #endif
  952. /*
  953. * Restore user backing store.
  954. *
  955. * NOTE: alloc, loadrs, and cover can't be predicated.
  956. */
  957. (pNonSys) br.cond.dpnt dont_preserve_current_frame
  958. COVER // add current frame into dirty partition and set cr.ifs
  959. ;;
  960. mov r19=ar.bsp // get new backing store pointer
  961. rbs_switch:
  962. sub r16=r16,r18 // krbs = old bsp - size of dirty partition
  963. cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
  964. ;;
  965. sub r19=r19,r16 // calculate total byte size of dirty partition
  966. add r18=64,r18 // don't force in0-in7 into memory...
  967. ;;
  968. shl r19=r19,16 // shift size of dirty partition into loadrs position
  969. ;;
  970. dont_preserve_current_frame:
  971. /*
  972. * To prevent leaking bits between the kernel and user-space,
  973. * we must clear the stacked registers in the "invalid" partition here.
  974. * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
  975. * 5 registers/cycle on McKinley).
  976. */
  977. # define pRecurse p6
  978. # define pReturn p7
  979. #ifdef CONFIG_ITANIUM
  980. # define Nregs 10
  981. #else
  982. # define Nregs 14
  983. #endif
  984. alloc loc0=ar.pfs,2,Nregs-2,2,0
  985. shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
  986. sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
  987. ;;
  988. mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
  989. shladd in0=loc1,3,r17
  990. mov in1=0
  991. ;;
  992. TEXT_ALIGN(32)
  993. rse_clear_invalid:
  994. #ifdef CONFIG_ITANIUM
  995. // cycle 0
  996. { .mii
  997. alloc loc0=ar.pfs,2,Nregs-2,2,0
  998. cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
  999. add out0=-Nregs*8,in0
  1000. }{ .mfb
  1001. add out1=1,in1 // increment recursion count
  1002. nop.f 0
  1003. nop.b 0 // can't do br.call here because of alloc (WAW on CFM)
  1004. ;;
  1005. }{ .mfi // cycle 1
  1006. mov loc1=0
  1007. nop.f 0
  1008. mov loc2=0
  1009. }{ .mib
  1010. mov loc3=0
  1011. mov loc4=0
  1012. (pRecurse) br.call.sptk.many b0=rse_clear_invalid
  1013. }{ .mfi // cycle 2
  1014. mov loc5=0
  1015. nop.f 0
  1016. cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
  1017. }{ .mib
  1018. mov loc6=0
  1019. mov loc7=0
  1020. (pReturn) br.ret.sptk.many b0
  1021. }
  1022. #else /* !CONFIG_ITANIUM */
  1023. alloc loc0=ar.pfs,2,Nregs-2,2,0
  1024. cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
  1025. add out0=-Nregs*8,in0
  1026. add out1=1,in1 // increment recursion count
  1027. mov loc1=0
  1028. mov loc2=0
  1029. ;;
  1030. mov loc3=0
  1031. mov loc4=0
  1032. mov loc5=0
  1033. mov loc6=0
  1034. mov loc7=0
  1035. (pRecurse) br.call.dptk.few b0=rse_clear_invalid
  1036. ;;
  1037. mov loc8=0
  1038. mov loc9=0
  1039. cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
  1040. mov loc10=0
  1041. mov loc11=0
  1042. (pReturn) br.ret.dptk.many b0
  1043. #endif /* !CONFIG_ITANIUM */
  1044. # undef pRecurse
  1045. # undef pReturn
  1046. ;;
  1047. alloc r17=ar.pfs,0,0,0,0 // drop current register frame
  1048. ;;
  1049. loadrs
  1050. ;;
  1051. skip_rbs_switch:
  1052. mov ar.unat=r25 // M2
  1053. (pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22
  1054. (pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise
  1055. ;;
  1056. (pUStk) mov ar.bspstore=r23 // M2
  1057. (pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp
  1058. (pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise
  1059. ;;
  1060. MOV_TO_IPSR(p0, r29, r25) // M2
  1061. mov ar.pfs=r26 // I0
  1062. (pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise
  1063. MOV_TO_IFS(p9, r30, r25)// M2
  1064. mov b0=r21 // I0
  1065. (pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise
  1066. mov ar.fpsr=r20 // M2
  1067. MOV_TO_IIP(r28, r25) // M2
  1068. nop 0
  1069. ;;
  1070. (pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode
  1071. nop 0
  1072. (pLvSys)mov r2=r0
  1073. mov ar.rsc=r27 // M2
  1074. mov pr=r31,-1 // I0
  1075. RFI // B
  1076. /*
  1077. * On entry:
  1078. * r20 = &current->thread_info->pre_count (if CONFIG_PREEMPTION)
  1079. * r31 = current->thread_info->flags
  1080. * On exit:
  1081. * p6 = TRUE if work-pending-check needs to be redone
  1082. *
  1083. * Interrupts are disabled on entry, reenabled depend on work, and
  1084. * disabled on exit.
  1085. */
  1086. .work_pending_syscall:
  1087. add r2=-8,r2
  1088. add r3=-8,r3
  1089. ;;
  1090. st8 [r2]=r8
  1091. st8 [r3]=r10
  1092. .work_pending:
  1093. tbit.z p6,p0=r31,TIF_NEED_RESCHED // is resched not needed?
  1094. (p6) br.cond.sptk.few .notify
  1095. br.call.spnt.many rp=preempt_schedule_irq
  1096. .ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 (re-check)
  1097. (pLvSys)br.cond.sptk.few ia64_work_pending_syscall_end
  1098. br.cond.sptk.many .work_processed_kernel
  1099. .notify:
  1100. (pUStk) br.call.spnt.many rp=notify_resume_user
  1101. .ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 (don't re-check)
  1102. (pLvSys)br.cond.sptk.few ia64_work_pending_syscall_end
  1103. br.cond.sptk.many .work_processed_kernel
  1104. .global ia64_work_pending_syscall_end;
  1105. ia64_work_pending_syscall_end:
  1106. adds r2=PT(R8)+16,r12
  1107. adds r3=PT(R10)+16,r12
  1108. ;;
  1109. ld8 r8=[r2]
  1110. ld8 r10=[r3]
  1111. br.cond.sptk.many ia64_work_processed_syscall
  1112. END(ia64_leave_kernel)
  1113. ENTRY(handle_syscall_error)
  1114. /*
  1115. * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
  1116. * lead us to mistake a negative return value as a failed syscall. Those syscall
  1117. * must deposit a non-zero value in pt_regs.r8 to indicate an error. If
  1118. * pt_regs.r8 is zero, we assume that the call completed successfully.
  1119. */
  1120. PT_REGS_UNWIND_INFO(0)
  1121. ld8 r3=[r2] // load pt_regs.r8
  1122. ;;
  1123. cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
  1124. ;;
  1125. (p7) mov r10=-1
  1126. (p7) sub r8=0,r8 // negate return value to get errno
  1127. br.cond.sptk ia64_leave_syscall
  1128. END(handle_syscall_error)
  1129. /*
  1130. * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
  1131. * in case a system call gets restarted.
  1132. */
  1133. GLOBAL_ENTRY(ia64_invoke_schedule_tail)
  1134. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  1135. alloc loc1=ar.pfs,8,2,1,0
  1136. mov loc0=rp
  1137. mov out0=r8 // Address of previous task
  1138. ;;
  1139. br.call.sptk.many rp=schedule_tail
  1140. .ret11: mov ar.pfs=loc1
  1141. mov rp=loc0
  1142. br.ret.sptk.many rp
  1143. END(ia64_invoke_schedule_tail)
  1144. /*
  1145. * Setup stack and call do_notify_resume_user(), keeping interrupts
  1146. * disabled.
  1147. *
  1148. * Note that pSys and pNonSys need to be set up by the caller.
  1149. * We declare 8 input registers so the system call args get preserved,
  1150. * in case we need to restart a system call.
  1151. */
  1152. GLOBAL_ENTRY(notify_resume_user)
  1153. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  1154. alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
  1155. mov r9=ar.unat
  1156. mov loc0=rp // save return address
  1157. mov out0=0 // there is no "oldset"
  1158. adds out1=8,sp // out1=&sigscratch->ar_pfs
  1159. (pSys) mov out2=1 // out2==1 => we're in a syscall
  1160. ;;
  1161. (pNonSys) mov out2=0 // out2==0 => not a syscall
  1162. .fframe 16
  1163. .spillsp ar.unat, 16
  1164. st8 [sp]=r9,-16 // allocate space for ar.unat and save it
  1165. st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch
  1166. .body
  1167. br.call.sptk.many rp=do_notify_resume_user
  1168. .ret15: .restore sp
  1169. adds sp=16,sp // pop scratch stack space
  1170. ;;
  1171. ld8 r9=[sp] // load new unat from sigscratch->scratch_unat
  1172. mov rp=loc0
  1173. ;;
  1174. mov ar.unat=r9
  1175. mov ar.pfs=loc1
  1176. br.ret.sptk.many rp
  1177. END(notify_resume_user)
  1178. ENTRY(sys_rt_sigreturn)
  1179. PT_REGS_UNWIND_INFO(0)
  1180. /*
  1181. * Allocate 8 input registers since ptrace() may clobber them
  1182. */
  1183. alloc r2=ar.pfs,8,0,1,0
  1184. .prologue
  1185. PT_REGS_SAVES(16)
  1186. adds sp=-16,sp
  1187. .body
  1188. cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall...
  1189. ;;
  1190. /*
  1191. * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
  1192. * syscall-entry path does not save them we save them here instead. Note: we
  1193. * don't need to save any other registers that are not saved by the stream-lined
  1194. * syscall path, because restore_sigcontext() restores them.
  1195. */
  1196. adds r16=PT(F6)+32,sp
  1197. adds r17=PT(F7)+32,sp
  1198. ;;
  1199. stf.spill [r16]=f6,32
  1200. stf.spill [r17]=f7,32
  1201. ;;
  1202. stf.spill [r16]=f8,32
  1203. stf.spill [r17]=f9,32
  1204. ;;
  1205. stf.spill [r16]=f10
  1206. stf.spill [r17]=f11
  1207. adds out0=16,sp // out0 = &sigscratch
  1208. br.call.sptk.many rp=ia64_rt_sigreturn
  1209. .ret19: .restore sp,0
  1210. adds sp=16,sp
  1211. ;;
  1212. ld8 r9=[sp] // load new ar.unat
  1213. mov.sptk b7=r8,ia64_leave_kernel
  1214. ;;
  1215. mov ar.unat=r9
  1216. br.many b7
  1217. END(sys_rt_sigreturn)
  1218. GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
  1219. .prologue
  1220. /*
  1221. * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
  1222. */
  1223. mov r16=r0
  1224. DO_SAVE_SWITCH_STACK
  1225. br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt
  1226. .ret21: .body
  1227. DO_LOAD_SWITCH_STACK
  1228. br.cond.sptk.many rp // goes to ia64_leave_kernel
  1229. END(ia64_prepare_handle_unaligned)
  1230. //
  1231. // unw_init_running(void (*callback)(info, arg), void *arg)
  1232. //
  1233. # define EXTRA_FRAME_SIZE ((UNW_FRAME_INFO_SIZE+15)&~15)
  1234. GLOBAL_ENTRY(unw_init_running)
  1235. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
  1236. alloc loc1=ar.pfs,2,3,3,0
  1237. ;;
  1238. ld8 loc2=[in0],8
  1239. mov loc0=rp
  1240. mov r16=loc1
  1241. DO_SAVE_SWITCH_STACK
  1242. .body
  1243. .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
  1244. .fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
  1245. SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
  1246. adds sp=-EXTRA_FRAME_SIZE,sp
  1247. .body
  1248. ;;
  1249. adds out0=16,sp // &info
  1250. mov out1=r13 // current
  1251. adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack
  1252. br.call.sptk.many rp=unw_init_frame_info
  1253. 1: adds out0=16,sp // &info
  1254. mov b6=loc2
  1255. mov loc2=gp // save gp across indirect function call
  1256. ;;
  1257. ld8 gp=[in0]
  1258. mov out1=in1 // arg
  1259. br.call.sptk.many rp=b6 // invoke the callback function
  1260. 1: mov gp=loc2 // restore gp
  1261. // For now, we don't allow changing registers from within
  1262. // unw_init_running; if we ever want to allow that, we'd
  1263. // have to do a load_switch_stack here:
  1264. .restore sp
  1265. adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
  1266. mov ar.pfs=loc1
  1267. mov rp=loc0
  1268. br.ret.sptk.many rp
  1269. END(unw_init_running)
  1270. EXPORT_SYMBOL(unw_init_running)
  1271. #ifdef CONFIG_FUNCTION_TRACER
  1272. #ifdef CONFIG_DYNAMIC_FTRACE
  1273. GLOBAL_ENTRY(_mcount)
  1274. br ftrace_stub
  1275. END(_mcount)
  1276. EXPORT_SYMBOL(_mcount)
  1277. .here:
  1278. br.ret.sptk.many b0
  1279. GLOBAL_ENTRY(ftrace_caller)
  1280. alloc out0 = ar.pfs, 8, 0, 4, 0
  1281. mov out3 = r0
  1282. ;;
  1283. mov out2 = b0
  1284. add r3 = 0x20, r3
  1285. mov out1 = r1;
  1286. br.call.sptk.many b0 = ftrace_patch_gp
  1287. //this might be called from module, so we must patch gp
  1288. ftrace_patch_gp:
  1289. movl gp=__gp
  1290. mov b0 = r3
  1291. ;;
  1292. .global ftrace_call;
  1293. ftrace_call:
  1294. {
  1295. .mlx
  1296. nop.m 0x0
  1297. movl r3 = .here;;
  1298. }
  1299. alloc loc0 = ar.pfs, 4, 4, 2, 0
  1300. ;;
  1301. mov loc1 = b0
  1302. mov out0 = b0
  1303. mov loc2 = r8
  1304. mov loc3 = r15
  1305. ;;
  1306. adds out0 = -MCOUNT_INSN_SIZE, out0
  1307. mov out1 = in2
  1308. mov b6 = r3
  1309. br.call.sptk.many b0 = b6
  1310. ;;
  1311. mov ar.pfs = loc0
  1312. mov b0 = loc1
  1313. mov r8 = loc2
  1314. mov r15 = loc3
  1315. br ftrace_stub
  1316. ;;
  1317. END(ftrace_caller)
  1318. #else
  1319. GLOBAL_ENTRY(_mcount)
  1320. movl r2 = ftrace_stub
  1321. movl r3 = ftrace_trace_function;;
  1322. ld8 r3 = [r3];;
  1323. ld8 r3 = [r3];;
  1324. cmp.eq p7,p0 = r2, r3
  1325. (p7) br.sptk.many ftrace_stub
  1326. ;;
  1327. alloc loc0 = ar.pfs, 4, 4, 2, 0
  1328. ;;
  1329. mov loc1 = b0
  1330. mov out0 = b0
  1331. mov loc2 = r8
  1332. mov loc3 = r15
  1333. ;;
  1334. adds out0 = -MCOUNT_INSN_SIZE, out0
  1335. mov out1 = in2
  1336. mov b6 = r3
  1337. br.call.sptk.many b0 = b6
  1338. ;;
  1339. mov ar.pfs = loc0
  1340. mov b0 = loc1
  1341. mov r8 = loc2
  1342. mov r15 = loc3
  1343. br ftrace_stub
  1344. ;;
  1345. END(_mcount)
  1346. #endif
  1347. GLOBAL_ENTRY(ftrace_stub)
  1348. mov r3 = b0
  1349. movl r2 = _mcount_ret_helper
  1350. ;;
  1351. mov b6 = r2
  1352. mov b7 = r3
  1353. br.ret.sptk.many b6
  1354. _mcount_ret_helper:
  1355. mov b0 = r42
  1356. mov r1 = r41
  1357. mov ar.pfs = r40
  1358. br b7
  1359. END(ftrace_stub)
  1360. #endif /* CONFIG_FUNCTION_TRACER */
  1361. #define __SYSCALL(nr, entry) data8 entry
  1362. .rodata
  1363. .align 8
  1364. .globl sys_call_table
  1365. sys_call_table:
  1366. #include <asm/syscall_table.h>