decode.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385
  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * arch/arm/probes/decode.h
  4. *
  5. * Copyright (C) 2011 Jon Medhurst <[email protected]>.
  6. *
  7. * Some contents moved here from arch/arm/include/asm/kprobes.h which is
  8. * Copyright (C) 2006, 2007 Motorola Inc.
  9. */
  10. #ifndef _ARM_KERNEL_PROBES_H
  11. #define _ARM_KERNEL_PROBES_H
  12. #include <linux/types.h>
  13. #include <linux/stddef.h>
  14. #include <asm/probes.h>
  15. #include <asm/ptrace.h>
  16. #include <asm/kprobes.h>
  17. void __init arm_probes_decode_init(void);
  18. extern probes_check_cc * const probes_condition_checks[16];
  19. #if __LINUX_ARM_ARCH__ >= 7
  20. /* str_pc_offset is architecturally defined from ARMv7 onwards */
  21. #define str_pc_offset 8
  22. #define find_str_pc_offset()
  23. #else /* __LINUX_ARM_ARCH__ < 7 */
  24. /* We need a run-time check to determine str_pc_offset */
  25. extern int str_pc_offset;
  26. void __init find_str_pc_offset(void);
  27. #endif
  28. static inline void __kprobes bx_write_pc(long pcv, struct pt_regs *regs)
  29. {
  30. long cpsr = regs->ARM_cpsr;
  31. if (pcv & 0x1) {
  32. cpsr |= PSR_T_BIT;
  33. pcv &= ~0x1;
  34. } else {
  35. cpsr &= ~PSR_T_BIT;
  36. pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */
  37. }
  38. regs->ARM_cpsr = cpsr;
  39. regs->ARM_pc = pcv;
  40. }
  41. #if __LINUX_ARM_ARCH__ >= 6
  42. /* Kernels built for >= ARMv6 should never run on <= ARMv5 hardware, so... */
  43. #define load_write_pc_interworks true
  44. #define test_load_write_pc_interworking()
  45. #else /* __LINUX_ARM_ARCH__ < 6 */
  46. /* We need run-time testing to determine if load_write_pc() should interwork. */
  47. extern bool load_write_pc_interworks;
  48. void __init test_load_write_pc_interworking(void);
  49. #endif
  50. static inline void __kprobes load_write_pc(long pcv, struct pt_regs *regs)
  51. {
  52. if (load_write_pc_interworks)
  53. bx_write_pc(pcv, regs);
  54. else
  55. regs->ARM_pc = pcv;
  56. }
  57. #if __LINUX_ARM_ARCH__ >= 7
  58. #define alu_write_pc_interworks true
  59. #define test_alu_write_pc_interworking()
  60. #elif __LINUX_ARM_ARCH__ <= 5
  61. /* Kernels built for <= ARMv5 should never run on >= ARMv6 hardware, so... */
  62. #define alu_write_pc_interworks false
  63. #define test_alu_write_pc_interworking()
  64. #else /* __LINUX_ARM_ARCH__ == 6 */
  65. /* We could be an ARMv6 binary on ARMv7 hardware so we need a run-time check. */
  66. extern bool alu_write_pc_interworks;
  67. void __init test_alu_write_pc_interworking(void);
  68. #endif /* __LINUX_ARM_ARCH__ == 6 */
  69. static inline void __kprobes alu_write_pc(long pcv, struct pt_regs *regs)
  70. {
  71. if (alu_write_pc_interworks)
  72. bx_write_pc(pcv, regs);
  73. else
  74. regs->ARM_pc = pcv;
  75. }
  76. /*
  77. * Test if load/store instructions writeback the address register.
  78. * if P (bit 24) == 0 or W (bit 21) == 1
  79. */
  80. #define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
  81. /*
  82. * The following definitions and macros are used to build instruction
  83. * decoding tables for use by probes_decode_insn.
  84. *
  85. * These tables are a concatenation of entries each of which consist of one of
  86. * the decode_* structs. All of the fields in every type of decode structure
  87. * are of the union type decode_item, therefore the entire decode table can be
  88. * viewed as an array of these and declared like:
  89. *
  90. * static const union decode_item table_name[] = {};
  91. *
  92. * In order to construct each entry in the table, macros are used to
  93. * initialise a number of sequential decode_item values in a layout which
  94. * matches the relevant struct. E.g. DECODE_SIMULATE initialise a struct
  95. * decode_simulate by initialising four decode_item objects like this...
  96. *
  97. * {.bits = _type},
  98. * {.bits = _mask},
  99. * {.bits = _value},
  100. * {.action = _handler},
  101. *
  102. * Initialising a specified member of the union means that the compiler
  103. * will produce a warning if the argument is of an incorrect type.
  104. *
  105. * Below is a list of each of the macros used to initialise entries and a
  106. * description of the action performed when that entry is matched to an
  107. * instruction. A match is found when (instruction & mask) == value.
  108. *
  109. * DECODE_TABLE(mask, value, table)
  110. * Instruction decoding jumps to parsing the new sub-table 'table'.
  111. *
  112. * DECODE_CUSTOM(mask, value, decoder)
  113. * The value of 'decoder' is used as an index into the array of
  114. * action functions, and the retrieved decoder function is invoked
  115. * to complete decoding of the instruction.
  116. *
  117. * DECODE_SIMULATE(mask, value, handler)
  118. * The probes instruction handler is set to the value found by
  119. * indexing into the action array using the value of 'handler'. This
  120. * will be used to simulate the instruction when the probe is hit.
  121. * Decoding returns with INSN_GOOD_NO_SLOT.
  122. *
  123. * DECODE_EMULATE(mask, value, handler)
  124. * The probes instruction handler is set to the value found by
  125. * indexing into the action array using the value of 'handler'. This
  126. * will be used to emulate the instruction when the probe is hit. The
  127. * modified instruction (see below) is placed in the probes instruction
  128. * slot so it may be called by the emulation code. Decoding returns
  129. * with INSN_GOOD.
  130. *
  131. * DECODE_REJECT(mask, value)
  132. * Instruction decoding fails with INSN_REJECTED
  133. *
  134. * DECODE_OR(mask, value)
  135. * This allows the mask/value test of multiple table entries to be
  136. * logically ORed. Once an 'or' entry is matched the decoding action to
  137. * be performed is that of the next entry which isn't an 'or'. E.g.
  138. *
  139. * DECODE_OR (mask1, value1)
  140. * DECODE_OR (mask2, value2)
  141. * DECODE_SIMULATE (mask3, value3, simulation_handler)
  142. *
  143. * This means that if any of the three mask/value pairs match the
  144. * instruction being decoded, then 'simulation_handler' will be used
  145. * for it.
  146. *
  147. * Both the SIMULATE and EMULATE macros have a second form which take an
  148. * additional 'regs' argument.
  149. *
  150. * DECODE_SIMULATEX(mask, value, handler, regs)
  151. * DECODE_EMULATEX (mask, value, handler, regs)
  152. *
  153. * These are used to specify what kind of CPU register is encoded in each of the
  154. * least significant 5 nibbles of the instruction being decoded. The regs value
  155. * is specified using the REGS macro, this takes any of the REG_TYPE_* values
  156. * from enum decode_reg_type as arguments; only the '*' part of the name is
  157. * given. E.g.
  158. *
  159. * REGS(0, ANY, NOPC, 0, ANY)
  160. *
  161. * This indicates an instruction is encoded like:
  162. *
  163. * bits 19..16 ignore
  164. * bits 15..12 any register allowed here
  165. * bits 11.. 8 any register except PC allowed here
  166. * bits 7.. 4 ignore
  167. * bits 3.. 0 any register allowed here
  168. *
  169. * This register specification is checked after a decode table entry is found to
  170. * match an instruction (through the mask/value test). Any invalid register then
  171. * found in the instruction will cause decoding to fail with INSN_REJECTED. In
  172. * the above example this would happen if bits 11..8 of the instruction were
  173. * 1111, indicating R15 or PC.
  174. *
  175. * As well as checking for legal combinations of registers, this data is also
  176. * used to modify the registers encoded in the instructions so that an
  177. * emulation routines can use it. (See decode_regs() and INSN_NEW_BITS.)
  178. *
  179. * Here is a real example which matches ARM instructions of the form
  180. * "AND <Rd>,<Rn>,<Rm>,<shift> <Rs>"
  181. *
  182. * DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
  183. * REGS(ANY, ANY, NOPC, 0, ANY)),
  184. * ^ ^ ^ ^
  185. * Rn Rd Rs Rm
  186. *
  187. * Decoding the instruction "AND R4, R5, R6, ASL R15" will be rejected because
  188. * Rs == R15
  189. *
  190. * Decoding the instruction "AND R4, R5, R6, ASL R7" will be accepted and the
  191. * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
  192. * the kprobes instruction slot. This can then be called later by the handler
  193. * function emulate_rd12rn16rm0rs8_rwflags (a pointer to which is retrieved from
  194. * the indicated slot in the action array), in order to simulate the instruction.
  195. */
  196. enum decode_type {
  197. DECODE_TYPE_END,
  198. DECODE_TYPE_TABLE,
  199. DECODE_TYPE_CUSTOM,
  200. DECODE_TYPE_SIMULATE,
  201. DECODE_TYPE_EMULATE,
  202. DECODE_TYPE_OR,
  203. DECODE_TYPE_REJECT,
  204. NUM_DECODE_TYPES /* Must be last enum */
  205. };
  206. #define DECODE_TYPE_BITS 4
  207. #define DECODE_TYPE_MASK ((1 << DECODE_TYPE_BITS) - 1)
  208. enum decode_reg_type {
  209. REG_TYPE_NONE = 0, /* Not a register, ignore */
  210. REG_TYPE_ANY, /* Any register allowed */
  211. REG_TYPE_SAMEAS16, /* Register should be same as that at bits 19..16 */
  212. REG_TYPE_SP, /* Register must be SP */
  213. REG_TYPE_PC, /* Register must be PC */
  214. REG_TYPE_NOSP, /* Register must not be SP */
  215. REG_TYPE_NOSPPC, /* Register must not be SP or PC */
  216. REG_TYPE_NOPC, /* Register must not be PC */
  217. REG_TYPE_NOPCWB, /* No PC if load/store write-back flag also set */
  218. /* The following types are used when the encoding for PC indicates
  219. * another instruction form. This distiction only matters for test
  220. * case coverage checks.
  221. */
  222. REG_TYPE_NOPCX, /* Register must not be PC */
  223. REG_TYPE_NOSPPCX, /* Register must not be SP or PC */
  224. /* Alias to allow '0' arg to be used in REGS macro. */
  225. REG_TYPE_0 = REG_TYPE_NONE
  226. };
  227. #define REGS(r16, r12, r8, r4, r0) \
  228. (((REG_TYPE_##r16) << 16) + \
  229. ((REG_TYPE_##r12) << 12) + \
  230. ((REG_TYPE_##r8) << 8) + \
  231. ((REG_TYPE_##r4) << 4) + \
  232. (REG_TYPE_##r0))
  233. union decode_item {
  234. u32 bits;
  235. const union decode_item *table;
  236. int action;
  237. };
  238. struct decode_header;
  239. typedef enum probes_insn (probes_custom_decode_t)(probes_opcode_t,
  240. struct arch_probes_insn *,
  241. const struct decode_header *);
  242. union decode_action {
  243. probes_insn_handler_t *handler;
  244. probes_custom_decode_t *decoder;
  245. };
  246. typedef enum probes_insn (probes_check_t)(probes_opcode_t,
  247. struct arch_probes_insn *,
  248. const struct decode_header *);
  249. struct decode_checker {
  250. probes_check_t *checker;
  251. };
  252. #define DECODE_END \
  253. {.bits = DECODE_TYPE_END}
  254. struct decode_header {
  255. union decode_item type_regs;
  256. union decode_item mask;
  257. union decode_item value;
  258. };
  259. #define DECODE_HEADER(_type, _mask, _value, _regs) \
  260. {.bits = (_type) | ((_regs) << DECODE_TYPE_BITS)}, \
  261. {.bits = (_mask)}, \
  262. {.bits = (_value)}
  263. struct decode_table {
  264. struct decode_header header;
  265. union decode_item table;
  266. };
  267. #define DECODE_TABLE(_mask, _value, _table) \
  268. DECODE_HEADER(DECODE_TYPE_TABLE, _mask, _value, 0), \
  269. {.table = (_table)}
  270. struct decode_custom {
  271. struct decode_header header;
  272. union decode_item decoder;
  273. };
  274. #define DECODE_CUSTOM(_mask, _value, _decoder) \
  275. DECODE_HEADER(DECODE_TYPE_CUSTOM, _mask, _value, 0), \
  276. {.action = (_decoder)}
  277. struct decode_simulate {
  278. struct decode_header header;
  279. union decode_item handler;
  280. };
  281. #define DECODE_SIMULATEX(_mask, _value, _handler, _regs) \
  282. DECODE_HEADER(DECODE_TYPE_SIMULATE, _mask, _value, _regs), \
  283. {.action = (_handler)}
  284. #define DECODE_SIMULATE(_mask, _value, _handler) \
  285. DECODE_SIMULATEX(_mask, _value, _handler, 0)
  286. struct decode_emulate {
  287. struct decode_header header;
  288. union decode_item handler;
  289. };
  290. #define DECODE_EMULATEX(_mask, _value, _handler, _regs) \
  291. DECODE_HEADER(DECODE_TYPE_EMULATE, _mask, _value, _regs), \
  292. {.action = (_handler)}
  293. #define DECODE_EMULATE(_mask, _value, _handler) \
  294. DECODE_EMULATEX(_mask, _value, _handler, 0)
  295. struct decode_or {
  296. struct decode_header header;
  297. };
  298. #define DECODE_OR(_mask, _value) \
  299. DECODE_HEADER(DECODE_TYPE_OR, _mask, _value, 0)
  300. enum probes_insn {
  301. INSN_REJECTED,
  302. INSN_GOOD,
  303. INSN_GOOD_NO_SLOT
  304. };
  305. struct decode_reject {
  306. struct decode_header header;
  307. };
  308. #define DECODE_REJECT(_mask, _value) \
  309. DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
  310. probes_insn_handler_t probes_simulate_nop;
  311. probes_insn_handler_t probes_emulate_none;
  312. int __kprobes
  313. probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
  314. const union decode_item *table, bool thumb, bool emulate,
  315. const union decode_action *actions,
  316. const struct decode_checker **checkers);
  317. #endif