bpf_jit_32.h 9.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Just-In-Time compiler for BPF filters on 32bit ARM
  4. *
  5. * Copyright (c) 2011 Mircea Gherzan <[email protected]>
  6. */
  7. #ifndef PFILTER_OPCODES_ARM_H
  8. #define PFILTER_OPCODES_ARM_H
  9. /* ARM 32bit Registers */
  10. #define ARM_R0 0
  11. #define ARM_R1 1
  12. #define ARM_R2 2
  13. #define ARM_R3 3
  14. #define ARM_R4 4
  15. #define ARM_R5 5
  16. #define ARM_R6 6
  17. #define ARM_R7 7
  18. #define ARM_R8 8
  19. #define ARM_R9 9
  20. #define ARM_R10 10
  21. #define ARM_FP 11 /* Frame Pointer */
  22. #define ARM_IP 12 /* Intra-procedure scratch register */
  23. #define ARM_SP 13 /* Stack pointer: as load/store base reg */
  24. #define ARM_LR 14 /* Link Register */
  25. #define ARM_PC 15 /* Program counter */
  26. #define ARM_COND_EQ 0x0 /* == */
  27. #define ARM_COND_NE 0x1 /* != */
  28. #define ARM_COND_CS 0x2 /* unsigned >= */
  29. #define ARM_COND_HS ARM_COND_CS
  30. #define ARM_COND_CC 0x3 /* unsigned < */
  31. #define ARM_COND_LO ARM_COND_CC
  32. #define ARM_COND_MI 0x4 /* < 0 */
  33. #define ARM_COND_PL 0x5 /* >= 0 */
  34. #define ARM_COND_VS 0x6 /* Signed Overflow */
  35. #define ARM_COND_VC 0x7 /* No Signed Overflow */
  36. #define ARM_COND_HI 0x8 /* unsigned > */
  37. #define ARM_COND_LS 0x9 /* unsigned <= */
  38. #define ARM_COND_GE 0xa /* Signed >= */
  39. #define ARM_COND_LT 0xb /* Signed < */
  40. #define ARM_COND_GT 0xc /* Signed > */
  41. #define ARM_COND_LE 0xd /* Signed <= */
  42. #define ARM_COND_AL 0xe /* None */
  43. /* register shift types */
  44. #define SRTYPE_LSL 0
  45. #define SRTYPE_LSR 1
  46. #define SRTYPE_ASR 2
  47. #define SRTYPE_ROR 3
  48. #define SRTYPE_ASL (SRTYPE_LSL)
  49. #define ARM_INST_ADD_R 0x00800000
  50. #define ARM_INST_ADDS_R 0x00900000
  51. #define ARM_INST_ADC_R 0x00a00000
  52. #define ARM_INST_ADC_I 0x02a00000
  53. #define ARM_INST_ADD_I 0x02800000
  54. #define ARM_INST_ADDS_I 0x02900000
  55. #define ARM_INST_AND_R 0x00000000
  56. #define ARM_INST_ANDS_R 0x00100000
  57. #define ARM_INST_AND_I 0x02000000
  58. #define ARM_INST_BIC_R 0x01c00000
  59. #define ARM_INST_BIC_I 0x03c00000
  60. #define ARM_INST_B 0x0a000000
  61. #define ARM_INST_BX 0x012FFF10
  62. #define ARM_INST_BLX_R 0x012fff30
  63. #define ARM_INST_CMP_R 0x01500000
  64. #define ARM_INST_CMP_I 0x03500000
  65. #define ARM_INST_EOR_R 0x00200000
  66. #define ARM_INST_EOR_I 0x02200000
  67. #define ARM_INST_LDST__U 0x00800000
  68. #define ARM_INST_LDST__IMM12 0x00000fff
  69. #define ARM_INST_LDRB_I 0x05500000
  70. #define ARM_INST_LDRB_R 0x07d00000
  71. #define ARM_INST_LDRD_I 0x014000d0
  72. #define ARM_INST_LDRH_I 0x015000b0
  73. #define ARM_INST_LDRH_R 0x019000b0
  74. #define ARM_INST_LDR_I 0x05100000
  75. #define ARM_INST_LDR_R 0x07900000
  76. #define ARM_INST_LDM 0x08900000
  77. #define ARM_INST_LDM_IA 0x08b00000
  78. #define ARM_INST_LSL_I 0x01a00000
  79. #define ARM_INST_LSL_R 0x01a00010
  80. #define ARM_INST_LSR_I 0x01a00020
  81. #define ARM_INST_LSR_R 0x01a00030
  82. #define ARM_INST_ASR_I 0x01a00040
  83. #define ARM_INST_ASR_R 0x01a00050
  84. #define ARM_INST_MOV_R 0x01a00000
  85. #define ARM_INST_MOVS_R 0x01b00000
  86. #define ARM_INST_MOV_I 0x03a00000
  87. #define ARM_INST_MOVW 0x03000000
  88. #define ARM_INST_MOVT 0x03400000
  89. #define ARM_INST_MUL 0x00000090
  90. #define ARM_INST_POP 0x08bd0000
  91. #define ARM_INST_PUSH 0x092d0000
  92. #define ARM_INST_ORR_R 0x01800000
  93. #define ARM_INST_ORRS_R 0x01900000
  94. #define ARM_INST_ORR_I 0x03800000
  95. #define ARM_INST_REV 0x06bf0f30
  96. #define ARM_INST_REV16 0x06bf0fb0
  97. #define ARM_INST_RSB_I 0x02600000
  98. #define ARM_INST_RSBS_I 0x02700000
  99. #define ARM_INST_RSC_I 0x02e00000
  100. #define ARM_INST_SUB_R 0x00400000
  101. #define ARM_INST_SUBS_R 0x00500000
  102. #define ARM_INST_RSB_R 0x00600000
  103. #define ARM_INST_SUB_I 0x02400000
  104. #define ARM_INST_SUBS_I 0x02500000
  105. #define ARM_INST_SBC_I 0x02c00000
  106. #define ARM_INST_SBC_R 0x00c00000
  107. #define ARM_INST_SBCS_R 0x00d00000
  108. #define ARM_INST_STR_I 0x05000000
  109. #define ARM_INST_STRB_I 0x05400000
  110. #define ARM_INST_STRD_I 0x014000f0
  111. #define ARM_INST_STRH_I 0x014000b0
  112. #define ARM_INST_TST_R 0x01100000
  113. #define ARM_INST_TST_I 0x03100000
  114. #define ARM_INST_UDIV 0x0730f010
  115. #define ARM_INST_UMULL 0x00800090
  116. #define ARM_INST_MLS 0x00600090
  117. #define ARM_INST_UXTH 0x06ff0070
  118. /*
  119. * Use a suitable undefined instruction to use for ARM/Thumb2 faulting.
  120. * We need to be careful not to conflict with those used by other modules
  121. * (BUG, kprobes, etc) and the register_undef_hook() system.
  122. *
  123. * The ARM architecture reference manual guarantees that the following
  124. * instruction space will produce an undefined instruction exception on
  125. * all CPUs:
  126. *
  127. * ARM: xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx ARMv7-AR, section A5.4
  128. * Thumb: 1101 1110 xxxx xxxx ARMv7-M, section A5.2.6
  129. */
  130. #define ARM_INST_UDF 0xe7fddef1
  131. /* register */
  132. #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm))
  133. /* immediate */
  134. #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm))
  135. /* register with register-shift */
  136. #define _AL3_SR(inst) (inst | (1 << 4))
  137. #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm)
  138. #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm)
  139. #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm)
  140. #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm)
  141. #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm)
  142. #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm)
  143. #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm)
  144. #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm)
  145. #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm)
  146. #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm)
  147. #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm)
  148. #define ARM_B(imm24) (ARM_INST_B | ((imm24) & 0xffffff))
  149. #define ARM_BX(rm) (ARM_INST_BX | (rm))
  150. #define ARM_BLX_R(rm) (ARM_INST_BLX_R | (rm))
  151. #define ARM_CMP_R(rn, rm) _AL3_R(ARM_INST_CMP, 0, rn, rm)
  152. #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm)
  153. #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm)
  154. #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm)
  155. #define ARM_LDR_R(rt, rn, rm) (ARM_INST_LDR_R | ARM_INST_LDST__U \
  156. | (rt) << 12 | (rn) << 16 \
  157. | (rm))
  158. #define ARM_LDR_R_SI(rt, rn, rm, type, imm) \
  159. (ARM_INST_LDR_R | ARM_INST_LDST__U \
  160. | (rt) << 12 | (rn) << 16 \
  161. | (imm) << 7 | (type) << 5 | (rm))
  162. #define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | ARM_INST_LDST__U \
  163. | (rt) << 12 | (rn) << 16 \
  164. | (rm))
  165. #define ARM_LDRH_R(rt, rn, rm) (ARM_INST_LDRH_R | ARM_INST_LDST__U \
  166. | (rt) << 12 | (rn) << 16 \
  167. | (rm))
  168. #define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs))
  169. #define ARM_LDM_IA(rn, regs) (ARM_INST_LDM_IA | (rn) << 16 | (regs))
  170. #define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8)
  171. #define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7)
  172. #define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8)
  173. #define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7)
  174. #define ARM_ASR_R(rd, rn, rm) (_AL3_R(ARM_INST_ASR, rd, 0, rn) | (rm) << 8)
  175. #define ARM_ASR_I(rd, rn, imm) (_AL3_I(ARM_INST_ASR, rd, 0, rn) | (imm) << 7)
  176. #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm)
  177. #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm)
  178. #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm)
  179. #define ARM_MOV_SR(rd, rm, type, rs) \
  180. (_AL3_SR(ARM_MOV_R(rd, rm)) | (type) << 5 | (rs) << 8)
  181. #define ARM_MOV_SI(rd, rm, type, imm6) \
  182. (ARM_MOV_R(rd, rm) | (type) << 5 | (imm6) << 7)
  183. #define ARM_MOVW(rd, imm) \
  184. (ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
  185. #define ARM_MOVT(rd, imm) \
  186. (ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff))
  187. #define ARM_MUL(rd, rm, rn) (ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn))
  188. #define ARM_POP(regs) (ARM_INST_POP | (regs))
  189. #define ARM_PUSH(regs) (ARM_INST_PUSH | (regs))
  190. #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm)
  191. #define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm)
  192. #define ARM_ORR_SR(rd, rn, rm, type, rs) \
  193. (_AL3_SR(ARM_ORR_R(rd, rn, rm)) | (type) << 5 | (rs) << 8)
  194. #define ARM_ORRS_R(rd, rn, rm) _AL3_R(ARM_INST_ORRS, rd, rn, rm)
  195. #define ARM_ORRS_SR(rd, rn, rm, type, rs) \
  196. (_AL3_SR(ARM_ORRS_R(rd, rn, rm)) | (type) << 5 | (rs) << 8)
  197. #define ARM_ORR_SI(rd, rn, rm, type, imm6) \
  198. (ARM_ORR_R(rd, rn, rm) | (type) << 5 | (imm6) << 7)
  199. #define ARM_ORRS_SI(rd, rn, rm, type, imm6) \
  200. (ARM_ORRS_R(rd, rn, rm) | (type) << 5 | (imm6) << 7)
  201. #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm))
  202. #define ARM_REV16(rd, rm) (ARM_INST_REV16 | (rd) << 12 | (rm))
  203. #define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm)
  204. #define ARM_RSBS_I(rd, rn, imm) _AL3_I(ARM_INST_RSBS, rd, rn, imm)
  205. #define ARM_RSC_I(rd, rn, imm) _AL3_I(ARM_INST_RSC, rd, rn, imm)
  206. #define ARM_SUB_R(rd, rn, rm) _AL3_R(ARM_INST_SUB, rd, rn, rm)
  207. #define ARM_SUBS_R(rd, rn, rm) _AL3_R(ARM_INST_SUBS, rd, rn, rm)
  208. #define ARM_RSB_R(rd, rn, rm) _AL3_R(ARM_INST_RSB, rd, rn, rm)
  209. #define ARM_SBC_R(rd, rn, rm) _AL3_R(ARM_INST_SBC, rd, rn, rm)
  210. #define ARM_SBCS_R(rd, rn, rm) _AL3_R(ARM_INST_SBCS, rd, rn, rm)
  211. #define ARM_SUB_I(rd, rn, imm) _AL3_I(ARM_INST_SUB, rd, rn, imm)
  212. #define ARM_SUBS_I(rd, rn, imm) _AL3_I(ARM_INST_SUBS, rd, rn, imm)
  213. #define ARM_SBC_I(rd, rn, imm) _AL3_I(ARM_INST_SBC, rd, rn, imm)
  214. #define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm)
  215. #define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm)
  216. #define ARM_UDIV(rd, rn, rm) (ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8)
  217. #define ARM_UMULL(rd_lo, rd_hi, rn, rm) (ARM_INST_UMULL | (rd_hi) << 16 \
  218. | (rd_lo) << 12 | (rm) << 8 | rn)
  219. #define ARM_MLS(rd, rn, rm, ra) (ARM_INST_MLS | (rd) << 16 | (rn) | (rm) << 8 \
  220. | (ra) << 12)
  221. #define ARM_UXTH(rd, rm) (ARM_INST_UXTH | (rd) << 12 | (rm))
  222. #endif /* PFILTER_OPCODES_ARM_H */