bpf_jit_32.c 54 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Just-In-Time compiler for eBPF filters on 32bit ARM
  4. *
  5. * Copyright (c) 2017 Shubham Bansal <[email protected]>
  6. * Copyright (c) 2011 Mircea Gherzan <[email protected]>
  7. */
  8. #include <linux/bpf.h>
  9. #include <linux/bitops.h>
  10. #include <linux/compiler.h>
  11. #include <linux/errno.h>
  12. #include <linux/filter.h>
  13. #include <linux/netdevice.h>
  14. #include <linux/string.h>
  15. #include <linux/slab.h>
  16. #include <linux/if_vlan.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/hwcap.h>
  19. #include <asm/opcodes.h>
  20. #include <asm/system_info.h>
  21. #include "bpf_jit_32.h"
  22. /*
  23. * eBPF prog stack layout:
  24. *
  25. * high
  26. * original ARM_SP => +-----+
  27. * | | callee saved registers
  28. * +-----+ <= (BPF_FP + SCRATCH_SIZE)
  29. * | ... | eBPF JIT scratch space
  30. * eBPF fp register => +-----+
  31. * (BPF_FP) | ... | eBPF prog stack
  32. * +-----+
  33. * |RSVD | JIT scratchpad
  34. * current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
  35. * | ... | caller-saved registers
  36. * +-----+
  37. * | ... | arguments passed on stack
  38. * ARM_SP during call => +-----|
  39. * | |
  40. * | ... | Function call stack
  41. * | |
  42. * +-----+
  43. * low
  44. *
  45. * The callee saved registers depends on whether frame pointers are enabled.
  46. * With frame pointers (to be compliant with the ABI):
  47. *
  48. * high
  49. * original ARM_SP => +--------------+ \
  50. * | pc | |
  51. * current ARM_FP => +--------------+ } callee saved registers
  52. * |r4-r9,fp,ip,lr| |
  53. * +--------------+ /
  54. * low
  55. *
  56. * Without frame pointers:
  57. *
  58. * high
  59. * original ARM_SP => +--------------+
  60. * | r4-r9,fp,lr | callee saved registers
  61. * current ARM_FP => +--------------+
  62. * low
  63. *
  64. * When popping registers off the stack at the end of a BPF function, we
  65. * reference them via the current ARM_FP register.
  66. *
  67. * Some eBPF operations are implemented via a call to a helper function.
  68. * Such calls are "invisible" in the eBPF code, so it is up to the calling
  69. * program to preserve any caller-saved ARM registers during the call. The
  70. * JIT emits code to push and pop those registers onto the stack, immediately
  71. * above the callee stack frame.
  72. */
  73. #define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
  74. 1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
  75. 1 << ARM_FP)
  76. #define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
  77. #define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
  78. #define CALLER_MASK (1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3)
  79. enum {
  80. /* Stack layout - these are offsets from (top of stack - 4) */
  81. BPF_R2_HI,
  82. BPF_R2_LO,
  83. BPF_R3_HI,
  84. BPF_R3_LO,
  85. BPF_R4_HI,
  86. BPF_R4_LO,
  87. BPF_R5_HI,
  88. BPF_R5_LO,
  89. BPF_R7_HI,
  90. BPF_R7_LO,
  91. BPF_R8_HI,
  92. BPF_R8_LO,
  93. BPF_R9_HI,
  94. BPF_R9_LO,
  95. BPF_FP_HI,
  96. BPF_FP_LO,
  97. BPF_TC_HI,
  98. BPF_TC_LO,
  99. BPF_AX_HI,
  100. BPF_AX_LO,
  101. /* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4,
  102. * BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9,
  103. * BPF_REG_FP and Tail call counts.
  104. */
  105. BPF_JIT_SCRATCH_REGS,
  106. };
  107. /*
  108. * Negative "register" values indicate the register is stored on the stack
  109. * and are the offset from the top of the eBPF JIT scratch space.
  110. */
  111. #define STACK_OFFSET(k) (-4 - (k) * 4)
  112. #define SCRATCH_SIZE (BPF_JIT_SCRATCH_REGS * 4)
  113. #ifdef CONFIG_FRAME_POINTER
  114. #define EBPF_SCRATCH_TO_ARM_FP(x) ((x) - 4 * hweight16(CALLEE_PUSH_MASK) - 4)
  115. #else
  116. #define EBPF_SCRATCH_TO_ARM_FP(x) (x)
  117. #endif
  118. #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) /* TEMP Register 1 */
  119. #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) /* TEMP Register 2 */
  120. #define TCALL_CNT (MAX_BPF_JIT_REG + 2) /* Tail Call Count */
  121. #define FLAG_IMM_OVERFLOW (1 << 0)
  122. /*
  123. * Map eBPF registers to ARM 32bit registers or stack scratch space.
  124. *
  125. * 1. First argument is passed using the arm 32bit registers and rest of the
  126. * arguments are passed on stack scratch space.
  127. * 2. First callee-saved argument is mapped to arm 32 bit registers and rest
  128. * arguments are mapped to scratch space on stack.
  129. * 3. We need two 64 bit temp registers to do complex operations on eBPF
  130. * registers.
  131. *
  132. * As the eBPF registers are all 64 bit registers and arm has only 32 bit
  133. * registers, we have to map each eBPF registers with two arm 32 bit regs or
  134. * scratch memory space and we have to build eBPF 64 bit register from those.
  135. *
  136. */
  137. static const s8 bpf2a32[][2] = {
  138. /* return value from in-kernel function, and exit value from eBPF */
  139. [BPF_REG_0] = {ARM_R1, ARM_R0},
  140. /* arguments from eBPF program to in-kernel function */
  141. [BPF_REG_1] = {ARM_R3, ARM_R2},
  142. /* Stored on stack scratch space */
  143. [BPF_REG_2] = {STACK_OFFSET(BPF_R2_HI), STACK_OFFSET(BPF_R2_LO)},
  144. [BPF_REG_3] = {STACK_OFFSET(BPF_R3_HI), STACK_OFFSET(BPF_R3_LO)},
  145. [BPF_REG_4] = {STACK_OFFSET(BPF_R4_HI), STACK_OFFSET(BPF_R4_LO)},
  146. [BPF_REG_5] = {STACK_OFFSET(BPF_R5_HI), STACK_OFFSET(BPF_R5_LO)},
  147. /* callee saved registers that in-kernel function will preserve */
  148. [BPF_REG_6] = {ARM_R5, ARM_R4},
  149. /* Stored on stack scratch space */
  150. [BPF_REG_7] = {STACK_OFFSET(BPF_R7_HI), STACK_OFFSET(BPF_R7_LO)},
  151. [BPF_REG_8] = {STACK_OFFSET(BPF_R8_HI), STACK_OFFSET(BPF_R8_LO)},
  152. [BPF_REG_9] = {STACK_OFFSET(BPF_R9_HI), STACK_OFFSET(BPF_R9_LO)},
  153. /* Read only Frame Pointer to access Stack */
  154. [BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)},
  155. /* Temporary Register for BPF JIT, can be used
  156. * for constant blindings and others.
  157. */
  158. [TMP_REG_1] = {ARM_R7, ARM_R6},
  159. [TMP_REG_2] = {ARM_R9, ARM_R8},
  160. /* Tail call count. Stored on stack scratch space. */
  161. [TCALL_CNT] = {STACK_OFFSET(BPF_TC_HI), STACK_OFFSET(BPF_TC_LO)},
  162. /* temporary register for blinding constants.
  163. * Stored on stack scratch space.
  164. */
  165. [BPF_REG_AX] = {STACK_OFFSET(BPF_AX_HI), STACK_OFFSET(BPF_AX_LO)},
  166. };
  167. #define dst_lo dst[1]
  168. #define dst_hi dst[0]
  169. #define src_lo src[1]
  170. #define src_hi src[0]
  171. /*
  172. * JIT Context:
  173. *
  174. * prog : bpf_prog
  175. * idx : index of current last JITed instruction.
  176. * prologue_bytes : bytes used in prologue.
  177. * epilogue_offset : offset of epilogue starting.
  178. * offsets : array of eBPF instruction offsets in
  179. * JITed code.
  180. * target : final JITed code.
  181. * epilogue_bytes : no of bytes used in epilogue.
  182. * imm_count : no of immediate counts used for global
  183. * variables.
  184. * imms : array of global variable addresses.
  185. */
  186. struct jit_ctx {
  187. const struct bpf_prog *prog;
  188. unsigned int idx;
  189. unsigned int prologue_bytes;
  190. unsigned int epilogue_offset;
  191. unsigned int cpu_architecture;
  192. u32 flags;
  193. u32 *offsets;
  194. u32 *target;
  195. u32 stack_size;
  196. #if __LINUX_ARM_ARCH__ < 7
  197. u16 epilogue_bytes;
  198. u16 imm_count;
  199. u32 *imms;
  200. #endif
  201. };
  202. /*
  203. * Wrappers which handle both OABI and EABI and assures Thumb2 interworking
  204. * (where the assembly routines like __aeabi_uidiv could cause problems).
  205. */
  206. static u32 jit_udiv32(u32 dividend, u32 divisor)
  207. {
  208. return dividend / divisor;
  209. }
  210. static u32 jit_mod32(u32 dividend, u32 divisor)
  211. {
  212. return dividend % divisor;
  213. }
  214. static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
  215. {
  216. inst |= (cond << 28);
  217. inst = __opcode_to_mem_arm(inst);
  218. if (ctx->target != NULL)
  219. ctx->target[ctx->idx] = inst;
  220. ctx->idx++;
  221. }
  222. /*
  223. * Emit an instruction that will be executed unconditionally.
  224. */
  225. static inline void emit(u32 inst, struct jit_ctx *ctx)
  226. {
  227. _emit(ARM_COND_AL, inst, ctx);
  228. }
  229. /*
  230. * This is rather horrid, but necessary to convert an integer constant
  231. * to an immediate operand for the opcodes, and be able to detect at
  232. * build time whether the constant can't be converted (iow, usable in
  233. * BUILD_BUG_ON()).
  234. */
  235. #define imm12val(v, s) (rol32(v, (s)) | (s) << 7)
  236. #define const_imm8m(x) \
  237. ({ int r; \
  238. u32 v = (x); \
  239. if (!(v & ~0x000000ff)) \
  240. r = imm12val(v, 0); \
  241. else if (!(v & ~0xc000003f)) \
  242. r = imm12val(v, 2); \
  243. else if (!(v & ~0xf000000f)) \
  244. r = imm12val(v, 4); \
  245. else if (!(v & ~0xfc000003)) \
  246. r = imm12val(v, 6); \
  247. else if (!(v & ~0xff000000)) \
  248. r = imm12val(v, 8); \
  249. else if (!(v & ~0x3fc00000)) \
  250. r = imm12val(v, 10); \
  251. else if (!(v & ~0x0ff00000)) \
  252. r = imm12val(v, 12); \
  253. else if (!(v & ~0x03fc0000)) \
  254. r = imm12val(v, 14); \
  255. else if (!(v & ~0x00ff0000)) \
  256. r = imm12val(v, 16); \
  257. else if (!(v & ~0x003fc000)) \
  258. r = imm12val(v, 18); \
  259. else if (!(v & ~0x000ff000)) \
  260. r = imm12val(v, 20); \
  261. else if (!(v & ~0x0003fc00)) \
  262. r = imm12val(v, 22); \
  263. else if (!(v & ~0x0000ff00)) \
  264. r = imm12val(v, 24); \
  265. else if (!(v & ~0x00003fc0)) \
  266. r = imm12val(v, 26); \
  267. else if (!(v & ~0x00000ff0)) \
  268. r = imm12val(v, 28); \
  269. else if (!(v & ~0x000003fc)) \
  270. r = imm12val(v, 30); \
  271. else \
  272. r = -1; \
  273. r; })
  274. /*
  275. * Checks if immediate value can be converted to imm12(12 bits) value.
  276. */
  277. static int imm8m(u32 x)
  278. {
  279. u32 rot;
  280. for (rot = 0; rot < 16; rot++)
  281. if ((x & ~ror32(0xff, 2 * rot)) == 0)
  282. return rol32(x, 2 * rot) | (rot << 8);
  283. return -1;
  284. }
  285. #define imm8m(x) (__builtin_constant_p(x) ? const_imm8m(x) : imm8m(x))
  286. static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12)
  287. {
  288. op |= rt << 12 | rn << 16;
  289. if (imm12 >= 0)
  290. op |= ARM_INST_LDST__U;
  291. else
  292. imm12 = -imm12;
  293. return op | (imm12 & ARM_INST_LDST__IMM12);
  294. }
  295. static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8)
  296. {
  297. op |= rt << 12 | rn << 16;
  298. if (imm8 >= 0)
  299. op |= ARM_INST_LDST__U;
  300. else
  301. imm8 = -imm8;
  302. return op | (imm8 & 0xf0) << 4 | (imm8 & 0x0f);
  303. }
  304. #define ARM_LDR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off)
  305. #define ARM_LDRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off)
  306. #define ARM_LDRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off)
  307. #define ARM_LDRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off)
  308. #define ARM_STR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off)
  309. #define ARM_STRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off)
  310. #define ARM_STRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRD_I, rt, rn, off)
  311. #define ARM_STRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRH_I, rt, rn, off)
  312. /*
  313. * Initializes the JIT space with undefined instructions.
  314. */
  315. static void jit_fill_hole(void *area, unsigned int size)
  316. {
  317. u32 *ptr;
  318. /* We are guaranteed to have aligned memory. */
  319. for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
  320. *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
  321. }
  322. #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
  323. /* EABI requires the stack to be aligned to 64-bit boundaries */
  324. #define STACK_ALIGNMENT 8
  325. #else
  326. /* Stack must be aligned to 32-bit boundaries */
  327. #define STACK_ALIGNMENT 4
  328. #endif
  329. /* total stack size used in JITed code */
  330. #define _STACK_SIZE (ctx->prog->aux->stack_depth + SCRATCH_SIZE)
  331. #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT)
  332. #if __LINUX_ARM_ARCH__ < 7
  333. static u16 imm_offset(u32 k, struct jit_ctx *ctx)
  334. {
  335. unsigned int i = 0, offset;
  336. u16 imm;
  337. /* on the "fake" run we just count them (duplicates included) */
  338. if (ctx->target == NULL) {
  339. ctx->imm_count++;
  340. return 0;
  341. }
  342. while ((i < ctx->imm_count) && ctx->imms[i]) {
  343. if (ctx->imms[i] == k)
  344. break;
  345. i++;
  346. }
  347. if (ctx->imms[i] == 0)
  348. ctx->imms[i] = k;
  349. /* constants go just after the epilogue */
  350. offset = ctx->offsets[ctx->prog->len - 1] * 4;
  351. offset += ctx->prologue_bytes;
  352. offset += ctx->epilogue_bytes;
  353. offset += i * 4;
  354. ctx->target[offset / 4] = k;
  355. /* PC in ARM mode == address of the instruction + 8 */
  356. imm = offset - (8 + ctx->idx * 4);
  357. if (imm & ~0xfff) {
  358. /*
  359. * literal pool is too far, signal it into flags. we
  360. * can only detect it on the second pass unfortunately.
  361. */
  362. ctx->flags |= FLAG_IMM_OVERFLOW;
  363. return 0;
  364. }
  365. return imm;
  366. }
  367. #endif /* __LINUX_ARM_ARCH__ */
  368. static inline int bpf2a32_offset(int bpf_to, int bpf_from,
  369. const struct jit_ctx *ctx) {
  370. int to, from;
  371. if (ctx->target == NULL)
  372. return 0;
  373. to = ctx->offsets[bpf_to];
  374. from = ctx->offsets[bpf_from];
  375. return to - from - 1;
  376. }
  377. /*
  378. * Move an immediate that's not an imm8m to a core register.
  379. */
  380. static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx)
  381. {
  382. #if __LINUX_ARM_ARCH__ < 7
  383. emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
  384. #else
  385. emit(ARM_MOVW(rd, val & 0xffff), ctx);
  386. if (val > 0xffff)
  387. emit(ARM_MOVT(rd, val >> 16), ctx);
  388. #endif
  389. }
  390. static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx)
  391. {
  392. int imm12 = imm8m(val);
  393. if (imm12 >= 0)
  394. emit(ARM_MOV_I(rd, imm12), ctx);
  395. else
  396. emit_mov_i_no8m(rd, val, ctx);
  397. }
  398. static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx)
  399. {
  400. if (elf_hwcap & HWCAP_THUMB)
  401. emit(ARM_BX(tgt_reg), ctx);
  402. else
  403. emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
  404. }
  405. static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
  406. {
  407. #if __LINUX_ARM_ARCH__ < 5
  408. emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
  409. emit_bx_r(tgt_reg, ctx);
  410. #else
  411. emit(ARM_BLX_R(tgt_reg), ctx);
  412. #endif
  413. }
  414. static inline int epilogue_offset(const struct jit_ctx *ctx)
  415. {
  416. int to, from;
  417. /* No need for 1st dummy run */
  418. if (ctx->target == NULL)
  419. return 0;
  420. to = ctx->epilogue_offset;
  421. from = ctx->idx;
  422. return to - from - 2;
  423. }
  424. static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
  425. {
  426. const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1);
  427. const s8 *tmp = bpf2a32[TMP_REG_1];
  428. #if __LINUX_ARM_ARCH__ == 7
  429. if (elf_hwcap & HWCAP_IDIVA) {
  430. if (op == BPF_DIV)
  431. emit(ARM_UDIV(rd, rm, rn), ctx);
  432. else {
  433. emit(ARM_UDIV(ARM_IP, rm, rn), ctx);
  434. emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx);
  435. }
  436. return;
  437. }
  438. #endif
  439. /*
  440. * For BPF_ALU | BPF_DIV | BPF_K instructions
  441. * As ARM_R1 and ARM_R0 contains 1st argument of bpf
  442. * function, we need to save it on caller side to save
  443. * it from getting destroyed within callee.
  444. * After the return from the callee, we restore ARM_R0
  445. * ARM_R1.
  446. */
  447. if (rn != ARM_R1) {
  448. emit(ARM_MOV_R(tmp[0], ARM_R1), ctx);
  449. emit(ARM_MOV_R(ARM_R1, rn), ctx);
  450. }
  451. if (rm != ARM_R0) {
  452. emit(ARM_MOV_R(tmp[1], ARM_R0), ctx);
  453. emit(ARM_MOV_R(ARM_R0, rm), ctx);
  454. }
  455. /* Push caller-saved registers on stack */
  456. emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx);
  457. /* Call appropriate function */
  458. emit_mov_i(ARM_IP, op == BPF_DIV ?
  459. (u32)jit_udiv32 : (u32)jit_mod32, ctx);
  460. emit_blx_r(ARM_IP, ctx);
  461. /* Restore caller-saved registers from stack */
  462. emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx);
  463. /* Save return value */
  464. if (rd != ARM_R0)
  465. emit(ARM_MOV_R(rd, ARM_R0), ctx);
  466. /* Restore ARM_R0 and ARM_R1 */
  467. if (rn != ARM_R1)
  468. emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx);
  469. if (rm != ARM_R0)
  470. emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx);
  471. }
  472. /* Is the translated BPF register on stack? */
  473. static bool is_stacked(s8 reg)
  474. {
  475. return reg < 0;
  476. }
  477. /* If a BPF register is on the stack (stk is true), load it to the
  478. * supplied temporary register and return the temporary register
  479. * for subsequent operations, otherwise just use the CPU register.
  480. */
  481. static s8 arm_bpf_get_reg32(s8 reg, s8 tmp, struct jit_ctx *ctx)
  482. {
  483. if (is_stacked(reg)) {
  484. emit(ARM_LDR_I(tmp, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
  485. reg = tmp;
  486. }
  487. return reg;
  488. }
  489. static const s8 *arm_bpf_get_reg64(const s8 *reg, const s8 *tmp,
  490. struct jit_ctx *ctx)
  491. {
  492. if (is_stacked(reg[1])) {
  493. if (__LINUX_ARM_ARCH__ >= 6 ||
  494. ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
  495. emit(ARM_LDRD_I(tmp[1], ARM_FP,
  496. EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
  497. } else {
  498. emit(ARM_LDR_I(tmp[1], ARM_FP,
  499. EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
  500. emit(ARM_LDR_I(tmp[0], ARM_FP,
  501. EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
  502. }
  503. reg = tmp;
  504. }
  505. return reg;
  506. }
  507. /* If a BPF register is on the stack (stk is true), save the register
  508. * back to the stack. If the source register is not the same, then
  509. * move it into the correct register.
  510. */
  511. static void arm_bpf_put_reg32(s8 reg, s8 src, struct jit_ctx *ctx)
  512. {
  513. if (is_stacked(reg))
  514. emit(ARM_STR_I(src, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx);
  515. else if (reg != src)
  516. emit(ARM_MOV_R(reg, src), ctx);
  517. }
  518. static void arm_bpf_put_reg64(const s8 *reg, const s8 *src,
  519. struct jit_ctx *ctx)
  520. {
  521. if (is_stacked(reg[1])) {
  522. if (__LINUX_ARM_ARCH__ >= 6 ||
  523. ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) {
  524. emit(ARM_STRD_I(src[1], ARM_FP,
  525. EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
  526. } else {
  527. emit(ARM_STR_I(src[1], ARM_FP,
  528. EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx);
  529. emit(ARM_STR_I(src[0], ARM_FP,
  530. EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx);
  531. }
  532. } else {
  533. if (reg[1] != src[1])
  534. emit(ARM_MOV_R(reg[1], src[1]), ctx);
  535. if (reg[0] != src[0])
  536. emit(ARM_MOV_R(reg[0], src[0]), ctx);
  537. }
  538. }
  539. static inline void emit_a32_mov_i(const s8 dst, const u32 val,
  540. struct jit_ctx *ctx)
  541. {
  542. const s8 *tmp = bpf2a32[TMP_REG_1];
  543. if (is_stacked(dst)) {
  544. emit_mov_i(tmp[1], val, ctx);
  545. arm_bpf_put_reg32(dst, tmp[1], ctx);
  546. } else {
  547. emit_mov_i(dst, val, ctx);
  548. }
  549. }
  550. static void emit_a32_mov_i64(const s8 dst[], u64 val, struct jit_ctx *ctx)
  551. {
  552. const s8 *tmp = bpf2a32[TMP_REG_1];
  553. const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
  554. emit_mov_i(rd[1], (u32)val, ctx);
  555. emit_mov_i(rd[0], val >> 32, ctx);
  556. arm_bpf_put_reg64(dst, rd, ctx);
  557. }
  558. /* Sign extended move */
  559. static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
  560. const u32 val, struct jit_ctx *ctx) {
  561. u64 val64 = val;
  562. if (is64 && (val & (1<<31)))
  563. val64 |= 0xffffffff00000000ULL;
  564. emit_a32_mov_i64(dst, val64, ctx);
  565. }
  566. static inline void emit_a32_add_r(const u8 dst, const u8 src,
  567. const bool is64, const bool hi,
  568. struct jit_ctx *ctx) {
  569. /* 64 bit :
  570. * adds dst_lo, dst_lo, src_lo
  571. * adc dst_hi, dst_hi, src_hi
  572. * 32 bit :
  573. * add dst_lo, dst_lo, src_lo
  574. */
  575. if (!hi && is64)
  576. emit(ARM_ADDS_R(dst, dst, src), ctx);
  577. else if (hi && is64)
  578. emit(ARM_ADC_R(dst, dst, src), ctx);
  579. else
  580. emit(ARM_ADD_R(dst, dst, src), ctx);
  581. }
  582. static inline void emit_a32_sub_r(const u8 dst, const u8 src,
  583. const bool is64, const bool hi,
  584. struct jit_ctx *ctx) {
  585. /* 64 bit :
  586. * subs dst_lo, dst_lo, src_lo
  587. * sbc dst_hi, dst_hi, src_hi
  588. * 32 bit :
  589. * sub dst_lo, dst_lo, src_lo
  590. */
  591. if (!hi && is64)
  592. emit(ARM_SUBS_R(dst, dst, src), ctx);
  593. else if (hi && is64)
  594. emit(ARM_SBC_R(dst, dst, src), ctx);
  595. else
  596. emit(ARM_SUB_R(dst, dst, src), ctx);
  597. }
  598. static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64,
  599. const bool hi, const u8 op, struct jit_ctx *ctx){
  600. switch (BPF_OP(op)) {
  601. /* dst = dst + src */
  602. case BPF_ADD:
  603. emit_a32_add_r(dst, src, is64, hi, ctx);
  604. break;
  605. /* dst = dst - src */
  606. case BPF_SUB:
  607. emit_a32_sub_r(dst, src, is64, hi, ctx);
  608. break;
  609. /* dst = dst | src */
  610. case BPF_OR:
  611. emit(ARM_ORR_R(dst, dst, src), ctx);
  612. break;
  613. /* dst = dst & src */
  614. case BPF_AND:
  615. emit(ARM_AND_R(dst, dst, src), ctx);
  616. break;
  617. /* dst = dst ^ src */
  618. case BPF_XOR:
  619. emit(ARM_EOR_R(dst, dst, src), ctx);
  620. break;
  621. /* dst = dst * src */
  622. case BPF_MUL:
  623. emit(ARM_MUL(dst, dst, src), ctx);
  624. break;
  625. /* dst = dst << src */
  626. case BPF_LSH:
  627. emit(ARM_LSL_R(dst, dst, src), ctx);
  628. break;
  629. /* dst = dst >> src */
  630. case BPF_RSH:
  631. emit(ARM_LSR_R(dst, dst, src), ctx);
  632. break;
  633. /* dst = dst >> src (signed)*/
  634. case BPF_ARSH:
  635. emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx);
  636. break;
  637. }
  638. }
  639. /* ALU operation (64 bit) */
  640. static inline void emit_a32_alu_r64(const bool is64, const s8 dst[],
  641. const s8 src[], struct jit_ctx *ctx,
  642. const u8 op) {
  643. const s8 *tmp = bpf2a32[TMP_REG_1];
  644. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  645. const s8 *rd;
  646. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  647. if (is64) {
  648. const s8 *rs;
  649. rs = arm_bpf_get_reg64(src, tmp2, ctx);
  650. /* ALU operation */
  651. emit_alu_r(rd[1], rs[1], true, false, op, ctx);
  652. emit_alu_r(rd[0], rs[0], true, true, op, ctx);
  653. } else {
  654. s8 rs;
  655. rs = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
  656. /* ALU operation */
  657. emit_alu_r(rd[1], rs, true, false, op, ctx);
  658. if (!ctx->prog->aux->verifier_zext)
  659. emit_a32_mov_i(rd[0], 0, ctx);
  660. }
  661. arm_bpf_put_reg64(dst, rd, ctx);
  662. }
  663. /* dst = src (4 bytes)*/
  664. static inline void emit_a32_mov_r(const s8 dst, const s8 src,
  665. struct jit_ctx *ctx) {
  666. const s8 *tmp = bpf2a32[TMP_REG_1];
  667. s8 rt;
  668. rt = arm_bpf_get_reg32(src, tmp[0], ctx);
  669. arm_bpf_put_reg32(dst, rt, ctx);
  670. }
  671. /* dst = src */
  672. static inline void emit_a32_mov_r64(const bool is64, const s8 dst[],
  673. const s8 src[],
  674. struct jit_ctx *ctx) {
  675. if (!is64) {
  676. emit_a32_mov_r(dst_lo, src_lo, ctx);
  677. if (!ctx->prog->aux->verifier_zext)
  678. /* Zero out high 4 bytes */
  679. emit_a32_mov_i(dst_hi, 0, ctx);
  680. } else if (__LINUX_ARM_ARCH__ < 6 &&
  681. ctx->cpu_architecture < CPU_ARCH_ARMv5TE) {
  682. /* complete 8 byte move */
  683. emit_a32_mov_r(dst_lo, src_lo, ctx);
  684. emit_a32_mov_r(dst_hi, src_hi, ctx);
  685. } else if (is_stacked(src_lo) && is_stacked(dst_lo)) {
  686. const u8 *tmp = bpf2a32[TMP_REG_1];
  687. emit(ARM_LDRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
  688. emit(ARM_STRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
  689. } else if (is_stacked(src_lo)) {
  690. emit(ARM_LDRD_I(dst[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx);
  691. } else if (is_stacked(dst_lo)) {
  692. emit(ARM_STRD_I(src[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx);
  693. } else {
  694. emit(ARM_MOV_R(dst[0], src[0]), ctx);
  695. emit(ARM_MOV_R(dst[1], src[1]), ctx);
  696. }
  697. }
  698. /* Shift operations */
  699. static inline void emit_a32_alu_i(const s8 dst, const u32 val,
  700. struct jit_ctx *ctx, const u8 op) {
  701. const s8 *tmp = bpf2a32[TMP_REG_1];
  702. s8 rd;
  703. rd = arm_bpf_get_reg32(dst, tmp[0], ctx);
  704. /* Do shift operation */
  705. switch (op) {
  706. case BPF_LSH:
  707. emit(ARM_LSL_I(rd, rd, val), ctx);
  708. break;
  709. case BPF_RSH:
  710. emit(ARM_LSR_I(rd, rd, val), ctx);
  711. break;
  712. case BPF_ARSH:
  713. emit(ARM_ASR_I(rd, rd, val), ctx);
  714. break;
  715. case BPF_NEG:
  716. emit(ARM_RSB_I(rd, rd, val), ctx);
  717. break;
  718. }
  719. arm_bpf_put_reg32(dst, rd, ctx);
  720. }
  721. /* dst = ~dst (64 bit) */
  722. static inline void emit_a32_neg64(const s8 dst[],
  723. struct jit_ctx *ctx){
  724. const s8 *tmp = bpf2a32[TMP_REG_1];
  725. const s8 *rd;
  726. /* Setup Operand */
  727. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  728. /* Do Negate Operation */
  729. emit(ARM_RSBS_I(rd[1], rd[1], 0), ctx);
  730. emit(ARM_RSC_I(rd[0], rd[0], 0), ctx);
  731. arm_bpf_put_reg64(dst, rd, ctx);
  732. }
  733. /* dst = dst << src */
  734. static inline void emit_a32_lsh_r64(const s8 dst[], const s8 src[],
  735. struct jit_ctx *ctx) {
  736. const s8 *tmp = bpf2a32[TMP_REG_1];
  737. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  738. const s8 *rd;
  739. s8 rt;
  740. /* Setup Operands */
  741. rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
  742. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  743. /* Do LSH operation */
  744. emit(ARM_SUB_I(ARM_IP, rt, 32), ctx);
  745. emit(ARM_RSB_I(tmp2[0], rt, 32), ctx);
  746. emit(ARM_MOV_SR(ARM_LR, rd[0], SRTYPE_ASL, rt), ctx);
  747. emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[1], SRTYPE_ASL, ARM_IP), ctx);
  748. emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd[1], SRTYPE_LSR, tmp2[0]), ctx);
  749. emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_ASL, rt), ctx);
  750. arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
  751. arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
  752. }
  753. /* dst = dst >> src (signed)*/
  754. static inline void emit_a32_arsh_r64(const s8 dst[], const s8 src[],
  755. struct jit_ctx *ctx) {
  756. const s8 *tmp = bpf2a32[TMP_REG_1];
  757. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  758. const s8 *rd;
  759. s8 rt;
  760. /* Setup Operands */
  761. rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
  762. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  763. /* Do the ARSH operation */
  764. emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
  765. emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
  766. emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
  767. emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
  768. _emit(ARM_COND_PL,
  769. ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx);
  770. emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx);
  771. arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
  772. arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
  773. }
  774. /* dst = dst >> src */
  775. static inline void emit_a32_rsh_r64(const s8 dst[], const s8 src[],
  776. struct jit_ctx *ctx) {
  777. const s8 *tmp = bpf2a32[TMP_REG_1];
  778. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  779. const s8 *rd;
  780. s8 rt;
  781. /* Setup Operands */
  782. rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
  783. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  784. /* Do RSH operation */
  785. emit(ARM_RSB_I(ARM_IP, rt, 32), ctx);
  786. emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx);
  787. emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx);
  788. emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx);
  789. emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_LSR, tmp2[0]), ctx);
  790. emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_LSR, rt), ctx);
  791. arm_bpf_put_reg32(dst_lo, ARM_LR, ctx);
  792. arm_bpf_put_reg32(dst_hi, ARM_IP, ctx);
  793. }
  794. /* dst = dst << val */
  795. static inline void emit_a32_lsh_i64(const s8 dst[],
  796. const u32 val, struct jit_ctx *ctx){
  797. const s8 *tmp = bpf2a32[TMP_REG_1];
  798. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  799. const s8 *rd;
  800. /* Setup operands */
  801. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  802. /* Do LSH operation */
  803. if (val < 32) {
  804. emit(ARM_MOV_SI(tmp2[0], rd[0], SRTYPE_ASL, val), ctx);
  805. emit(ARM_ORR_SI(rd[0], tmp2[0], rd[1], SRTYPE_LSR, 32 - val), ctx);
  806. emit(ARM_MOV_SI(rd[1], rd[1], SRTYPE_ASL, val), ctx);
  807. } else {
  808. if (val == 32)
  809. emit(ARM_MOV_R(rd[0], rd[1]), ctx);
  810. else
  811. emit(ARM_MOV_SI(rd[0], rd[1], SRTYPE_ASL, val - 32), ctx);
  812. emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx);
  813. }
  814. arm_bpf_put_reg64(dst, rd, ctx);
  815. }
  816. /* dst = dst >> val */
  817. static inline void emit_a32_rsh_i64(const s8 dst[],
  818. const u32 val, struct jit_ctx *ctx) {
  819. const s8 *tmp = bpf2a32[TMP_REG_1];
  820. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  821. const s8 *rd;
  822. /* Setup operands */
  823. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  824. /* Do LSR operation */
  825. if (val == 0) {
  826. /* An immediate value of 0 encodes a shift amount of 32
  827. * for LSR. To shift by 0, don't do anything.
  828. */
  829. } else if (val < 32) {
  830. emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
  831. emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
  832. emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx);
  833. } else if (val == 32) {
  834. emit(ARM_MOV_R(rd[1], rd[0]), ctx);
  835. emit(ARM_MOV_I(rd[0], 0), ctx);
  836. } else {
  837. emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_LSR, val - 32), ctx);
  838. emit(ARM_MOV_I(rd[0], 0), ctx);
  839. }
  840. arm_bpf_put_reg64(dst, rd, ctx);
  841. }
  842. /* dst = dst >> val (signed) */
  843. static inline void emit_a32_arsh_i64(const s8 dst[],
  844. const u32 val, struct jit_ctx *ctx){
  845. const s8 *tmp = bpf2a32[TMP_REG_1];
  846. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  847. const s8 *rd;
  848. /* Setup operands */
  849. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  850. /* Do ARSH operation */
  851. if (val == 0) {
  852. /* An immediate value of 0 encodes a shift amount of 32
  853. * for ASR. To shift by 0, don't do anything.
  854. */
  855. } else if (val < 32) {
  856. emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx);
  857. emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx);
  858. emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx);
  859. } else if (val == 32) {
  860. emit(ARM_MOV_R(rd[1], rd[0]), ctx);
  861. emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
  862. } else {
  863. emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_ASR, val - 32), ctx);
  864. emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx);
  865. }
  866. arm_bpf_put_reg64(dst, rd, ctx);
  867. }
  868. static inline void emit_a32_mul_r64(const s8 dst[], const s8 src[],
  869. struct jit_ctx *ctx) {
  870. const s8 *tmp = bpf2a32[TMP_REG_1];
  871. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  872. const s8 *rd, *rt;
  873. /* Setup operands for multiplication */
  874. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  875. rt = arm_bpf_get_reg64(src, tmp2, ctx);
  876. /* Do Multiplication */
  877. emit(ARM_MUL(ARM_IP, rd[1], rt[0]), ctx);
  878. emit(ARM_MUL(ARM_LR, rd[0], rt[1]), ctx);
  879. emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx);
  880. emit(ARM_UMULL(ARM_IP, rd[0], rd[1], rt[1]), ctx);
  881. emit(ARM_ADD_R(rd[0], ARM_LR, rd[0]), ctx);
  882. arm_bpf_put_reg32(dst_lo, ARM_IP, ctx);
  883. arm_bpf_put_reg32(dst_hi, rd[0], ctx);
  884. }
  885. static bool is_ldst_imm(s16 off, const u8 size)
  886. {
  887. s16 off_max = 0;
  888. switch (size) {
  889. case BPF_B:
  890. case BPF_W:
  891. off_max = 0xfff;
  892. break;
  893. case BPF_H:
  894. off_max = 0xff;
  895. break;
  896. case BPF_DW:
  897. /* Need to make sure off+4 does not overflow. */
  898. off_max = 0xfff - 4;
  899. break;
  900. }
  901. return -off_max <= off && off <= off_max;
  902. }
  903. /* *(size *)(dst + off) = src */
  904. static inline void emit_str_r(const s8 dst, const s8 src[],
  905. s16 off, struct jit_ctx *ctx, const u8 sz){
  906. const s8 *tmp = bpf2a32[TMP_REG_1];
  907. s8 rd;
  908. rd = arm_bpf_get_reg32(dst, tmp[1], ctx);
  909. if (!is_ldst_imm(off, sz)) {
  910. emit_a32_mov_i(tmp[0], off, ctx);
  911. emit(ARM_ADD_R(tmp[0], tmp[0], rd), ctx);
  912. rd = tmp[0];
  913. off = 0;
  914. }
  915. switch (sz) {
  916. case BPF_B:
  917. /* Store a Byte */
  918. emit(ARM_STRB_I(src_lo, rd, off), ctx);
  919. break;
  920. case BPF_H:
  921. /* Store a HalfWord */
  922. emit(ARM_STRH_I(src_lo, rd, off), ctx);
  923. break;
  924. case BPF_W:
  925. /* Store a Word */
  926. emit(ARM_STR_I(src_lo, rd, off), ctx);
  927. break;
  928. case BPF_DW:
  929. /* Store a Double Word */
  930. emit(ARM_STR_I(src_lo, rd, off), ctx);
  931. emit(ARM_STR_I(src_hi, rd, off + 4), ctx);
  932. break;
  933. }
  934. }
  935. /* dst = *(size*)(src + off) */
  936. static inline void emit_ldx_r(const s8 dst[], const s8 src,
  937. s16 off, struct jit_ctx *ctx, const u8 sz){
  938. const s8 *tmp = bpf2a32[TMP_REG_1];
  939. const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
  940. s8 rm = src;
  941. if (!is_ldst_imm(off, sz)) {
  942. emit_a32_mov_i(tmp[0], off, ctx);
  943. emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx);
  944. rm = tmp[0];
  945. off = 0;
  946. } else if (rd[1] == rm) {
  947. emit(ARM_MOV_R(tmp[0], rm), ctx);
  948. rm = tmp[0];
  949. }
  950. switch (sz) {
  951. case BPF_B:
  952. /* Load a Byte */
  953. emit(ARM_LDRB_I(rd[1], rm, off), ctx);
  954. if (!ctx->prog->aux->verifier_zext)
  955. emit_a32_mov_i(rd[0], 0, ctx);
  956. break;
  957. case BPF_H:
  958. /* Load a HalfWord */
  959. emit(ARM_LDRH_I(rd[1], rm, off), ctx);
  960. if (!ctx->prog->aux->verifier_zext)
  961. emit_a32_mov_i(rd[0], 0, ctx);
  962. break;
  963. case BPF_W:
  964. /* Load a Word */
  965. emit(ARM_LDR_I(rd[1], rm, off), ctx);
  966. if (!ctx->prog->aux->verifier_zext)
  967. emit_a32_mov_i(rd[0], 0, ctx);
  968. break;
  969. case BPF_DW:
  970. /* Load a Double Word */
  971. emit(ARM_LDR_I(rd[1], rm, off), ctx);
  972. emit(ARM_LDR_I(rd[0], rm, off + 4), ctx);
  973. break;
  974. }
  975. arm_bpf_put_reg64(dst, rd, ctx);
  976. }
  977. /* Arithmatic Operation */
  978. static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm,
  979. const u8 rn, struct jit_ctx *ctx, u8 op,
  980. bool is_jmp64) {
  981. switch (op) {
  982. case BPF_JSET:
  983. if (is_jmp64) {
  984. emit(ARM_AND_R(ARM_IP, rt, rn), ctx);
  985. emit(ARM_AND_R(ARM_LR, rd, rm), ctx);
  986. emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx);
  987. } else {
  988. emit(ARM_ANDS_R(ARM_IP, rt, rn), ctx);
  989. }
  990. break;
  991. case BPF_JEQ:
  992. case BPF_JNE:
  993. case BPF_JGT:
  994. case BPF_JGE:
  995. case BPF_JLE:
  996. case BPF_JLT:
  997. if (is_jmp64) {
  998. emit(ARM_CMP_R(rd, rm), ctx);
  999. /* Only compare low halve if high halve are equal. */
  1000. _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx);
  1001. } else {
  1002. emit(ARM_CMP_R(rt, rn), ctx);
  1003. }
  1004. break;
  1005. case BPF_JSLE:
  1006. case BPF_JSGT:
  1007. emit(ARM_CMP_R(rn, rt), ctx);
  1008. if (is_jmp64)
  1009. emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx);
  1010. break;
  1011. case BPF_JSLT:
  1012. case BPF_JSGE:
  1013. emit(ARM_CMP_R(rt, rn), ctx);
  1014. if (is_jmp64)
  1015. emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx);
  1016. break;
  1017. }
  1018. }
  1019. static int out_offset = -1; /* initialized on the first pass of build_body() */
  1020. static int emit_bpf_tail_call(struct jit_ctx *ctx)
  1021. {
  1022. /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */
  1023. const s8 *r2 = bpf2a32[BPF_REG_2];
  1024. const s8 *r3 = bpf2a32[BPF_REG_3];
  1025. const s8 *tmp = bpf2a32[TMP_REG_1];
  1026. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  1027. const s8 *tcc = bpf2a32[TCALL_CNT];
  1028. const s8 *tc;
  1029. const int idx0 = ctx->idx;
  1030. #define cur_offset (ctx->idx - idx0)
  1031. #define jmp_offset (out_offset - (cur_offset) - 2)
  1032. u32 lo, hi;
  1033. s8 r_array, r_index;
  1034. int off;
  1035. /* if (index >= array->map.max_entries)
  1036. * goto out;
  1037. */
  1038. BUILD_BUG_ON(offsetof(struct bpf_array, map.max_entries) >
  1039. ARM_INST_LDST__IMM12);
  1040. off = offsetof(struct bpf_array, map.max_entries);
  1041. r_array = arm_bpf_get_reg32(r2[1], tmp2[0], ctx);
  1042. /* index is 32-bit for arrays */
  1043. r_index = arm_bpf_get_reg32(r3[1], tmp2[1], ctx);
  1044. /* array->map.max_entries */
  1045. emit(ARM_LDR_I(tmp[1], r_array, off), ctx);
  1046. /* index >= array->map.max_entries */
  1047. emit(ARM_CMP_R(r_index, tmp[1]), ctx);
  1048. _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
  1049. /* tmp2[0] = array, tmp2[1] = index */
  1050. /*
  1051. * if (tail_call_cnt >= MAX_TAIL_CALL_CNT)
  1052. * goto out;
  1053. * tail_call_cnt++;
  1054. */
  1055. lo = (u32)MAX_TAIL_CALL_CNT;
  1056. hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32);
  1057. tc = arm_bpf_get_reg64(tcc, tmp, ctx);
  1058. emit(ARM_CMP_I(tc[0], hi), ctx);
  1059. _emit(ARM_COND_EQ, ARM_CMP_I(tc[1], lo), ctx);
  1060. _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
  1061. emit(ARM_ADDS_I(tc[1], tc[1], 1), ctx);
  1062. emit(ARM_ADC_I(tc[0], tc[0], 0), ctx);
  1063. arm_bpf_put_reg64(tcc, tmp, ctx);
  1064. /* prog = array->ptrs[index]
  1065. * if (prog == NULL)
  1066. * goto out;
  1067. */
  1068. BUILD_BUG_ON(imm8m(offsetof(struct bpf_array, ptrs)) < 0);
  1069. off = imm8m(offsetof(struct bpf_array, ptrs));
  1070. emit(ARM_ADD_I(tmp[1], r_array, off), ctx);
  1071. emit(ARM_LDR_R_SI(tmp[1], tmp[1], r_index, SRTYPE_ASL, 2), ctx);
  1072. emit(ARM_CMP_I(tmp[1], 0), ctx);
  1073. _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
  1074. /* goto *(prog->bpf_func + prologue_size); */
  1075. BUILD_BUG_ON(offsetof(struct bpf_prog, bpf_func) >
  1076. ARM_INST_LDST__IMM12);
  1077. off = offsetof(struct bpf_prog, bpf_func);
  1078. emit(ARM_LDR_I(tmp[1], tmp[1], off), ctx);
  1079. emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx);
  1080. emit_bx_r(tmp[1], ctx);
  1081. /* out: */
  1082. if (out_offset == -1)
  1083. out_offset = cur_offset;
  1084. if (cur_offset != out_offset) {
  1085. pr_err_once("tail_call out_offset = %d, expected %d!\n",
  1086. cur_offset, out_offset);
  1087. return -1;
  1088. }
  1089. return 0;
  1090. #undef cur_offset
  1091. #undef jmp_offset
  1092. }
  1093. /* 0xabcd => 0xcdab */
  1094. static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx)
  1095. {
  1096. #if __LINUX_ARM_ARCH__ < 6
  1097. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  1098. emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
  1099. emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx);
  1100. emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
  1101. emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx);
  1102. #else /* ARMv6+ */
  1103. emit(ARM_REV16(rd, rn), ctx);
  1104. #endif
  1105. }
  1106. /* 0xabcdefgh => 0xghefcdab */
  1107. static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx)
  1108. {
  1109. #if __LINUX_ARM_ARCH__ < 6
  1110. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  1111. emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx);
  1112. emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx);
  1113. emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx);
  1114. emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx);
  1115. emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx);
  1116. emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx);
  1117. emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx);
  1118. emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx);
  1119. emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx);
  1120. emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx);
  1121. #else /* ARMv6+ */
  1122. emit(ARM_REV(rd, rn), ctx);
  1123. #endif
  1124. }
  1125. // push the scratch stack register on top of the stack
  1126. static inline void emit_push_r64(const s8 src[], struct jit_ctx *ctx)
  1127. {
  1128. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  1129. const s8 *rt;
  1130. u16 reg_set = 0;
  1131. rt = arm_bpf_get_reg64(src, tmp2, ctx);
  1132. reg_set = (1 << rt[1]) | (1 << rt[0]);
  1133. emit(ARM_PUSH(reg_set), ctx);
  1134. }
  1135. static void build_prologue(struct jit_ctx *ctx)
  1136. {
  1137. const s8 arm_r0 = bpf2a32[BPF_REG_0][1];
  1138. const s8 *bpf_r1 = bpf2a32[BPF_REG_1];
  1139. const s8 *bpf_fp = bpf2a32[BPF_REG_FP];
  1140. const s8 *tcc = bpf2a32[TCALL_CNT];
  1141. /* Save callee saved registers. */
  1142. #ifdef CONFIG_FRAME_POINTER
  1143. u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC;
  1144. emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
  1145. emit(ARM_PUSH(reg_set), ctx);
  1146. emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
  1147. #else
  1148. emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx);
  1149. emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx);
  1150. #endif
  1151. /* mov r3, #0 */
  1152. /* sub r2, sp, #SCRATCH_SIZE */
  1153. emit(ARM_MOV_I(bpf_r1[0], 0), ctx);
  1154. emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx);
  1155. ctx->stack_size = imm8m(STACK_SIZE);
  1156. /* Set up function call stack */
  1157. emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx);
  1158. /* Set up BPF prog stack base register */
  1159. emit_a32_mov_r64(true, bpf_fp, bpf_r1, ctx);
  1160. /* Initialize Tail Count */
  1161. emit(ARM_MOV_I(bpf_r1[1], 0), ctx);
  1162. emit_a32_mov_r64(true, tcc, bpf_r1, ctx);
  1163. /* Move BPF_CTX to BPF_R1 */
  1164. emit(ARM_MOV_R(bpf_r1[1], arm_r0), ctx);
  1165. /* end of prologue */
  1166. }
  1167. /* restore callee saved registers. */
  1168. static void build_epilogue(struct jit_ctx *ctx)
  1169. {
  1170. #ifdef CONFIG_FRAME_POINTER
  1171. /* When using frame pointers, some additional registers need to
  1172. * be loaded. */
  1173. u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP;
  1174. emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx);
  1175. emit(ARM_LDM(ARM_SP, reg_set), ctx);
  1176. #else
  1177. /* Restore callee saved registers. */
  1178. emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx);
  1179. emit(ARM_POP(CALLEE_POP_MASK), ctx);
  1180. #endif
  1181. }
  1182. /*
  1183. * Convert an eBPF instruction to native instruction, i.e
  1184. * JITs an eBPF instruction.
  1185. * Returns :
  1186. * 0 - Successfully JITed an 8-byte eBPF instruction
  1187. * >0 - Successfully JITed a 16-byte eBPF instruction
  1188. * <0 - Failed to JIT.
  1189. */
  1190. static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx)
  1191. {
  1192. const u8 code = insn->code;
  1193. const s8 *dst = bpf2a32[insn->dst_reg];
  1194. const s8 *src = bpf2a32[insn->src_reg];
  1195. const s8 *tmp = bpf2a32[TMP_REG_1];
  1196. const s8 *tmp2 = bpf2a32[TMP_REG_2];
  1197. const s16 off = insn->off;
  1198. const s32 imm = insn->imm;
  1199. const int i = insn - ctx->prog->insnsi;
  1200. const bool is64 = BPF_CLASS(code) == BPF_ALU64;
  1201. const s8 *rd, *rs;
  1202. s8 rd_lo, rt, rm, rn;
  1203. s32 jmp_offset;
  1204. #define check_imm(bits, imm) do { \
  1205. if ((imm) >= (1 << ((bits) - 1)) || \
  1206. (imm) < -(1 << ((bits) - 1))) { \
  1207. pr_info("[%2d] imm=%d(0x%x) out of range\n", \
  1208. i, imm, imm); \
  1209. return -EINVAL; \
  1210. } \
  1211. } while (0)
  1212. #define check_imm24(imm) check_imm(24, imm)
  1213. switch (code) {
  1214. /* ALU operations */
  1215. /* dst = src */
  1216. case BPF_ALU | BPF_MOV | BPF_K:
  1217. case BPF_ALU | BPF_MOV | BPF_X:
  1218. case BPF_ALU64 | BPF_MOV | BPF_K:
  1219. case BPF_ALU64 | BPF_MOV | BPF_X:
  1220. switch (BPF_SRC(code)) {
  1221. case BPF_X:
  1222. if (imm == 1) {
  1223. /* Special mov32 for zext */
  1224. emit_a32_mov_i(dst_hi, 0, ctx);
  1225. break;
  1226. }
  1227. emit_a32_mov_r64(is64, dst, src, ctx);
  1228. break;
  1229. case BPF_K:
  1230. /* Sign-extend immediate value to destination reg */
  1231. emit_a32_mov_se_i64(is64, dst, imm, ctx);
  1232. break;
  1233. }
  1234. break;
  1235. /* dst = dst + src/imm */
  1236. /* dst = dst - src/imm */
  1237. /* dst = dst | src/imm */
  1238. /* dst = dst & src/imm */
  1239. /* dst = dst ^ src/imm */
  1240. /* dst = dst * src/imm */
  1241. /* dst = dst << src */
  1242. /* dst = dst >> src */
  1243. case BPF_ALU | BPF_ADD | BPF_K:
  1244. case BPF_ALU | BPF_ADD | BPF_X:
  1245. case BPF_ALU | BPF_SUB | BPF_K:
  1246. case BPF_ALU | BPF_SUB | BPF_X:
  1247. case BPF_ALU | BPF_OR | BPF_K:
  1248. case BPF_ALU | BPF_OR | BPF_X:
  1249. case BPF_ALU | BPF_AND | BPF_K:
  1250. case BPF_ALU | BPF_AND | BPF_X:
  1251. case BPF_ALU | BPF_XOR | BPF_K:
  1252. case BPF_ALU | BPF_XOR | BPF_X:
  1253. case BPF_ALU | BPF_MUL | BPF_K:
  1254. case BPF_ALU | BPF_MUL | BPF_X:
  1255. case BPF_ALU | BPF_LSH | BPF_X:
  1256. case BPF_ALU | BPF_RSH | BPF_X:
  1257. case BPF_ALU | BPF_ARSH | BPF_X:
  1258. case BPF_ALU64 | BPF_ADD | BPF_K:
  1259. case BPF_ALU64 | BPF_ADD | BPF_X:
  1260. case BPF_ALU64 | BPF_SUB | BPF_K:
  1261. case BPF_ALU64 | BPF_SUB | BPF_X:
  1262. case BPF_ALU64 | BPF_OR | BPF_K:
  1263. case BPF_ALU64 | BPF_OR | BPF_X:
  1264. case BPF_ALU64 | BPF_AND | BPF_K:
  1265. case BPF_ALU64 | BPF_AND | BPF_X:
  1266. case BPF_ALU64 | BPF_XOR | BPF_K:
  1267. case BPF_ALU64 | BPF_XOR | BPF_X:
  1268. switch (BPF_SRC(code)) {
  1269. case BPF_X:
  1270. emit_a32_alu_r64(is64, dst, src, ctx, BPF_OP(code));
  1271. break;
  1272. case BPF_K:
  1273. /* Move immediate value to the temporary register
  1274. * and then do the ALU operation on the temporary
  1275. * register as this will sign-extend the immediate
  1276. * value into temporary reg and then it would be
  1277. * safe to do the operation on it.
  1278. */
  1279. emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
  1280. emit_a32_alu_r64(is64, dst, tmp2, ctx, BPF_OP(code));
  1281. break;
  1282. }
  1283. break;
  1284. /* dst = dst / src(imm) */
  1285. /* dst = dst % src(imm) */
  1286. case BPF_ALU | BPF_DIV | BPF_K:
  1287. case BPF_ALU | BPF_DIV | BPF_X:
  1288. case BPF_ALU | BPF_MOD | BPF_K:
  1289. case BPF_ALU | BPF_MOD | BPF_X:
  1290. rd_lo = arm_bpf_get_reg32(dst_lo, tmp2[1], ctx);
  1291. switch (BPF_SRC(code)) {
  1292. case BPF_X:
  1293. rt = arm_bpf_get_reg32(src_lo, tmp2[0], ctx);
  1294. break;
  1295. case BPF_K:
  1296. rt = tmp2[0];
  1297. emit_a32_mov_i(rt, imm, ctx);
  1298. break;
  1299. default:
  1300. rt = src_lo;
  1301. break;
  1302. }
  1303. emit_udivmod(rd_lo, rd_lo, rt, ctx, BPF_OP(code));
  1304. arm_bpf_put_reg32(dst_lo, rd_lo, ctx);
  1305. if (!ctx->prog->aux->verifier_zext)
  1306. emit_a32_mov_i(dst_hi, 0, ctx);
  1307. break;
  1308. case BPF_ALU64 | BPF_DIV | BPF_K:
  1309. case BPF_ALU64 | BPF_DIV | BPF_X:
  1310. case BPF_ALU64 | BPF_MOD | BPF_K:
  1311. case BPF_ALU64 | BPF_MOD | BPF_X:
  1312. goto notyet;
  1313. /* dst = dst << imm */
  1314. /* dst = dst >> imm */
  1315. /* dst = dst >> imm (signed) */
  1316. case BPF_ALU | BPF_LSH | BPF_K:
  1317. case BPF_ALU | BPF_RSH | BPF_K:
  1318. case BPF_ALU | BPF_ARSH | BPF_K:
  1319. if (unlikely(imm > 31))
  1320. return -EINVAL;
  1321. if (imm)
  1322. emit_a32_alu_i(dst_lo, imm, ctx, BPF_OP(code));
  1323. if (!ctx->prog->aux->verifier_zext)
  1324. emit_a32_mov_i(dst_hi, 0, ctx);
  1325. break;
  1326. /* dst = dst << imm */
  1327. case BPF_ALU64 | BPF_LSH | BPF_K:
  1328. if (unlikely(imm > 63))
  1329. return -EINVAL;
  1330. emit_a32_lsh_i64(dst, imm, ctx);
  1331. break;
  1332. /* dst = dst >> imm */
  1333. case BPF_ALU64 | BPF_RSH | BPF_K:
  1334. if (unlikely(imm > 63))
  1335. return -EINVAL;
  1336. emit_a32_rsh_i64(dst, imm, ctx);
  1337. break;
  1338. /* dst = dst << src */
  1339. case BPF_ALU64 | BPF_LSH | BPF_X:
  1340. emit_a32_lsh_r64(dst, src, ctx);
  1341. break;
  1342. /* dst = dst >> src */
  1343. case BPF_ALU64 | BPF_RSH | BPF_X:
  1344. emit_a32_rsh_r64(dst, src, ctx);
  1345. break;
  1346. /* dst = dst >> src (signed) */
  1347. case BPF_ALU64 | BPF_ARSH | BPF_X:
  1348. emit_a32_arsh_r64(dst, src, ctx);
  1349. break;
  1350. /* dst = dst >> imm (signed) */
  1351. case BPF_ALU64 | BPF_ARSH | BPF_K:
  1352. if (unlikely(imm > 63))
  1353. return -EINVAL;
  1354. emit_a32_arsh_i64(dst, imm, ctx);
  1355. break;
  1356. /* dst = ~dst */
  1357. case BPF_ALU | BPF_NEG:
  1358. emit_a32_alu_i(dst_lo, 0, ctx, BPF_OP(code));
  1359. if (!ctx->prog->aux->verifier_zext)
  1360. emit_a32_mov_i(dst_hi, 0, ctx);
  1361. break;
  1362. /* dst = ~dst (64 bit) */
  1363. case BPF_ALU64 | BPF_NEG:
  1364. emit_a32_neg64(dst, ctx);
  1365. break;
  1366. /* dst = dst * src/imm */
  1367. case BPF_ALU64 | BPF_MUL | BPF_X:
  1368. case BPF_ALU64 | BPF_MUL | BPF_K:
  1369. switch (BPF_SRC(code)) {
  1370. case BPF_X:
  1371. emit_a32_mul_r64(dst, src, ctx);
  1372. break;
  1373. case BPF_K:
  1374. /* Move immediate value to the temporary register
  1375. * and then do the multiplication on it as this
  1376. * will sign-extend the immediate value into temp
  1377. * reg then it would be safe to do the operation
  1378. * on it.
  1379. */
  1380. emit_a32_mov_se_i64(is64, tmp2, imm, ctx);
  1381. emit_a32_mul_r64(dst, tmp2, ctx);
  1382. break;
  1383. }
  1384. break;
  1385. /* dst = htole(dst) */
  1386. /* dst = htobe(dst) */
  1387. case BPF_ALU | BPF_END | BPF_FROM_LE:
  1388. case BPF_ALU | BPF_END | BPF_FROM_BE:
  1389. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  1390. if (BPF_SRC(code) == BPF_FROM_LE)
  1391. goto emit_bswap_uxt;
  1392. switch (imm) {
  1393. case 16:
  1394. emit_rev16(rd[1], rd[1], ctx);
  1395. goto emit_bswap_uxt;
  1396. case 32:
  1397. emit_rev32(rd[1], rd[1], ctx);
  1398. goto emit_bswap_uxt;
  1399. case 64:
  1400. emit_rev32(ARM_LR, rd[1], ctx);
  1401. emit_rev32(rd[1], rd[0], ctx);
  1402. emit(ARM_MOV_R(rd[0], ARM_LR), ctx);
  1403. break;
  1404. }
  1405. goto exit;
  1406. emit_bswap_uxt:
  1407. switch (imm) {
  1408. case 16:
  1409. /* zero-extend 16 bits into 64 bits */
  1410. #if __LINUX_ARM_ARCH__ < 6
  1411. emit_a32_mov_i(tmp2[1], 0xffff, ctx);
  1412. emit(ARM_AND_R(rd[1], rd[1], tmp2[1]), ctx);
  1413. #else /* ARMv6+ */
  1414. emit(ARM_UXTH(rd[1], rd[1]), ctx);
  1415. #endif
  1416. if (!ctx->prog->aux->verifier_zext)
  1417. emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
  1418. break;
  1419. case 32:
  1420. /* zero-extend 32 bits into 64 bits */
  1421. if (!ctx->prog->aux->verifier_zext)
  1422. emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx);
  1423. break;
  1424. case 64:
  1425. /* nop */
  1426. break;
  1427. }
  1428. exit:
  1429. arm_bpf_put_reg64(dst, rd, ctx);
  1430. break;
  1431. /* dst = imm64 */
  1432. case BPF_LD | BPF_IMM | BPF_DW:
  1433. {
  1434. u64 val = (u32)imm | (u64)insn[1].imm << 32;
  1435. emit_a32_mov_i64(dst, val, ctx);
  1436. return 1;
  1437. }
  1438. /* LDX: dst = *(size *)(src + off) */
  1439. case BPF_LDX | BPF_MEM | BPF_W:
  1440. case BPF_LDX | BPF_MEM | BPF_H:
  1441. case BPF_LDX | BPF_MEM | BPF_B:
  1442. case BPF_LDX | BPF_MEM | BPF_DW:
  1443. rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
  1444. emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code));
  1445. break;
  1446. /* speculation barrier */
  1447. case BPF_ST | BPF_NOSPEC:
  1448. break;
  1449. /* ST: *(size *)(dst + off) = imm */
  1450. case BPF_ST | BPF_MEM | BPF_W:
  1451. case BPF_ST | BPF_MEM | BPF_H:
  1452. case BPF_ST | BPF_MEM | BPF_B:
  1453. case BPF_ST | BPF_MEM | BPF_DW:
  1454. switch (BPF_SIZE(code)) {
  1455. case BPF_DW:
  1456. /* Sign-extend immediate value into temp reg */
  1457. emit_a32_mov_se_i64(true, tmp2, imm, ctx);
  1458. break;
  1459. case BPF_W:
  1460. case BPF_H:
  1461. case BPF_B:
  1462. emit_a32_mov_i(tmp2[1], imm, ctx);
  1463. break;
  1464. }
  1465. emit_str_r(dst_lo, tmp2, off, ctx, BPF_SIZE(code));
  1466. break;
  1467. /* Atomic ops */
  1468. case BPF_STX | BPF_ATOMIC | BPF_W:
  1469. case BPF_STX | BPF_ATOMIC | BPF_DW:
  1470. goto notyet;
  1471. /* STX: *(size *)(dst + off) = src */
  1472. case BPF_STX | BPF_MEM | BPF_W:
  1473. case BPF_STX | BPF_MEM | BPF_H:
  1474. case BPF_STX | BPF_MEM | BPF_B:
  1475. case BPF_STX | BPF_MEM | BPF_DW:
  1476. rs = arm_bpf_get_reg64(src, tmp2, ctx);
  1477. emit_str_r(dst_lo, rs, off, ctx, BPF_SIZE(code));
  1478. break;
  1479. /* PC += off if dst == src */
  1480. /* PC += off if dst > src */
  1481. /* PC += off if dst >= src */
  1482. /* PC += off if dst < src */
  1483. /* PC += off if dst <= src */
  1484. /* PC += off if dst != src */
  1485. /* PC += off if dst > src (signed) */
  1486. /* PC += off if dst >= src (signed) */
  1487. /* PC += off if dst < src (signed) */
  1488. /* PC += off if dst <= src (signed) */
  1489. /* PC += off if dst & src */
  1490. case BPF_JMP | BPF_JEQ | BPF_X:
  1491. case BPF_JMP | BPF_JGT | BPF_X:
  1492. case BPF_JMP | BPF_JGE | BPF_X:
  1493. case BPF_JMP | BPF_JNE | BPF_X:
  1494. case BPF_JMP | BPF_JSGT | BPF_X:
  1495. case BPF_JMP | BPF_JSGE | BPF_X:
  1496. case BPF_JMP | BPF_JSET | BPF_X:
  1497. case BPF_JMP | BPF_JLE | BPF_X:
  1498. case BPF_JMP | BPF_JLT | BPF_X:
  1499. case BPF_JMP | BPF_JSLT | BPF_X:
  1500. case BPF_JMP | BPF_JSLE | BPF_X:
  1501. case BPF_JMP32 | BPF_JEQ | BPF_X:
  1502. case BPF_JMP32 | BPF_JGT | BPF_X:
  1503. case BPF_JMP32 | BPF_JGE | BPF_X:
  1504. case BPF_JMP32 | BPF_JNE | BPF_X:
  1505. case BPF_JMP32 | BPF_JSGT | BPF_X:
  1506. case BPF_JMP32 | BPF_JSGE | BPF_X:
  1507. case BPF_JMP32 | BPF_JSET | BPF_X:
  1508. case BPF_JMP32 | BPF_JLE | BPF_X:
  1509. case BPF_JMP32 | BPF_JLT | BPF_X:
  1510. case BPF_JMP32 | BPF_JSLT | BPF_X:
  1511. case BPF_JMP32 | BPF_JSLE | BPF_X:
  1512. /* Setup source registers */
  1513. rm = arm_bpf_get_reg32(src_hi, tmp2[0], ctx);
  1514. rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx);
  1515. goto go_jmp;
  1516. /* PC += off if dst == imm */
  1517. /* PC += off if dst > imm */
  1518. /* PC += off if dst >= imm */
  1519. /* PC += off if dst < imm */
  1520. /* PC += off if dst <= imm */
  1521. /* PC += off if dst != imm */
  1522. /* PC += off if dst > imm (signed) */
  1523. /* PC += off if dst >= imm (signed) */
  1524. /* PC += off if dst < imm (signed) */
  1525. /* PC += off if dst <= imm (signed) */
  1526. /* PC += off if dst & imm */
  1527. case BPF_JMP | BPF_JEQ | BPF_K:
  1528. case BPF_JMP | BPF_JGT | BPF_K:
  1529. case BPF_JMP | BPF_JGE | BPF_K:
  1530. case BPF_JMP | BPF_JNE | BPF_K:
  1531. case BPF_JMP | BPF_JSGT | BPF_K:
  1532. case BPF_JMP | BPF_JSGE | BPF_K:
  1533. case BPF_JMP | BPF_JSET | BPF_K:
  1534. case BPF_JMP | BPF_JLT | BPF_K:
  1535. case BPF_JMP | BPF_JLE | BPF_K:
  1536. case BPF_JMP | BPF_JSLT | BPF_K:
  1537. case BPF_JMP | BPF_JSLE | BPF_K:
  1538. case BPF_JMP32 | BPF_JEQ | BPF_K:
  1539. case BPF_JMP32 | BPF_JGT | BPF_K:
  1540. case BPF_JMP32 | BPF_JGE | BPF_K:
  1541. case BPF_JMP32 | BPF_JNE | BPF_K:
  1542. case BPF_JMP32 | BPF_JSGT | BPF_K:
  1543. case BPF_JMP32 | BPF_JSGE | BPF_K:
  1544. case BPF_JMP32 | BPF_JSET | BPF_K:
  1545. case BPF_JMP32 | BPF_JLT | BPF_K:
  1546. case BPF_JMP32 | BPF_JLE | BPF_K:
  1547. case BPF_JMP32 | BPF_JSLT | BPF_K:
  1548. case BPF_JMP32 | BPF_JSLE | BPF_K:
  1549. if (off == 0)
  1550. break;
  1551. rm = tmp2[0];
  1552. rn = tmp2[1];
  1553. /* Sign-extend immediate value */
  1554. emit_a32_mov_se_i64(true, tmp2, imm, ctx);
  1555. go_jmp:
  1556. /* Setup destination register */
  1557. rd = arm_bpf_get_reg64(dst, tmp, ctx);
  1558. /* Check for the condition */
  1559. emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code),
  1560. BPF_CLASS(code) == BPF_JMP);
  1561. /* Setup JUMP instruction */
  1562. jmp_offset = bpf2a32_offset(i+off, i, ctx);
  1563. switch (BPF_OP(code)) {
  1564. case BPF_JNE:
  1565. case BPF_JSET:
  1566. _emit(ARM_COND_NE, ARM_B(jmp_offset), ctx);
  1567. break;
  1568. case BPF_JEQ:
  1569. _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx);
  1570. break;
  1571. case BPF_JGT:
  1572. _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx);
  1573. break;
  1574. case BPF_JGE:
  1575. _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx);
  1576. break;
  1577. case BPF_JSGT:
  1578. _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
  1579. break;
  1580. case BPF_JSGE:
  1581. _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
  1582. break;
  1583. case BPF_JLE:
  1584. _emit(ARM_COND_LS, ARM_B(jmp_offset), ctx);
  1585. break;
  1586. case BPF_JLT:
  1587. _emit(ARM_COND_CC, ARM_B(jmp_offset), ctx);
  1588. break;
  1589. case BPF_JSLT:
  1590. _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx);
  1591. break;
  1592. case BPF_JSLE:
  1593. _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx);
  1594. break;
  1595. }
  1596. break;
  1597. /* JMP OFF */
  1598. case BPF_JMP | BPF_JA:
  1599. {
  1600. if (off == 0)
  1601. break;
  1602. jmp_offset = bpf2a32_offset(i+off, i, ctx);
  1603. check_imm24(jmp_offset);
  1604. emit(ARM_B(jmp_offset), ctx);
  1605. break;
  1606. }
  1607. /* tail call */
  1608. case BPF_JMP | BPF_TAIL_CALL:
  1609. if (emit_bpf_tail_call(ctx))
  1610. return -EFAULT;
  1611. break;
  1612. /* function call */
  1613. case BPF_JMP | BPF_CALL:
  1614. {
  1615. const s8 *r0 = bpf2a32[BPF_REG_0];
  1616. const s8 *r1 = bpf2a32[BPF_REG_1];
  1617. const s8 *r2 = bpf2a32[BPF_REG_2];
  1618. const s8 *r3 = bpf2a32[BPF_REG_3];
  1619. const s8 *r4 = bpf2a32[BPF_REG_4];
  1620. const s8 *r5 = bpf2a32[BPF_REG_5];
  1621. const u32 func = (u32)__bpf_call_base + (u32)imm;
  1622. emit_a32_mov_r64(true, r0, r1, ctx);
  1623. emit_a32_mov_r64(true, r1, r2, ctx);
  1624. emit_push_r64(r5, ctx);
  1625. emit_push_r64(r4, ctx);
  1626. emit_push_r64(r3, ctx);
  1627. emit_a32_mov_i(tmp[1], func, ctx);
  1628. emit_blx_r(tmp[1], ctx);
  1629. emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean
  1630. break;
  1631. }
  1632. /* function return */
  1633. case BPF_JMP | BPF_EXIT:
  1634. /* Optimization: when last instruction is EXIT
  1635. * simply fallthrough to epilogue.
  1636. */
  1637. if (i == ctx->prog->len - 1)
  1638. break;
  1639. jmp_offset = epilogue_offset(ctx);
  1640. check_imm24(jmp_offset);
  1641. emit(ARM_B(jmp_offset), ctx);
  1642. break;
  1643. notyet:
  1644. pr_info_once("*** NOT YET: opcode %02x ***\n", code);
  1645. return -EFAULT;
  1646. default:
  1647. pr_err_once("unknown opcode %02x\n", code);
  1648. return -EINVAL;
  1649. }
  1650. if (ctx->flags & FLAG_IMM_OVERFLOW)
  1651. /*
  1652. * this instruction generated an overflow when
  1653. * trying to access the literal pool, so
  1654. * delegate this filter to the kernel interpreter.
  1655. */
  1656. return -1;
  1657. return 0;
  1658. }
  1659. static int build_body(struct jit_ctx *ctx)
  1660. {
  1661. const struct bpf_prog *prog = ctx->prog;
  1662. unsigned int i;
  1663. for (i = 0; i < prog->len; i++) {
  1664. const struct bpf_insn *insn = &(prog->insnsi[i]);
  1665. int ret;
  1666. ret = build_insn(insn, ctx);
  1667. /* It's used with loading the 64 bit immediate value. */
  1668. if (ret > 0) {
  1669. i++;
  1670. if (ctx->target == NULL)
  1671. ctx->offsets[i] = ctx->idx;
  1672. continue;
  1673. }
  1674. if (ctx->target == NULL)
  1675. ctx->offsets[i] = ctx->idx;
  1676. /* If unsuccesful, return with error code */
  1677. if (ret)
  1678. return ret;
  1679. }
  1680. return 0;
  1681. }
  1682. static int validate_code(struct jit_ctx *ctx)
  1683. {
  1684. int i;
  1685. for (i = 0; i < ctx->idx; i++) {
  1686. if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF))
  1687. return -1;
  1688. }
  1689. return 0;
  1690. }
  1691. bool bpf_jit_needs_zext(void)
  1692. {
  1693. return true;
  1694. }
  1695. struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
  1696. {
  1697. struct bpf_prog *tmp, *orig_prog = prog;
  1698. struct bpf_binary_header *header;
  1699. bool tmp_blinded = false;
  1700. struct jit_ctx ctx;
  1701. unsigned int tmp_idx;
  1702. unsigned int image_size;
  1703. u8 *image_ptr;
  1704. /* If BPF JIT was not enabled then we must fall back to
  1705. * the interpreter.
  1706. */
  1707. if (!prog->jit_requested)
  1708. return orig_prog;
  1709. /* If constant blinding was enabled and we failed during blinding
  1710. * then we must fall back to the interpreter. Otherwise, we save
  1711. * the new JITed code.
  1712. */
  1713. tmp = bpf_jit_blind_constants(prog);
  1714. if (IS_ERR(tmp))
  1715. return orig_prog;
  1716. if (tmp != prog) {
  1717. tmp_blinded = true;
  1718. prog = tmp;
  1719. }
  1720. memset(&ctx, 0, sizeof(ctx));
  1721. ctx.prog = prog;
  1722. ctx.cpu_architecture = cpu_architecture();
  1723. /* Not able to allocate memory for offsets[] , then
  1724. * we must fall back to the interpreter
  1725. */
  1726. ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL);
  1727. if (ctx.offsets == NULL) {
  1728. prog = orig_prog;
  1729. goto out;
  1730. }
  1731. /* 1) fake pass to find in the length of the JITed code,
  1732. * to compute ctx->offsets and other context variables
  1733. * needed to compute final JITed code.
  1734. * Also, calculate random starting pointer/start of JITed code
  1735. * which is prefixed by random number of fault instructions.
  1736. *
  1737. * If the first pass fails then there is no chance of it
  1738. * being successful in the second pass, so just fall back
  1739. * to the interpreter.
  1740. */
  1741. if (build_body(&ctx)) {
  1742. prog = orig_prog;
  1743. goto out_off;
  1744. }
  1745. tmp_idx = ctx.idx;
  1746. build_prologue(&ctx);
  1747. ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
  1748. ctx.epilogue_offset = ctx.idx;
  1749. #if __LINUX_ARM_ARCH__ < 7
  1750. tmp_idx = ctx.idx;
  1751. build_epilogue(&ctx);
  1752. ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
  1753. ctx.idx += ctx.imm_count;
  1754. if (ctx.imm_count) {
  1755. ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL);
  1756. if (ctx.imms == NULL) {
  1757. prog = orig_prog;
  1758. goto out_off;
  1759. }
  1760. }
  1761. #else
  1762. /* there's nothing about the epilogue on ARMv7 */
  1763. build_epilogue(&ctx);
  1764. #endif
  1765. /* Now we can get the actual image size of the JITed arm code.
  1766. * Currently, we are not considering the THUMB-2 instructions
  1767. * for jit, although it can decrease the size of the image.
  1768. *
  1769. * As each arm instruction is of length 32bit, we are translating
  1770. * number of JITed instructions into the size required to store these
  1771. * JITed code.
  1772. */
  1773. image_size = sizeof(u32) * ctx.idx;
  1774. /* Now we know the size of the structure to make */
  1775. header = bpf_jit_binary_alloc(image_size, &image_ptr,
  1776. sizeof(u32), jit_fill_hole);
  1777. /* Not able to allocate memory for the structure then
  1778. * we must fall back to the interpretation
  1779. */
  1780. if (header == NULL) {
  1781. prog = orig_prog;
  1782. goto out_imms;
  1783. }
  1784. /* 2.) Actual pass to generate final JIT code */
  1785. ctx.target = (u32 *) image_ptr;
  1786. ctx.idx = 0;
  1787. build_prologue(&ctx);
  1788. /* If building the body of the JITed code fails somehow,
  1789. * we fall back to the interpretation.
  1790. */
  1791. if (build_body(&ctx) < 0) {
  1792. image_ptr = NULL;
  1793. bpf_jit_binary_free(header);
  1794. prog = orig_prog;
  1795. goto out_imms;
  1796. }
  1797. build_epilogue(&ctx);
  1798. /* 3.) Extra pass to validate JITed Code */
  1799. if (validate_code(&ctx)) {
  1800. image_ptr = NULL;
  1801. bpf_jit_binary_free(header);
  1802. prog = orig_prog;
  1803. goto out_imms;
  1804. }
  1805. flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx));
  1806. if (bpf_jit_enable > 1)
  1807. /* there are 2 passes here */
  1808. bpf_jit_dump(prog->len, image_size, 2, ctx.target);
  1809. bpf_jit_binary_lock_ro(header);
  1810. prog->bpf_func = (void *)ctx.target;
  1811. prog->jited = 1;
  1812. prog->jited_len = image_size;
  1813. out_imms:
  1814. #if __LINUX_ARM_ARCH__ < 7
  1815. if (ctx.imm_count)
  1816. kfree(ctx.imms);
  1817. #endif
  1818. out_off:
  1819. kfree(ctx.offsets);
  1820. out:
  1821. if (tmp_blinded)
  1822. bpf_jit_prog_release_other(prog, prog == orig_prog ?
  1823. tmp : orig_prog);
  1824. return prog;
  1825. }