proc-xscale.S 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/mm/proc-xscale.S
  4. *
  5. * Author: Nicolas Pitre
  6. * Created: November 2000
  7. * Copyright: (C) 2000, 2001 MontaVista Software Inc.
  8. *
  9. * MMU functions for the Intel XScale CPUs
  10. *
  11. * 2001 Aug 21:
  12. * some contributions by Brett Gaines <[email protected]>
  13. * Copyright 2001 by Intel Corp.
  14. *
  15. * 2001 Sep 08:
  16. * Completely revisited, many important fixes
  17. * Nicolas Pitre <[email protected]>
  18. */
  19. #include <linux/linkage.h>
  20. #include <linux/init.h>
  21. #include <linux/pgtable.h>
  22. #include <asm/assembler.h>
  23. #include <asm/hwcap.h>
  24. #include <asm/pgtable-hwdef.h>
  25. #include <asm/page.h>
  26. #include <asm/ptrace.h>
  27. #include "proc-macros.S"
  28. /*
  29. * This is the maximum size of an area which will be flushed. If the area
  30. * is larger than this, then we flush the whole cache
  31. */
  32. #define MAX_AREA_SIZE 32768
  33. /*
  34. * the cache line size of the I and D cache
  35. */
  36. #define CACHELINESIZE 32
  37. /*
  38. * the size of the data cache
  39. */
  40. #define CACHESIZE 32768
  41. /*
  42. * Virtual address used to allocate the cache when flushed
  43. *
  44. * This must be an address range which is _never_ used. It should
  45. * apparently have a mapping in the corresponding page table for
  46. * compatibility with future CPUs that _could_ require it. For instance we
  47. * don't care.
  48. *
  49. * This must be aligned on a 2*CACHESIZE boundary. The code selects one of
  50. * the 2 areas in alternance each time the clean_d_cache macro is used.
  51. * Without this the XScale core exhibits cache eviction problems and no one
  52. * knows why.
  53. *
  54. * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
  55. */
  56. #define CLEAN_ADDR 0xfffe0000
  57. /*
  58. * This macro is used to wait for a CP15 write and is needed
  59. * when we have to ensure that the last operation to the co-pro
  60. * was completed before continuing with operation.
  61. */
  62. .macro cpwait, rd
  63. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  64. mov \rd, \rd @ wait for completion
  65. sub pc, pc, #4 @ flush instruction pipeline
  66. .endm
  67. .macro cpwait_ret, lr, rd
  68. mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
  69. sub pc, \lr, \rd, LSR #32 @ wait for completion and
  70. @ flush instruction pipeline
  71. .endm
  72. /*
  73. * This macro cleans the entire dcache using line allocate.
  74. * The main loop has been unrolled to reduce loop overhead.
  75. * rd and rs are two scratch registers.
  76. */
  77. .macro clean_d_cache, rd, rs
  78. ldr \rs, =clean_addr
  79. ldr \rd, [\rs]
  80. eor \rd, \rd, #CACHESIZE
  81. str \rd, [\rs]
  82. add \rs, \rd, #CACHESIZE
  83. 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  84. add \rd, \rd, #CACHELINESIZE
  85. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  86. add \rd, \rd, #CACHELINESIZE
  87. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  88. add \rd, \rd, #CACHELINESIZE
  89. mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
  90. add \rd, \rd, #CACHELINESIZE
  91. teq \rd, \rs
  92. bne 1b
  93. .endm
  94. .data
  95. .align 2
  96. clean_addr: .word CLEAN_ADDR
  97. .text
  98. /*
  99. * cpu_xscale_proc_init()
  100. *
  101. * Nothing too exciting at the moment
  102. */
  103. ENTRY(cpu_xscale_proc_init)
  104. @ enable write buffer coalescing. Some bootloader disable it
  105. mrc p15, 0, r1, c1, c0, 1
  106. bic r1, r1, #1
  107. mcr p15, 0, r1, c1, c0, 1
  108. ret lr
  109. /*
  110. * cpu_xscale_proc_fin()
  111. */
  112. ENTRY(cpu_xscale_proc_fin)
  113. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  114. bic r0, r0, #0x1800 @ ...IZ...........
  115. bic r0, r0, #0x0006 @ .............CA.
  116. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  117. ret lr
  118. /*
  119. * cpu_xscale_reset(loc)
  120. *
  121. * Perform a soft reset of the system. Put the CPU into the
  122. * same state as it would be if it had been reset, and branch
  123. * to what would be the reset vector.
  124. *
  125. * loc: location to jump to for soft reset
  126. *
  127. * Beware PXA270 erratum E7.
  128. */
  129. .align 5
  130. .pushsection .idmap.text, "ax"
  131. ENTRY(cpu_xscale_reset)
  132. mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
  133. msr cpsr_c, r1 @ reset CPSR
  134. mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
  135. mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
  136. mrc p15, 0, r1, c1, c0, 0 @ ctrl register
  137. bic r1, r1, #0x0086 @ ........B....CA.
  138. bic r1, r1, #0x3900 @ ..VIZ..S........
  139. sub pc, pc, #4 @ flush pipeline
  140. @ *** cache line aligned ***
  141. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  142. bic r1, r1, #0x0001 @ ...............M
  143. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
  144. mcr p15, 0, r1, c1, c0, 0 @ ctrl register
  145. @ CAUTION: MMU turned off from this point. We count on the pipeline
  146. @ already containing those two last instructions to survive.
  147. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  148. ret r0
  149. ENDPROC(cpu_xscale_reset)
  150. .popsection
  151. /*
  152. * cpu_xscale_do_idle()
  153. *
  154. * Cause the processor to idle
  155. *
  156. * For now we do nothing but go to idle mode for every case
  157. *
  158. * XScale supports clock switching, but using idle mode support
  159. * allows external hardware to react to system state changes.
  160. */
  161. .align 5
  162. ENTRY(cpu_xscale_do_idle)
  163. mov r0, #1
  164. mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
  165. ret lr
  166. /* ================================= CACHE ================================ */
  167. /*
  168. * flush_icache_all()
  169. *
  170. * Unconditionally clean and invalidate the entire icache.
  171. */
  172. ENTRY(xscale_flush_icache_all)
  173. mov r0, #0
  174. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  175. ret lr
  176. ENDPROC(xscale_flush_icache_all)
  177. /*
  178. * flush_user_cache_all()
  179. *
  180. * Invalidate all cache entries in a particular address
  181. * space.
  182. */
  183. ENTRY(xscale_flush_user_cache_all)
  184. /* FALLTHROUGH */
  185. /*
  186. * flush_kern_cache_all()
  187. *
  188. * Clean and invalidate the entire cache.
  189. */
  190. ENTRY(xscale_flush_kern_cache_all)
  191. mov r2, #VM_EXEC
  192. mov ip, #0
  193. __flush_whole_cache:
  194. clean_d_cache r0, r1
  195. tst r2, #VM_EXEC
  196. mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
  197. mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  198. ret lr
  199. /*
  200. * flush_user_cache_range(start, end, vm_flags)
  201. *
  202. * Invalidate a range of cache entries in the specified
  203. * address space.
  204. *
  205. * - start - start address (may not be aligned)
  206. * - end - end address (exclusive, may not be aligned)
  207. * - vma - vma_area_struct describing address space
  208. */
  209. .align 5
  210. ENTRY(xscale_flush_user_cache_range)
  211. mov ip, #0
  212. sub r3, r1, r0 @ calculate total size
  213. cmp r3, #MAX_AREA_SIZE
  214. bhs __flush_whole_cache
  215. 1: tst r2, #VM_EXEC
  216. mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
  217. mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
  218. mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
  219. add r0, r0, #CACHELINESIZE
  220. cmp r0, r1
  221. blo 1b
  222. tst r2, #VM_EXEC
  223. mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
  224. mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  225. ret lr
  226. /*
  227. * coherent_kern_range(start, end)
  228. *
  229. * Ensure coherency between the Icache and the Dcache in the
  230. * region described by start. If you have non-snooping
  231. * Harvard caches, you need to implement this function.
  232. *
  233. * - start - virtual start address
  234. * - end - virtual end address
  235. *
  236. * Note: single I-cache line invalidation isn't used here since
  237. * it also trashes the mini I-cache used by JTAG debuggers.
  238. */
  239. ENTRY(xscale_coherent_kern_range)
  240. bic r0, r0, #CACHELINESIZE - 1
  241. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  242. add r0, r0, #CACHELINESIZE
  243. cmp r0, r1
  244. blo 1b
  245. mov r0, #0
  246. mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
  247. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  248. ret lr
  249. /*
  250. * coherent_user_range(start, end)
  251. *
  252. * Ensure coherency between the Icache and the Dcache in the
  253. * region described by start. If you have non-snooping
  254. * Harvard caches, you need to implement this function.
  255. *
  256. * - start - virtual start address
  257. * - end - virtual end address
  258. */
  259. ENTRY(xscale_coherent_user_range)
  260. bic r0, r0, #CACHELINESIZE - 1
  261. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  262. mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
  263. add r0, r0, #CACHELINESIZE
  264. cmp r0, r1
  265. blo 1b
  266. mov r0, #0
  267. mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
  268. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  269. ret lr
  270. /*
  271. * flush_kern_dcache_area(void *addr, size_t size)
  272. *
  273. * Ensure no D cache aliasing occurs, either with itself or
  274. * the I cache
  275. *
  276. * - addr - kernel address
  277. * - size - region size
  278. */
  279. ENTRY(xscale_flush_kern_dcache_area)
  280. add r1, r0, r1
  281. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  282. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  283. add r0, r0, #CACHELINESIZE
  284. cmp r0, r1
  285. blo 1b
  286. mov r0, #0
  287. mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
  288. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  289. ret lr
  290. /*
  291. * dma_inv_range(start, end)
  292. *
  293. * Invalidate (discard) the specified virtual address range.
  294. * May not write back any entries. If 'start' or 'end'
  295. * are not cache line aligned, those lines must be written
  296. * back.
  297. *
  298. * - start - virtual start address
  299. * - end - virtual end address
  300. */
  301. xscale_dma_inv_range:
  302. tst r0, #CACHELINESIZE - 1
  303. bic r0, r0, #CACHELINESIZE - 1
  304. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  305. tst r1, #CACHELINESIZE - 1
  306. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  307. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  308. add r0, r0, #CACHELINESIZE
  309. cmp r0, r1
  310. blo 1b
  311. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  312. ret lr
  313. /*
  314. * dma_clean_range(start, end)
  315. *
  316. * Clean the specified virtual address range.
  317. *
  318. * - start - virtual start address
  319. * - end - virtual end address
  320. */
  321. xscale_dma_clean_range:
  322. bic r0, r0, #CACHELINESIZE - 1
  323. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  324. add r0, r0, #CACHELINESIZE
  325. cmp r0, r1
  326. blo 1b
  327. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  328. ret lr
  329. /*
  330. * dma_flush_range(start, end)
  331. *
  332. * Clean and invalidate the specified virtual address range.
  333. *
  334. * - start - virtual start address
  335. * - end - virtual end address
  336. */
  337. ENTRY(xscale_dma_flush_range)
  338. bic r0, r0, #CACHELINESIZE - 1
  339. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  340. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  341. add r0, r0, #CACHELINESIZE
  342. cmp r0, r1
  343. blo 1b
  344. mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
  345. ret lr
  346. /*
  347. * dma_map_area(start, size, dir)
  348. * - start - kernel virtual start address
  349. * - size - size of region
  350. * - dir - DMA direction
  351. */
  352. ENTRY(xscale_dma_map_area)
  353. add r1, r1, r0
  354. cmp r2, #DMA_TO_DEVICE
  355. beq xscale_dma_clean_range
  356. bcs xscale_dma_inv_range
  357. b xscale_dma_flush_range
  358. ENDPROC(xscale_dma_map_area)
  359. /*
  360. * dma_map_area(start, size, dir)
  361. * - start - kernel virtual start address
  362. * - size - size of region
  363. * - dir - DMA direction
  364. */
  365. ENTRY(xscale_80200_A0_A1_dma_map_area)
  366. add r1, r1, r0
  367. teq r2, #DMA_TO_DEVICE
  368. beq xscale_dma_clean_range
  369. b xscale_dma_flush_range
  370. ENDPROC(xscale_80200_A0_A1_dma_map_area)
  371. /*
  372. * dma_unmap_area(start, size, dir)
  373. * - start - kernel virtual start address
  374. * - size - size of region
  375. * - dir - DMA direction
  376. */
  377. ENTRY(xscale_dma_unmap_area)
  378. ret lr
  379. ENDPROC(xscale_dma_unmap_area)
  380. .globl xscale_flush_kern_cache_louis
  381. .equ xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all
  382. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  383. define_cache_functions xscale
  384. /*
  385. * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
  386. * clear the dirty bits, which means that if we invalidate a dirty line,
  387. * the dirty data can still be written back to external memory later on.
  388. *
  389. * The recommended workaround is to always do a clean D-cache line before
  390. * doing an invalidate D-cache line, so on the affected processors,
  391. * dma_inv_range() is implemented as dma_flush_range().
  392. *
  393. * See erratum #25 of "Intel 80200 Processor Specification Update",
  394. * revision January 22, 2003, available at:
  395. * http://www.intel.com/design/iio/specupdt/273415.htm
  396. */
  397. .macro a0_alias basename
  398. .globl xscale_80200_A0_A1_\basename
  399. .type xscale_80200_A0_A1_\basename , %function
  400. .equ xscale_80200_A0_A1_\basename , xscale_\basename
  401. .endm
  402. /*
  403. * Most of the cache functions are unchanged for these processor revisions.
  404. * Export suitable alias symbols for the unchanged functions:
  405. */
  406. a0_alias flush_icache_all
  407. a0_alias flush_user_cache_all
  408. a0_alias flush_kern_cache_all
  409. a0_alias flush_kern_cache_louis
  410. a0_alias flush_user_cache_range
  411. a0_alias coherent_kern_range
  412. a0_alias coherent_user_range
  413. a0_alias flush_kern_dcache_area
  414. a0_alias dma_flush_range
  415. a0_alias dma_unmap_area
  416. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  417. define_cache_functions xscale_80200_A0_A1
  418. ENTRY(cpu_xscale_dcache_clean_area)
  419. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  420. add r0, r0, #CACHELINESIZE
  421. subs r1, r1, #CACHELINESIZE
  422. bhi 1b
  423. ret lr
  424. /* =============================== PageTable ============================== */
  425. /*
  426. * cpu_xscale_switch_mm(pgd)
  427. *
  428. * Set the translation base pointer to be as described by pgd.
  429. *
  430. * pgd: new page tables
  431. */
  432. .align 5
  433. ENTRY(cpu_xscale_switch_mm)
  434. clean_d_cache r1, r2
  435. mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
  436. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  437. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  438. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  439. cpwait_ret lr, ip
  440. /*
  441. * cpu_xscale_set_pte_ext(ptep, pte, ext)
  442. *
  443. * Set a PTE and flush it out
  444. *
  445. * Errata 40: must set memory to write-through for user read-only pages.
  446. */
  447. cpu_xscale_mt_table:
  448. .long 0x00 @ L_PTE_MT_UNCACHED
  449. .long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE
  450. .long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
  451. .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
  452. .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
  453. .long 0x00 @ unused
  454. .long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE
  455. .long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
  456. .long 0x00 @ unused
  457. .long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC
  458. .long 0x00 @ unused
  459. .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
  460. .long 0x00 @ L_PTE_MT_DEV_NONSHARED
  461. .long 0x00 @ unused
  462. .long 0x00 @ unused
  463. .long 0x00 @ unused
  464. .align 5
  465. ENTRY(cpu_xscale_set_pte_ext)
  466. xscale_set_pte_ext_prologue
  467. @
  468. @ Erratum 40: must set memory to write-through for user read-only pages
  469. @
  470. and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2)
  471. teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY
  472. moveq r1, #L_PTE_MT_WRITETHROUGH
  473. and r1, r1, #L_PTE_MT_MASK
  474. adr ip, cpu_xscale_mt_table
  475. ldr ip, [ip, r1]
  476. bic r2, r2, #0x0c
  477. orr r2, r2, ip
  478. xscale_set_pte_ext_epilogue
  479. ret lr
  480. .ltorg
  481. .align
  482. .globl cpu_xscale_suspend_size
  483. .equ cpu_xscale_suspend_size, 4 * 6
  484. #ifdef CONFIG_ARM_CPU_SUSPEND
  485. ENTRY(cpu_xscale_do_suspend)
  486. stmfd sp!, {r4 - r9, lr}
  487. mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
  488. mrc p15, 0, r5, c15, c1, 0 @ CP access reg
  489. mrc p15, 0, r6, c13, c0, 0 @ PID
  490. mrc p15, 0, r7, c3, c0, 0 @ domain ID
  491. mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
  492. mrc p15, 0, r9, c1, c0, 0 @ control reg
  493. bic r4, r4, #2 @ clear frequency change bit
  494. stmia r0, {r4 - r9} @ store cp regs
  495. ldmfd sp!, {r4 - r9, pc}
  496. ENDPROC(cpu_xscale_do_suspend)
  497. ENTRY(cpu_xscale_do_resume)
  498. ldmia r0, {r4 - r9} @ load cp regs
  499. mov ip, #0
  500. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  501. mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
  502. mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
  503. mcr p15, 0, r5, c15, c1, 0 @ CP access reg
  504. mcr p15, 0, r6, c13, c0, 0 @ PID
  505. mcr p15, 0, r7, c3, c0, 0 @ domain ID
  506. mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
  507. mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
  508. mov r0, r9 @ control register
  509. b cpu_resume_mmu
  510. ENDPROC(cpu_xscale_do_resume)
  511. #endif
  512. .type __xscale_setup, #function
  513. __xscale_setup:
  514. mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
  515. mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
  516. mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
  517. mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde
  518. orr r0, r0, #1 << 13 @ Its undefined whether this
  519. mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
  520. adr r5, xscale_crval
  521. ldmia r5, {r5, r6}
  522. mrc p15, 0, r0, c1, c0, 0 @ get control register
  523. bic r0, r0, r5
  524. orr r0, r0, r6
  525. ret lr
  526. .size __xscale_setup, . - __xscale_setup
  527. /*
  528. * R
  529. * .RVI ZFRS BLDP WCAM
  530. * ..11 1.01 .... .101
  531. *
  532. */
  533. .type xscale_crval, #object
  534. xscale_crval:
  535. crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
  536. __INITDATA
  537. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  538. define_processor_functions xscale, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1
  539. .section ".rodata"
  540. string cpu_arch_name, "armv5te"
  541. string cpu_elf_name, "v5"
  542. string cpu_80200_A0_A1_name, "XScale-80200 A0/A1"
  543. string cpu_80200_name, "XScale-80200"
  544. string cpu_80219_name, "XScale-80219"
  545. string cpu_8032x_name, "XScale-IOP8032x Family"
  546. string cpu_8033x_name, "XScale-IOP8033x Family"
  547. string cpu_pxa250_name, "XScale-PXA250"
  548. string cpu_pxa210_name, "XScale-PXA210"
  549. string cpu_ixp42x_name, "XScale-IXP42x Family"
  550. string cpu_ixp43x_name, "XScale-IXP43x Family"
  551. string cpu_ixp46x_name, "XScale-IXP46x Family"
  552. string cpu_ixp2400_name, "XScale-IXP2400"
  553. string cpu_ixp2800_name, "XScale-IXP2800"
  554. string cpu_pxa255_name, "XScale-PXA255"
  555. string cpu_pxa270_name, "XScale-PXA270"
  556. .align
  557. .section ".proc.info.init", "a"
  558. .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
  559. .type __\name\()_proc_info,#object
  560. __\name\()_proc_info:
  561. .long \cpu_val
  562. .long \cpu_mask
  563. .long PMD_TYPE_SECT | \
  564. PMD_SECT_BUFFERABLE | \
  565. PMD_SECT_CACHEABLE | \
  566. PMD_SECT_AP_WRITE | \
  567. PMD_SECT_AP_READ
  568. .long PMD_TYPE_SECT | \
  569. PMD_SECT_AP_WRITE | \
  570. PMD_SECT_AP_READ
  571. initfn __xscale_setup, __\name\()_proc_info
  572. .long cpu_arch_name
  573. .long cpu_elf_name
  574. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  575. .long \cpu_name
  576. .long xscale_processor_functions
  577. .long v4wbi_tlb_fns
  578. .long xscale_mc_user_fns
  579. .ifb \cache
  580. .long xscale_cache_fns
  581. .else
  582. .long \cache
  583. .endif
  584. .size __\name\()_proc_info, . - __\name\()_proc_info
  585. .endm
  586. xscale_proc_info 80200_A0_A1, 0x69052000, 0xfffffffe, cpu_80200_name, \
  587. cache=xscale_80200_A0_A1_cache_fns
  588. xscale_proc_info 80200, 0x69052000, 0xfffffff0, cpu_80200_name
  589. xscale_proc_info 80219, 0x69052e20, 0xffffffe0, cpu_80219_name
  590. xscale_proc_info 8032x, 0x69052420, 0xfffff7e0, cpu_8032x_name
  591. xscale_proc_info 8033x, 0x69054010, 0xfffffd30, cpu_8033x_name
  592. xscale_proc_info pxa250, 0x69052100, 0xfffff7f0, cpu_pxa250_name
  593. xscale_proc_info pxa210, 0x69052120, 0xfffff3f0, cpu_pxa210_name
  594. xscale_proc_info ixp2400, 0x69054190, 0xfffffff0, cpu_ixp2400_name
  595. xscale_proc_info ixp2800, 0x690541a0, 0xfffffff0, cpu_ixp2800_name
  596. xscale_proc_info ixp42x, 0x690541c0, 0xffffffc0, cpu_ixp42x_name
  597. xscale_proc_info ixp43x, 0x69054040, 0xfffffff0, cpu_ixp43x_name
  598. xscale_proc_info ixp46x, 0x69054200, 0xffffff00, cpu_ixp46x_name
  599. xscale_proc_info pxa255, 0x69052d00, 0xfffffff0, cpu_pxa255_name
  600. xscale_proc_info pxa270, 0x69054110, 0xfffffff0, cpu_pxa270_name