proc-sa1100.S 6.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/mm/proc-sa1100.S
  4. *
  5. * Copyright (C) 1997-2002 Russell King
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * MMU functions for SA110
  9. *
  10. * These are the low level assembler for performing cache and TLB
  11. * functions on the StrongARM-1100 and StrongARM-1110.
  12. *
  13. * Note that SA1100 and SA1110 share everything but their name and CPU ID.
  14. *
  15. * 12-jun-2000, Erik Mouw ([email protected]):
  16. * Flush the read buffer at context switches
  17. */
  18. #include <linux/linkage.h>
  19. #include <linux/init.h>
  20. #include <linux/pgtable.h>
  21. #include <asm/assembler.h>
  22. #include <asm/asm-offsets.h>
  23. #include <asm/hwcap.h>
  24. #include <mach/hardware.h>
  25. #include <asm/pgtable-hwdef.h>
  26. #include "proc-macros.S"
  27. /*
  28. * the cache line size of the I and D cache
  29. */
  30. #define DCACHELINESIZE 32
  31. .section .text
  32. /*
  33. * cpu_sa1100_proc_init()
  34. */
  35. ENTRY(cpu_sa1100_proc_init)
  36. mov r0, #0
  37. mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
  38. mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
  39. ret lr
  40. /*
  41. * cpu_sa1100_proc_fin()
  42. *
  43. * Prepare the CPU for reset:
  44. * - Disable interrupts
  45. * - Clean and turn off caches.
  46. */
  47. ENTRY(cpu_sa1100_proc_fin)
  48. mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
  49. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  50. bic r0, r0, #0x1000 @ ...i............
  51. bic r0, r0, #0x000e @ ............wca.
  52. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  53. ret lr
  54. /*
  55. * cpu_sa1100_reset(loc)
  56. *
  57. * Perform a soft reset of the system. Put the CPU into the
  58. * same state as it would be if it had been reset, and branch
  59. * to what would be the reset vector.
  60. *
  61. * loc: location to jump to for soft reset
  62. */
  63. .align 5
  64. .pushsection .idmap.text, "ax"
  65. ENTRY(cpu_sa1100_reset)
  66. mov ip, #0
  67. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  68. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  69. #ifdef CONFIG_MMU
  70. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  71. #endif
  72. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  73. bic ip, ip, #0x000f @ ............wcam
  74. bic ip, ip, #0x1100 @ ...i...s........
  75. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  76. ret r0
  77. ENDPROC(cpu_sa1100_reset)
  78. .popsection
  79. /*
  80. * cpu_sa1100_do_idle(type)
  81. *
  82. * Cause the processor to idle
  83. *
  84. * type: call type:
  85. * 0 = slow idle
  86. * 1 = fast idle
  87. * 2 = switch to slow processor clock
  88. * 3 = switch to fast processor clock
  89. */
  90. .align 5
  91. ENTRY(cpu_sa1100_do_idle)
  92. mov r0, r0 @ 4 nop padding
  93. mov r0, r0
  94. mov r0, r0
  95. mov r0, r0 @ 4 nop padding
  96. mov r0, r0
  97. mov r0, r0
  98. mov r0, #0
  99. ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
  100. @ --- aligned to a cache line
  101. mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
  102. ldr r1, [r1, #0] @ force switch to MCLK
  103. mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
  104. mov r0, r0 @ safety
  105. mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
  106. ret lr
  107. /* ================================= CACHE ================================ */
  108. /*
  109. * cpu_sa1100_dcache_clean_area(addr,sz)
  110. *
  111. * Clean the specified entry of any caches such that the MMU
  112. * translation fetches will obtain correct data.
  113. *
  114. * addr: cache-unaligned virtual address
  115. */
  116. .align 5
  117. ENTRY(cpu_sa1100_dcache_clean_area)
  118. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  119. add r0, r0, #DCACHELINESIZE
  120. subs r1, r1, #DCACHELINESIZE
  121. bhi 1b
  122. ret lr
  123. /* =============================== PageTable ============================== */
  124. /*
  125. * cpu_sa1100_switch_mm(pgd)
  126. *
  127. * Set the translation base pointer to be as described by pgd.
  128. *
  129. * pgd: new page tables
  130. */
  131. .align 5
  132. ENTRY(cpu_sa1100_switch_mm)
  133. #ifdef CONFIG_MMU
  134. str lr, [sp, #-4]!
  135. bl v4wb_flush_kern_cache_all @ clears IP
  136. mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
  137. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  138. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  139. ldr pc, [sp], #4
  140. #else
  141. ret lr
  142. #endif
  143. /*
  144. * cpu_sa1100_set_pte_ext(ptep, pte, ext)
  145. *
  146. * Set a PTE and flush it out
  147. */
  148. .align 5
  149. ENTRY(cpu_sa1100_set_pte_ext)
  150. #ifdef CONFIG_MMU
  151. armv3_set_pte_ext wc_disable=0
  152. mov r0, r0
  153. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  154. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  155. #endif
  156. ret lr
  157. .globl cpu_sa1100_suspend_size
  158. .equ cpu_sa1100_suspend_size, 4 * 3
  159. #ifdef CONFIG_ARM_CPU_SUSPEND
  160. ENTRY(cpu_sa1100_do_suspend)
  161. stmfd sp!, {r4 - r6, lr}
  162. mrc p15, 0, r4, c3, c0, 0 @ domain ID
  163. mrc p15, 0, r5, c13, c0, 0 @ PID
  164. mrc p15, 0, r6, c1, c0, 0 @ control reg
  165. stmia r0, {r4 - r6} @ store cp regs
  166. ldmfd sp!, {r4 - r6, pc}
  167. ENDPROC(cpu_sa1100_do_suspend)
  168. ENTRY(cpu_sa1100_do_resume)
  169. ldmia r0, {r4 - r6} @ load cp regs
  170. mov ip, #0
  171. mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
  172. mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
  173. mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
  174. mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
  175. mcr p15, 0, r4, c3, c0, 0 @ domain ID
  176. mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
  177. mcr p15, 0, r5, c13, c0, 0 @ PID
  178. mov r0, r6 @ control register
  179. b cpu_resume_mmu
  180. ENDPROC(cpu_sa1100_do_resume)
  181. #endif
  182. .type __sa1100_setup, #function
  183. __sa1100_setup:
  184. mov r0, #0
  185. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  186. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  187. #ifdef CONFIG_MMU
  188. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  189. #endif
  190. adr r5, sa1100_crval
  191. ldmia r5, {r5, r6}
  192. mrc p15, 0, r0, c1, c0 @ get control register v4
  193. bic r0, r0, r5
  194. orr r0, r0, r6
  195. ret lr
  196. .size __sa1100_setup, . - __sa1100_setup
  197. /*
  198. * R
  199. * .RVI ZFRS BLDP WCAM
  200. * ..11 0001 ..11 1101
  201. *
  202. */
  203. .type sa1100_crval, #object
  204. sa1100_crval:
  205. crval clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
  206. __INITDATA
  207. /*
  208. * SA1100 and SA1110 share the same function calls
  209. */
  210. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  211. define_processor_functions sa1100, dabort=v4_early_abort, pabort=legacy_pabort, suspend=1
  212. .section ".rodata"
  213. string cpu_arch_name, "armv4"
  214. string cpu_elf_name, "v4"
  215. string cpu_sa1100_name, "StrongARM-1100"
  216. string cpu_sa1110_name, "StrongARM-1110"
  217. .align
  218. .section ".proc.info.init", "a"
  219. .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req
  220. .type __\name\()_proc_info,#object
  221. __\name\()_proc_info:
  222. .long \cpu_val
  223. .long \cpu_mask
  224. .long PMD_TYPE_SECT | \
  225. PMD_SECT_BUFFERABLE | \
  226. PMD_SECT_CACHEABLE | \
  227. PMD_SECT_AP_WRITE | \
  228. PMD_SECT_AP_READ
  229. .long PMD_TYPE_SECT | \
  230. PMD_SECT_AP_WRITE | \
  231. PMD_SECT_AP_READ
  232. initfn __sa1100_setup, __\name\()_proc_info
  233. .long cpu_arch_name
  234. .long cpu_elf_name
  235. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
  236. .long \cpu_name
  237. .long sa1100_processor_functions
  238. .long v4wb_tlb_fns
  239. .long v4_mc_user_fns
  240. .long v4wb_cache_fns
  241. .size __\name\()_proc_info, . - __\name\()_proc_info
  242. .endm
  243. sa1100_proc_info sa1100, 0x4401a110, 0xfffffff0, cpu_sa1100_name
  244. sa1100_proc_info sa1110, 0x6901b110, 0xfffffff0, cpu_sa1110_name