proc-sa110.S 5.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/mm/proc-sa110.S
  4. *
  5. * Copyright (C) 1997-2002 Russell King
  6. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  7. *
  8. * MMU functions for SA110
  9. *
  10. * These are the low level assembler for performing cache and TLB
  11. * functions on the StrongARM-110.
  12. */
  13. #include <linux/linkage.h>
  14. #include <linux/init.h>
  15. #include <linux/pgtable.h>
  16. #include <asm/assembler.h>
  17. #include <asm/asm-offsets.h>
  18. #include <asm/hwcap.h>
  19. #include <mach/hardware.h>
  20. #include <asm/pgtable-hwdef.h>
  21. #include <asm/ptrace.h>
  22. #include "proc-macros.S"
  23. /*
  24. * the cache line size of the I and D cache
  25. */
  26. #define DCACHELINESIZE 32
  27. .text
  28. /*
  29. * cpu_sa110_proc_init()
  30. */
  31. ENTRY(cpu_sa110_proc_init)
  32. mov r0, #0
  33. mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
  34. ret lr
  35. /*
  36. * cpu_sa110_proc_fin()
  37. */
  38. ENTRY(cpu_sa110_proc_fin)
  39. mov r0, #0
  40. mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
  41. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  42. bic r0, r0, #0x1000 @ ...i............
  43. bic r0, r0, #0x000e @ ............wca.
  44. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  45. ret lr
  46. /*
  47. * cpu_sa110_reset(loc)
  48. *
  49. * Perform a soft reset of the system. Put the CPU into the
  50. * same state as it would be if it had been reset, and branch
  51. * to what would be the reset vector.
  52. *
  53. * loc: location to jump to for soft reset
  54. */
  55. .align 5
  56. .pushsection .idmap.text, "ax"
  57. ENTRY(cpu_sa110_reset)
  58. mov ip, #0
  59. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  60. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  61. #ifdef CONFIG_MMU
  62. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  63. #endif
  64. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  65. bic ip, ip, #0x000f @ ............wcam
  66. bic ip, ip, #0x1100 @ ...i...s........
  67. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  68. ret r0
  69. ENDPROC(cpu_sa110_reset)
  70. .popsection
  71. /*
  72. * cpu_sa110_do_idle(type)
  73. *
  74. * Cause the processor to idle
  75. *
  76. * type: call type:
  77. * 0 = slow idle
  78. * 1 = fast idle
  79. * 2 = switch to slow processor clock
  80. * 3 = switch to fast processor clock
  81. */
  82. .align 5
  83. ENTRY(cpu_sa110_do_idle)
  84. mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
  85. ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
  86. ldr r1, [r1, #0] @ force switch to MCLK
  87. mov r0, r0 @ safety
  88. mov r0, r0 @ safety
  89. mov r0, r0 @ safety
  90. mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
  91. mov r0, r0 @ safety
  92. mov r0, r0 @ safety
  93. mov r0, r0 @ safety
  94. mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
  95. ret lr
  96. /* ================================= CACHE ================================ */
  97. /*
  98. * cpu_sa110_dcache_clean_area(addr,sz)
  99. *
  100. * Clean the specified entry of any caches such that the MMU
  101. * translation fetches will obtain correct data.
  102. *
  103. * addr: cache-unaligned virtual address
  104. */
  105. .align 5
  106. ENTRY(cpu_sa110_dcache_clean_area)
  107. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  108. add r0, r0, #DCACHELINESIZE
  109. subs r1, r1, #DCACHELINESIZE
  110. bhi 1b
  111. ret lr
  112. /* =============================== PageTable ============================== */
  113. /*
  114. * cpu_sa110_switch_mm(pgd)
  115. *
  116. * Set the translation base pointer to be as described by pgd.
  117. *
  118. * pgd: new page tables
  119. */
  120. .align 5
  121. ENTRY(cpu_sa110_switch_mm)
  122. #ifdef CONFIG_MMU
  123. str lr, [sp, #-4]!
  124. bl v4wb_flush_kern_cache_all @ clears IP
  125. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  126. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  127. ldr pc, [sp], #4
  128. #else
  129. ret lr
  130. #endif
  131. /*
  132. * cpu_sa110_set_pte_ext(ptep, pte, ext)
  133. *
  134. * Set a PTE and flush it out
  135. */
  136. .align 5
  137. ENTRY(cpu_sa110_set_pte_ext)
  138. #ifdef CONFIG_MMU
  139. armv3_set_pte_ext wc_disable=0
  140. mov r0, r0
  141. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  142. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  143. #endif
  144. ret lr
  145. .type __sa110_setup, #function
  146. __sa110_setup:
  147. mov r10, #0
  148. mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
  149. mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
  150. #ifdef CONFIG_MMU
  151. mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
  152. #endif
  153. adr r5, sa110_crval
  154. ldmia r5, {r5, r6}
  155. mrc p15, 0, r0, c1, c0 @ get control register v4
  156. bic r0, r0, r5
  157. orr r0, r0, r6
  158. ret lr
  159. .size __sa110_setup, . - __sa110_setup
  160. /*
  161. * R
  162. * .RVI ZFRS BLDP WCAM
  163. * ..01 0001 ..11 1101
  164. *
  165. */
  166. .type sa110_crval, #object
  167. sa110_crval:
  168. crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
  169. __INITDATA
  170. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  171. define_processor_functions sa110, dabort=v4_early_abort, pabort=legacy_pabort
  172. .section ".rodata"
  173. string cpu_arch_name, "armv4"
  174. string cpu_elf_name, "v4"
  175. string cpu_sa110_name, "StrongARM-110"
  176. .align
  177. .section ".proc.info.init", "a"
  178. .type __sa110_proc_info,#object
  179. __sa110_proc_info:
  180. .long 0x4401a100
  181. .long 0xfffffff0
  182. .long PMD_TYPE_SECT | \
  183. PMD_SECT_BUFFERABLE | \
  184. PMD_SECT_CACHEABLE | \
  185. PMD_SECT_AP_WRITE | \
  186. PMD_SECT_AP_READ
  187. .long PMD_TYPE_SECT | \
  188. PMD_SECT_AP_WRITE | \
  189. PMD_SECT_AP_READ
  190. initfn __sa110_setup, __sa110_proc_info
  191. .long cpu_arch_name
  192. .long cpu_elf_name
  193. .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
  194. .long cpu_sa110_name
  195. .long sa110_processor_functions
  196. .long v4wb_tlb_fns
  197. .long v4wb_user_fns
  198. .long v4wb_cache_fns
  199. .size __sa110_proc_info, . - __sa110_proc_info