proc-mohawk.S 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core
  4. *
  5. * PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core.
  6. *
  7. * Heavily based on proc-arm926.S and proc-xsc3.S
  8. */
  9. #include <linux/linkage.h>
  10. #include <linux/init.h>
  11. #include <linux/pgtable.h>
  12. #include <asm/assembler.h>
  13. #include <asm/hwcap.h>
  14. #include <asm/pgtable-hwdef.h>
  15. #include <asm/page.h>
  16. #include <asm/ptrace.h>
  17. #include "proc-macros.S"
  18. /*
  19. * This is the maximum size of an area which will be flushed. If the
  20. * area is larger than this, then we flush the whole cache.
  21. */
  22. #define CACHE_DLIMIT 32768
  23. /*
  24. * The cache line size of the L1 D cache.
  25. */
  26. #define CACHE_DLINESIZE 32
  27. /*
  28. * cpu_mohawk_proc_init()
  29. */
  30. ENTRY(cpu_mohawk_proc_init)
  31. ret lr
  32. /*
  33. * cpu_mohawk_proc_fin()
  34. */
  35. ENTRY(cpu_mohawk_proc_fin)
  36. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  37. bic r0, r0, #0x1800 @ ...iz...........
  38. bic r0, r0, #0x0006 @ .............ca.
  39. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  40. ret lr
  41. /*
  42. * cpu_mohawk_reset(loc)
  43. *
  44. * Perform a soft reset of the system. Put the CPU into the
  45. * same state as it would be if it had been reset, and branch
  46. * to what would be the reset vector.
  47. *
  48. * loc: location to jump to for soft reset
  49. *
  50. * (same as arm926)
  51. */
  52. .align 5
  53. .pushsection .idmap.text, "ax"
  54. ENTRY(cpu_mohawk_reset)
  55. mov ip, #0
  56. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  57. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  58. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  59. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  60. bic ip, ip, #0x0007 @ .............cam
  61. bic ip, ip, #0x1100 @ ...i...s........
  62. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  63. ret r0
  64. ENDPROC(cpu_mohawk_reset)
  65. .popsection
  66. /*
  67. * cpu_mohawk_do_idle()
  68. *
  69. * Called with IRQs disabled
  70. */
  71. .align 5
  72. ENTRY(cpu_mohawk_do_idle)
  73. mov r0, #0
  74. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  75. mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
  76. ret lr
  77. /*
  78. * flush_icache_all()
  79. *
  80. * Unconditionally clean and invalidate the entire icache.
  81. */
  82. ENTRY(mohawk_flush_icache_all)
  83. mov r0, #0
  84. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  85. ret lr
  86. ENDPROC(mohawk_flush_icache_all)
  87. /*
  88. * flush_user_cache_all()
  89. *
  90. * Clean and invalidate all cache entries in a particular
  91. * address space.
  92. */
  93. ENTRY(mohawk_flush_user_cache_all)
  94. /* FALLTHROUGH */
  95. /*
  96. * flush_kern_cache_all()
  97. *
  98. * Clean and invalidate the entire cache.
  99. */
  100. ENTRY(mohawk_flush_kern_cache_all)
  101. mov r2, #VM_EXEC
  102. mov ip, #0
  103. __flush_whole_cache:
  104. mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
  105. tst r2, #VM_EXEC
  106. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  107. mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
  108. ret lr
  109. /*
  110. * flush_user_cache_range(start, end, flags)
  111. *
  112. * Clean and invalidate a range of cache entries in the
  113. * specified address range.
  114. *
  115. * - start - start address (inclusive)
  116. * - end - end address (exclusive)
  117. * - flags - vm_flags describing address space
  118. *
  119. * (same as arm926)
  120. */
  121. ENTRY(mohawk_flush_user_cache_range)
  122. mov ip, #0
  123. sub r3, r1, r0 @ calculate total size
  124. cmp r3, #CACHE_DLIMIT
  125. bgt __flush_whole_cache
  126. 1: tst r2, #VM_EXEC
  127. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  128. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  129. add r0, r0, #CACHE_DLINESIZE
  130. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  131. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  132. add r0, r0, #CACHE_DLINESIZE
  133. cmp r0, r1
  134. blo 1b
  135. tst r2, #VM_EXEC
  136. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  137. ret lr
  138. /*
  139. * coherent_kern_range(start, end)
  140. *
  141. * Ensure coherency between the Icache and the Dcache in the
  142. * region described by start, end. If you have non-snooping
  143. * Harvard caches, you need to implement this function.
  144. *
  145. * - start - virtual start address
  146. * - end - virtual end address
  147. */
  148. ENTRY(mohawk_coherent_kern_range)
  149. /* FALLTHROUGH */
  150. /*
  151. * coherent_user_range(start, end)
  152. *
  153. * Ensure coherency between the Icache and the Dcache in the
  154. * region described by start, end. If you have non-snooping
  155. * Harvard caches, you need to implement this function.
  156. *
  157. * - start - virtual start address
  158. * - end - virtual end address
  159. *
  160. * (same as arm926)
  161. */
  162. ENTRY(mohawk_coherent_user_range)
  163. bic r0, r0, #CACHE_DLINESIZE - 1
  164. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  165. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  166. add r0, r0, #CACHE_DLINESIZE
  167. cmp r0, r1
  168. blo 1b
  169. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  170. mov r0, #0
  171. ret lr
  172. /*
  173. * flush_kern_dcache_area(void *addr, size_t size)
  174. *
  175. * Ensure no D cache aliasing occurs, either with itself or
  176. * the I cache
  177. *
  178. * - addr - kernel address
  179. * - size - region size
  180. */
  181. ENTRY(mohawk_flush_kern_dcache_area)
  182. add r1, r0, r1
  183. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  184. add r0, r0, #CACHE_DLINESIZE
  185. cmp r0, r1
  186. blo 1b
  187. mov r0, #0
  188. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  189. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  190. ret lr
  191. /*
  192. * dma_inv_range(start, end)
  193. *
  194. * Invalidate (discard) the specified virtual address range.
  195. * May not write back any entries. If 'start' or 'end'
  196. * are not cache line aligned, those lines must be written
  197. * back.
  198. *
  199. * - start - virtual start address
  200. * - end - virtual end address
  201. *
  202. * (same as v4wb)
  203. */
  204. mohawk_dma_inv_range:
  205. tst r0, #CACHE_DLINESIZE - 1
  206. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  207. tst r1, #CACHE_DLINESIZE - 1
  208. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  209. bic r0, r0, #CACHE_DLINESIZE - 1
  210. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  211. add r0, r0, #CACHE_DLINESIZE
  212. cmp r0, r1
  213. blo 1b
  214. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  215. ret lr
  216. /*
  217. * dma_clean_range(start, end)
  218. *
  219. * Clean the specified virtual address range.
  220. *
  221. * - start - virtual start address
  222. * - end - virtual end address
  223. *
  224. * (same as v4wb)
  225. */
  226. mohawk_dma_clean_range:
  227. bic r0, r0, #CACHE_DLINESIZE - 1
  228. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  229. add r0, r0, #CACHE_DLINESIZE
  230. cmp r0, r1
  231. blo 1b
  232. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  233. ret lr
  234. /*
  235. * dma_flush_range(start, end)
  236. *
  237. * Clean and invalidate the specified virtual address range.
  238. *
  239. * - start - virtual start address
  240. * - end - virtual end address
  241. */
  242. ENTRY(mohawk_dma_flush_range)
  243. bic r0, r0, #CACHE_DLINESIZE - 1
  244. 1:
  245. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  246. add r0, r0, #CACHE_DLINESIZE
  247. cmp r0, r1
  248. blo 1b
  249. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  250. ret lr
  251. /*
  252. * dma_map_area(start, size, dir)
  253. * - start - kernel virtual start address
  254. * - size - size of region
  255. * - dir - DMA direction
  256. */
  257. ENTRY(mohawk_dma_map_area)
  258. add r1, r1, r0
  259. cmp r2, #DMA_TO_DEVICE
  260. beq mohawk_dma_clean_range
  261. bcs mohawk_dma_inv_range
  262. b mohawk_dma_flush_range
  263. ENDPROC(mohawk_dma_map_area)
  264. /*
  265. * dma_unmap_area(start, size, dir)
  266. * - start - kernel virtual start address
  267. * - size - size of region
  268. * - dir - DMA direction
  269. */
  270. ENTRY(mohawk_dma_unmap_area)
  271. ret lr
  272. ENDPROC(mohawk_dma_unmap_area)
  273. .globl mohawk_flush_kern_cache_louis
  274. .equ mohawk_flush_kern_cache_louis, mohawk_flush_kern_cache_all
  275. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  276. define_cache_functions mohawk
  277. ENTRY(cpu_mohawk_dcache_clean_area)
  278. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  279. add r0, r0, #CACHE_DLINESIZE
  280. subs r1, r1, #CACHE_DLINESIZE
  281. bhi 1b
  282. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  283. ret lr
  284. /*
  285. * cpu_mohawk_switch_mm(pgd)
  286. *
  287. * Set the translation base pointer to be as described by pgd.
  288. *
  289. * pgd: new page tables
  290. */
  291. .align 5
  292. ENTRY(cpu_mohawk_switch_mm)
  293. mov ip, #0
  294. mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
  295. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  296. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  297. orr r0, r0, #0x18 @ cache the page table in L2
  298. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  299. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  300. ret lr
  301. /*
  302. * cpu_mohawk_set_pte_ext(ptep, pte, ext)
  303. *
  304. * Set a PTE and flush it out
  305. */
  306. .align 5
  307. ENTRY(cpu_mohawk_set_pte_ext)
  308. #ifdef CONFIG_MMU
  309. armv3_set_pte_ext
  310. mov r0, r0
  311. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  312. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  313. ret lr
  314. #endif
  315. .globl cpu_mohawk_suspend_size
  316. .equ cpu_mohawk_suspend_size, 4 * 6
  317. #ifdef CONFIG_ARM_CPU_SUSPEND
  318. ENTRY(cpu_mohawk_do_suspend)
  319. stmfd sp!, {r4 - r9, lr}
  320. mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
  321. mrc p15, 0, r5, c15, c1, 0 @ CP access reg
  322. mrc p15, 0, r6, c13, c0, 0 @ PID
  323. mrc p15, 0, r7, c3, c0, 0 @ domain ID
  324. mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
  325. mrc p15, 0, r9, c1, c0, 0 @ control reg
  326. bic r4, r4, #2 @ clear frequency change bit
  327. stmia r0, {r4 - r9} @ store cp regs
  328. ldmia sp!, {r4 - r9, pc}
  329. ENDPROC(cpu_mohawk_do_suspend)
  330. ENTRY(cpu_mohawk_do_resume)
  331. ldmia r0, {r4 - r9} @ load cp regs
  332. mov ip, #0
  333. mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
  334. mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
  335. mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
  336. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  337. mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
  338. mcr p15, 0, r5, c15, c1, 0 @ CP access reg
  339. mcr p15, 0, r6, c13, c0, 0 @ PID
  340. mcr p15, 0, r7, c3, c0, 0 @ domain ID
  341. orr r1, r1, #0x18 @ cache the page table in L2
  342. mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
  343. mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
  344. mov r0, r9 @ control register
  345. b cpu_resume_mmu
  346. ENDPROC(cpu_mohawk_do_resume)
  347. #endif
  348. .type __mohawk_setup, #function
  349. __mohawk_setup:
  350. mov r0, #0
  351. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
  352. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  353. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
  354. orr r4, r4, #0x18 @ cache the page table in L2
  355. mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
  356. mov r0, #0 @ don't allow CP access
  357. mcr p15, 0, r0, c15, c1, 0 @ write CP access register
  358. adr r5, mohawk_crval
  359. ldmia r5, {r5, r6}
  360. mrc p15, 0, r0, c1, c0 @ get control register
  361. bic r0, r0, r5
  362. orr r0, r0, r6
  363. ret lr
  364. .size __mohawk_setup, . - __mohawk_setup
  365. /*
  366. * R
  367. * .RVI ZFRS BLDP WCAM
  368. * .011 1001 ..00 0101
  369. *
  370. */
  371. .type mohawk_crval, #object
  372. mohawk_crval:
  373. crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134
  374. __INITDATA
  375. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  376. define_processor_functions mohawk, dabort=v5t_early_abort, pabort=legacy_pabort
  377. .section ".rodata"
  378. string cpu_arch_name, "armv5te"
  379. string cpu_elf_name, "v5"
  380. string cpu_mohawk_name, "Marvell 88SV331x"
  381. .align
  382. .section ".proc.info.init", "a"
  383. .type __88sv331x_proc_info,#object
  384. __88sv331x_proc_info:
  385. .long 0x56158000 @ Marvell 88SV331x (MOHAWK)
  386. .long 0xfffff000
  387. .long PMD_TYPE_SECT | \
  388. PMD_SECT_BUFFERABLE | \
  389. PMD_SECT_CACHEABLE | \
  390. PMD_BIT4 | \
  391. PMD_SECT_AP_WRITE | \
  392. PMD_SECT_AP_READ
  393. .long PMD_TYPE_SECT | \
  394. PMD_BIT4 | \
  395. PMD_SECT_AP_WRITE | \
  396. PMD_SECT_AP_READ
  397. initfn __mohawk_setup, __88sv331x_proc_info
  398. .long cpu_arch_name
  399. .long cpu_elf_name
  400. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
  401. .long cpu_mohawk_name
  402. .long mohawk_processor_functions
  403. .long v4wbi_tlb_fns
  404. .long v4wb_user_fns
  405. .long mohawk_cache_fns
  406. .size __88sv331x_proc_info, . - __88sv331x_proc_info