proc-fa526.S 4.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
  4. *
  5. * Written by : Luke Lee
  6. * Copyright (C) 2005 Faraday Corp.
  7. * Copyright (C) 2008-2009 Paulius Zaleckas <[email protected]>
  8. *
  9. * These are the low level assembler for performing cache and TLB
  10. * functions on the fa526.
  11. */
  12. #include <linux/linkage.h>
  13. #include <linux/init.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/assembler.h>
  16. #include <asm/hwcap.h>
  17. #include <asm/pgtable-hwdef.h>
  18. #include <asm/page.h>
  19. #include <asm/ptrace.h>
  20. #include "proc-macros.S"
  21. #define CACHE_DLINESIZE 16
  22. .text
  23. /*
  24. * cpu_fa526_proc_init()
  25. */
  26. ENTRY(cpu_fa526_proc_init)
  27. ret lr
  28. /*
  29. * cpu_fa526_proc_fin()
  30. */
  31. ENTRY(cpu_fa526_proc_fin)
  32. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  33. bic r0, r0, #0x1000 @ ...i............
  34. bic r0, r0, #0x000e @ ............wca.
  35. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  36. nop
  37. nop
  38. ret lr
  39. /*
  40. * cpu_fa526_reset(loc)
  41. *
  42. * Perform a soft reset of the system. Put the CPU into the
  43. * same state as it would be if it had been reset, and branch
  44. * to what would be the reset vector.
  45. *
  46. * loc: location to jump to for soft reset
  47. */
  48. .align 4
  49. .pushsection .idmap.text, "ax"
  50. ENTRY(cpu_fa526_reset)
  51. /* TODO: Use CP8 if possible... */
  52. mov ip, #0
  53. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  54. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  55. #ifdef CONFIG_MMU
  56. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  57. #endif
  58. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  59. bic ip, ip, #0x000f @ ............wcam
  60. bic ip, ip, #0x1100 @ ...i...s........
  61. bic ip, ip, #0x0800 @ BTB off
  62. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  63. nop
  64. nop
  65. ret r0
  66. ENDPROC(cpu_fa526_reset)
  67. .popsection
  68. /*
  69. * cpu_fa526_do_idle()
  70. */
  71. .align 4
  72. ENTRY(cpu_fa526_do_idle)
  73. ret lr
  74. ENTRY(cpu_fa526_dcache_clean_area)
  75. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  76. add r0, r0, #CACHE_DLINESIZE
  77. subs r1, r1, #CACHE_DLINESIZE
  78. bhi 1b
  79. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  80. ret lr
  81. /* =============================== PageTable ============================== */
  82. /*
  83. * cpu_fa526_switch_mm(pgd)
  84. *
  85. * Set the translation base pointer to be as described by pgd.
  86. *
  87. * pgd: new page tables
  88. */
  89. .align 4
  90. ENTRY(cpu_fa526_switch_mm)
  91. #ifdef CONFIG_MMU
  92. mov ip, #0
  93. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  94. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  95. #else
  96. mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
  97. #endif
  98. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  99. mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
  100. mcr p15, 0, ip, c7, c10, 4 @ data write barrier
  101. mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
  102. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  103. mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
  104. #endif
  105. ret lr
  106. /*
  107. * cpu_fa526_set_pte_ext(ptep, pte, ext)
  108. *
  109. * Set a PTE and flush it out
  110. */
  111. .align 4
  112. ENTRY(cpu_fa526_set_pte_ext)
  113. #ifdef CONFIG_MMU
  114. armv3_set_pte_ext
  115. mov r0, r0
  116. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  117. mov r0, #0
  118. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  119. #endif
  120. ret lr
  121. .type __fa526_setup, #function
  122. __fa526_setup:
  123. /* On return of this routine, r0 must carry correct flags for CFG register */
  124. mov r0, #0
  125. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  126. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  127. #ifdef CONFIG_MMU
  128. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  129. #endif
  130. mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
  131. mov r0, #1
  132. mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
  133. mov r0, #0
  134. mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
  135. mcr p15, 0, r0, c7, c10, 4 @ data write barrier
  136. mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
  137. mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
  138. mcr p15, 0, r0, c3, c0 @ load domain access register
  139. mrc p15, 0, r0, c1, c0 @ get control register v4
  140. ldr r5, fa526_cr1_clear
  141. bic r0, r0, r5
  142. ldr r5, fa526_cr1_set
  143. orr r0, r0, r5
  144. ret lr
  145. .size __fa526_setup, . - __fa526_setup
  146. /*
  147. * .RVI ZFRS BLDP WCAM
  148. * ..11 1001 .111 1101
  149. *
  150. */
  151. .type fa526_cr1_clear, #object
  152. .type fa526_cr1_set, #object
  153. fa526_cr1_clear:
  154. .word 0x3f3f
  155. fa526_cr1_set:
  156. .word 0x397D
  157. __INITDATA
  158. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  159. define_processor_functions fa526, dabort=v4_early_abort, pabort=legacy_pabort
  160. .section ".rodata"
  161. string cpu_arch_name, "armv4"
  162. string cpu_elf_name, "v4"
  163. string cpu_fa526_name, "FA526"
  164. .align
  165. .section ".proc.info.init", "a"
  166. .type __fa526_proc_info,#object
  167. __fa526_proc_info:
  168. .long 0x66015261
  169. .long 0xff01fff1
  170. .long PMD_TYPE_SECT | \
  171. PMD_SECT_BUFFERABLE | \
  172. PMD_SECT_CACHEABLE | \
  173. PMD_BIT4 | \
  174. PMD_SECT_AP_WRITE | \
  175. PMD_SECT_AP_READ
  176. .long PMD_TYPE_SECT | \
  177. PMD_BIT4 | \
  178. PMD_SECT_AP_WRITE | \
  179. PMD_SECT_AP_READ
  180. initfn __fa526_setup, __fa526_proc_info
  181. .long cpu_arch_name
  182. .long cpu_elf_name
  183. .long HWCAP_SWP | HWCAP_HALF
  184. .long cpu_fa526_name
  185. .long fa526_processor_functions
  186. .long fa_tlb_fns
  187. .long fa_user_fns
  188. .long fa_cache_fns
  189. .size __fa526_proc_info, . - __fa526_proc_info