proc-arm946.S 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
  4. *
  5. * Copyright (C) 2004-2006 Hyok S. Choi ([email protected])
  6. *
  7. * (Many of cache codes are from proc-arm926.S)
  8. */
  9. #include <linux/linkage.h>
  10. #include <linux/init.h>
  11. #include <linux/pgtable.h>
  12. #include <asm/assembler.h>
  13. #include <asm/hwcap.h>
  14. #include <asm/pgtable-hwdef.h>
  15. #include <asm/ptrace.h>
  16. #include "proc-macros.S"
  17. /*
  18. * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
  19. * comprising 256 lines of 32 bytes (8 words).
  20. */
  21. #define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
  22. #define CACHE_DLINESIZE 32 /* fixed */
  23. #define CACHE_DSEGMENTS 4 /* fixed */
  24. #define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
  25. #define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
  26. .text
  27. /*
  28. * cpu_arm946_proc_init()
  29. * cpu_arm946_switch_mm()
  30. *
  31. * These are not required.
  32. */
  33. ENTRY(cpu_arm946_proc_init)
  34. ENTRY(cpu_arm946_switch_mm)
  35. ret lr
  36. /*
  37. * cpu_arm946_proc_fin()
  38. */
  39. ENTRY(cpu_arm946_proc_fin)
  40. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  41. bic r0, r0, #0x00001000 @ i-cache
  42. bic r0, r0, #0x00000004 @ d-cache
  43. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  44. ret lr
  45. /*
  46. * cpu_arm946_reset(loc)
  47. * Params : r0 = address to jump to
  48. * Notes : This sets up everything for a reset
  49. */
  50. .pushsection .idmap.text, "ax"
  51. ENTRY(cpu_arm946_reset)
  52. mov ip, #0
  53. mcr p15, 0, ip, c7, c5, 0 @ flush I cache
  54. mcr p15, 0, ip, c7, c6, 0 @ flush D cache
  55. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  56. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  57. bic ip, ip, #0x00000005 @ .............c.p
  58. bic ip, ip, #0x00001000 @ i-cache
  59. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  60. ret r0
  61. ENDPROC(cpu_arm946_reset)
  62. .popsection
  63. /*
  64. * cpu_arm946_do_idle()
  65. */
  66. .align 5
  67. ENTRY(cpu_arm946_do_idle)
  68. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  69. ret lr
  70. /*
  71. * flush_icache_all()
  72. *
  73. * Unconditionally clean and invalidate the entire icache.
  74. */
  75. ENTRY(arm946_flush_icache_all)
  76. mov r0, #0
  77. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  78. ret lr
  79. ENDPROC(arm946_flush_icache_all)
  80. /*
  81. * flush_user_cache_all()
  82. */
  83. ENTRY(arm946_flush_user_cache_all)
  84. /* FALLTHROUGH */
  85. /*
  86. * flush_kern_cache_all()
  87. *
  88. * Clean and invalidate the entire cache.
  89. */
  90. ENTRY(arm946_flush_kern_cache_all)
  91. mov r2, #VM_EXEC
  92. mov ip, #0
  93. __flush_whole_cache:
  94. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  95. mcr p15, 0, ip, c7, c6, 0 @ flush D cache
  96. #else
  97. mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
  98. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
  99. 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
  100. subs r3, r3, #1 << 4
  101. bcs 2b @ entries n to 0
  102. subs r1, r1, #1 << 29
  103. bcs 1b @ segments 3 to 0
  104. #endif
  105. tst r2, #VM_EXEC
  106. mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
  107. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  108. ret lr
  109. /*
  110. * flush_user_cache_range(start, end, flags)
  111. *
  112. * Clean and invalidate a range of cache entries in the
  113. * specified address range.
  114. *
  115. * - start - start address (inclusive)
  116. * - end - end address (exclusive)
  117. * - flags - vm_flags describing address space
  118. * (same as arm926)
  119. */
  120. ENTRY(arm946_flush_user_cache_range)
  121. mov ip, #0
  122. sub r3, r1, r0 @ calculate total size
  123. cmp r3, #CACHE_DLIMIT
  124. bhs __flush_whole_cache
  125. 1: tst r2, #VM_EXEC
  126. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  127. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  128. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  129. add r0, r0, #CACHE_DLINESIZE
  130. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  131. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  132. add r0, r0, #CACHE_DLINESIZE
  133. #else
  134. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  135. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  136. add r0, r0, #CACHE_DLINESIZE
  137. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  138. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  139. add r0, r0, #CACHE_DLINESIZE
  140. #endif
  141. cmp r0, r1
  142. blo 1b
  143. tst r2, #VM_EXEC
  144. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  145. ret lr
  146. /*
  147. * coherent_kern_range(start, end)
  148. *
  149. * Ensure coherency between the Icache and the Dcache in the
  150. * region described by start, end. If you have non-snooping
  151. * Harvard caches, you need to implement this function.
  152. *
  153. * - start - virtual start address
  154. * - end - virtual end address
  155. */
  156. ENTRY(arm946_coherent_kern_range)
  157. /* FALLTHROUGH */
  158. /*
  159. * coherent_user_range(start, end)
  160. *
  161. * Ensure coherency between the Icache and the Dcache in the
  162. * region described by start, end. If you have non-snooping
  163. * Harvard caches, you need to implement this function.
  164. *
  165. * - start - virtual start address
  166. * - end - virtual end address
  167. * (same as arm926)
  168. */
  169. ENTRY(arm946_coherent_user_range)
  170. bic r0, r0, #CACHE_DLINESIZE - 1
  171. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  172. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  173. add r0, r0, #CACHE_DLINESIZE
  174. cmp r0, r1
  175. blo 1b
  176. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  177. mov r0, #0
  178. ret lr
  179. /*
  180. * flush_kern_dcache_area(void *addr, size_t size)
  181. *
  182. * Ensure no D cache aliasing occurs, either with itself or
  183. * the I cache
  184. *
  185. * - addr - kernel address
  186. * - size - region size
  187. * (same as arm926)
  188. */
  189. ENTRY(arm946_flush_kern_dcache_area)
  190. add r1, r0, r1
  191. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  192. add r0, r0, #CACHE_DLINESIZE
  193. cmp r0, r1
  194. blo 1b
  195. mov r0, #0
  196. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  197. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  198. ret lr
  199. /*
  200. * dma_inv_range(start, end)
  201. *
  202. * Invalidate (discard) the specified virtual address range.
  203. * May not write back any entries. If 'start' or 'end'
  204. * are not cache line aligned, those lines must be written
  205. * back.
  206. *
  207. * - start - virtual start address
  208. * - end - virtual end address
  209. * (same as arm926)
  210. */
  211. arm946_dma_inv_range:
  212. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  213. tst r0, #CACHE_DLINESIZE - 1
  214. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  215. tst r1, #CACHE_DLINESIZE - 1
  216. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  217. #endif
  218. bic r0, r0, #CACHE_DLINESIZE - 1
  219. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  220. add r0, r0, #CACHE_DLINESIZE
  221. cmp r0, r1
  222. blo 1b
  223. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  224. ret lr
  225. /*
  226. * dma_clean_range(start, end)
  227. *
  228. * Clean the specified virtual address range.
  229. *
  230. * - start - virtual start address
  231. * - end - virtual end address
  232. *
  233. * (same as arm926)
  234. */
  235. arm946_dma_clean_range:
  236. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  237. bic r0, r0, #CACHE_DLINESIZE - 1
  238. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  239. add r0, r0, #CACHE_DLINESIZE
  240. cmp r0, r1
  241. blo 1b
  242. #endif
  243. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  244. ret lr
  245. /*
  246. * dma_flush_range(start, end)
  247. *
  248. * Clean and invalidate the specified virtual address range.
  249. *
  250. * - start - virtual start address
  251. * - end - virtual end address
  252. *
  253. * (same as arm926)
  254. */
  255. ENTRY(arm946_dma_flush_range)
  256. bic r0, r0, #CACHE_DLINESIZE - 1
  257. 1:
  258. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  259. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  260. #else
  261. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  262. #endif
  263. add r0, r0, #CACHE_DLINESIZE
  264. cmp r0, r1
  265. blo 1b
  266. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  267. ret lr
  268. /*
  269. * dma_map_area(start, size, dir)
  270. * - start - kernel virtual start address
  271. * - size - size of region
  272. * - dir - DMA direction
  273. */
  274. ENTRY(arm946_dma_map_area)
  275. add r1, r1, r0
  276. cmp r2, #DMA_TO_DEVICE
  277. beq arm946_dma_clean_range
  278. bcs arm946_dma_inv_range
  279. b arm946_dma_flush_range
  280. ENDPROC(arm946_dma_map_area)
  281. /*
  282. * dma_unmap_area(start, size, dir)
  283. * - start - kernel virtual start address
  284. * - size - size of region
  285. * - dir - DMA direction
  286. */
  287. ENTRY(arm946_dma_unmap_area)
  288. ret lr
  289. ENDPROC(arm946_dma_unmap_area)
  290. .globl arm946_flush_kern_cache_louis
  291. .equ arm946_flush_kern_cache_louis, arm946_flush_kern_cache_all
  292. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  293. define_cache_functions arm946
  294. ENTRY(cpu_arm946_dcache_clean_area)
  295. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  296. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  297. add r0, r0, #CACHE_DLINESIZE
  298. subs r1, r1, #CACHE_DLINESIZE
  299. bhi 1b
  300. #endif
  301. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  302. ret lr
  303. .type __arm946_setup, #function
  304. __arm946_setup:
  305. mov r0, #0
  306. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  307. mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
  308. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  309. mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
  310. mcr p15, 0, r0, c6, c4, 0
  311. mcr p15, 0, r0, c6, c5, 0
  312. mcr p15, 0, r0, c6, c6, 0
  313. mcr p15, 0, r0, c6, c7, 0
  314. mov r0, #0x0000003F @ base = 0, size = 4GB
  315. mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
  316. ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  317. ldr r7, =CONFIG_DRAM_SIZE @ size of RAM (must be >= 4KB)
  318. pr_val r3, r0, r7, #1
  319. mcr p15, 0, r3, c6, c1, 0
  320. ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  321. ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
  322. pr_val r3, r0, r7, #1
  323. mcr p15, 0, r3, c6, c2, 0
  324. mov r0, #0x06
  325. mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
  326. mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
  327. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  328. mov r0, #0x00 @ disable whole write buffer
  329. #else
  330. mov r0, #0x02 @ region 1 write bufferred
  331. #endif
  332. mcr p15, 0, r0, c3, c0, 0
  333. /*
  334. * Access Permission Settings for future permission control by PU.
  335. *
  336. * priv. user
  337. * region 0 (whole) rw -- : b0001
  338. * region 1 (RAM) rw rw : b0011
  339. * region 2 (FLASH) rw r- : b0010
  340. * region 3~7 (none) -- -- : b0000
  341. */
  342. mov r0, #0x00000031
  343. orr r0, r0, #0x00000200
  344. mcr p15, 0, r0, c5, c0, 2 @ set data access permission
  345. mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
  346. mrc p15, 0, r0, c1, c0 @ get control register
  347. orr r0, r0, #0x00001000 @ I-cache
  348. orr r0, r0, #0x00000005 @ MPU/D-cache
  349. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  350. orr r0, r0, #0x00004000 @ .1.. .... .... ....
  351. #endif
  352. ret lr
  353. .size __arm946_setup, . - __arm946_setup
  354. __INITDATA
  355. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  356. define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
  357. .section ".rodata"
  358. string cpu_arch_name, "armv5te"
  359. string cpu_elf_name, "v5t"
  360. string cpu_arm946_name, "ARM946E-S"
  361. .align
  362. .section ".proc.info.init", "a"
  363. .type __arm946_proc_info,#object
  364. __arm946_proc_info:
  365. .long 0x41009460
  366. .long 0xff00fff0
  367. .long 0
  368. .long 0
  369. initfn __arm946_setup, __arm946_proc_info
  370. .long cpu_arch_name
  371. .long cpu_elf_name
  372. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  373. .long cpu_arm946_name
  374. .long arm946_processor_functions
  375. .long 0
  376. .long 0
  377. .long arm946_cache_fns
  378. .size __arm946_proc_info, . - __arm946_proc_info