proc-arm926.S 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
  4. *
  5. * Copyright (C) 1999-2001 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  8. *
  9. * These are the low level assembler for performing cache and TLB
  10. * functions on the arm926.
  11. *
  12. * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/init.h>
  16. #include <linux/pgtable.h>
  17. #include <asm/assembler.h>
  18. #include <asm/hwcap.h>
  19. #include <asm/pgtable-hwdef.h>
  20. #include <asm/page.h>
  21. #include <asm/ptrace.h>
  22. #include "proc-macros.S"
  23. /*
  24. * This is the maximum size of an area which will be invalidated
  25. * using the single invalidate entry instructions. Anything larger
  26. * than this, and we go for the whole cache.
  27. *
  28. * This value should be chosen such that we choose the cheapest
  29. * alternative.
  30. */
  31. #define CACHE_DLIMIT 16384
  32. /*
  33. * the cache line size of the I and D cache
  34. */
  35. #define CACHE_DLINESIZE 32
  36. .text
  37. /*
  38. * cpu_arm926_proc_init()
  39. */
  40. ENTRY(cpu_arm926_proc_init)
  41. ret lr
  42. /*
  43. * cpu_arm926_proc_fin()
  44. */
  45. ENTRY(cpu_arm926_proc_fin)
  46. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  47. bic r0, r0, #0x1000 @ ...i............
  48. bic r0, r0, #0x000e @ ............wca.
  49. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  50. ret lr
  51. /*
  52. * cpu_arm926_reset(loc)
  53. *
  54. * Perform a soft reset of the system. Put the CPU into the
  55. * same state as it would be if it had been reset, and branch
  56. * to what would be the reset vector.
  57. *
  58. * loc: location to jump to for soft reset
  59. */
  60. .align 5
  61. .pushsection .idmap.text, "ax"
  62. ENTRY(cpu_arm926_reset)
  63. mov ip, #0
  64. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  65. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  66. #ifdef CONFIG_MMU
  67. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  68. #endif
  69. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  70. bic ip, ip, #0x000f @ ............wcam
  71. bic ip, ip, #0x1100 @ ...i...s........
  72. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  73. ret r0
  74. ENDPROC(cpu_arm926_reset)
  75. .popsection
  76. /*
  77. * cpu_arm926_do_idle()
  78. *
  79. * Called with IRQs disabled
  80. */
  81. .align 10
  82. ENTRY(cpu_arm926_do_idle)
  83. mov r0, #0
  84. mrc p15, 0, r1, c1, c0, 0 @ Read control register
  85. mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
  86. bic r2, r1, #1 << 12
  87. mrs r3, cpsr @ Disable FIQs while Icache
  88. orr ip, r3, #PSR_F_BIT @ is disabled
  89. msr cpsr_c, ip
  90. mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
  91. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  92. mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
  93. msr cpsr_c, r3 @ Restore FIQ state
  94. ret lr
  95. /*
  96. * flush_icache_all()
  97. *
  98. * Unconditionally clean and invalidate the entire icache.
  99. */
  100. ENTRY(arm926_flush_icache_all)
  101. mov r0, #0
  102. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  103. ret lr
  104. ENDPROC(arm926_flush_icache_all)
  105. /*
  106. * flush_user_cache_all()
  107. *
  108. * Clean and invalidate all cache entries in a particular
  109. * address space.
  110. */
  111. ENTRY(arm926_flush_user_cache_all)
  112. /* FALLTHROUGH */
  113. /*
  114. * flush_kern_cache_all()
  115. *
  116. * Clean and invalidate the entire cache.
  117. */
  118. ENTRY(arm926_flush_kern_cache_all)
  119. mov r2, #VM_EXEC
  120. mov ip, #0
  121. __flush_whole_cache:
  122. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  123. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  124. #else
  125. 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
  126. bne 1b
  127. #endif
  128. tst r2, #VM_EXEC
  129. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  130. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  131. ret lr
  132. /*
  133. * flush_user_cache_range(start, end, flags)
  134. *
  135. * Clean and invalidate a range of cache entries in the
  136. * specified address range.
  137. *
  138. * - start - start address (inclusive)
  139. * - end - end address (exclusive)
  140. * - flags - vm_flags describing address space
  141. */
  142. ENTRY(arm926_flush_user_cache_range)
  143. mov ip, #0
  144. sub r3, r1, r0 @ calculate total size
  145. cmp r3, #CACHE_DLIMIT
  146. bgt __flush_whole_cache
  147. 1: tst r2, #VM_EXEC
  148. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  149. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  150. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  151. add r0, r0, #CACHE_DLINESIZE
  152. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  153. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  154. add r0, r0, #CACHE_DLINESIZE
  155. #else
  156. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  157. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  158. add r0, r0, #CACHE_DLINESIZE
  159. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  160. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  161. add r0, r0, #CACHE_DLINESIZE
  162. #endif
  163. cmp r0, r1
  164. blo 1b
  165. tst r2, #VM_EXEC
  166. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  167. ret lr
  168. /*
  169. * coherent_kern_range(start, end)
  170. *
  171. * Ensure coherency between the Icache and the Dcache in the
  172. * region described by start, end. If you have non-snooping
  173. * Harvard caches, you need to implement this function.
  174. *
  175. * - start - virtual start address
  176. * - end - virtual end address
  177. */
  178. ENTRY(arm926_coherent_kern_range)
  179. /* FALLTHROUGH */
  180. /*
  181. * coherent_user_range(start, end)
  182. *
  183. * Ensure coherency between the Icache and the Dcache in the
  184. * region described by start, end. If you have non-snooping
  185. * Harvard caches, you need to implement this function.
  186. *
  187. * - start - virtual start address
  188. * - end - virtual end address
  189. */
  190. ENTRY(arm926_coherent_user_range)
  191. bic r0, r0, #CACHE_DLINESIZE - 1
  192. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  193. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  194. add r0, r0, #CACHE_DLINESIZE
  195. cmp r0, r1
  196. blo 1b
  197. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  198. mov r0, #0
  199. ret lr
  200. /*
  201. * flush_kern_dcache_area(void *addr, size_t size)
  202. *
  203. * Ensure no D cache aliasing occurs, either with itself or
  204. * the I cache
  205. *
  206. * - addr - kernel address
  207. * - size - region size
  208. */
  209. ENTRY(arm926_flush_kern_dcache_area)
  210. add r1, r0, r1
  211. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  212. add r0, r0, #CACHE_DLINESIZE
  213. cmp r0, r1
  214. blo 1b
  215. mov r0, #0
  216. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  217. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  218. ret lr
  219. /*
  220. * dma_inv_range(start, end)
  221. *
  222. * Invalidate (discard) the specified virtual address range.
  223. * May not write back any entries. If 'start' or 'end'
  224. * are not cache line aligned, those lines must be written
  225. * back.
  226. *
  227. * - start - virtual start address
  228. * - end - virtual end address
  229. *
  230. * (same as v4wb)
  231. */
  232. arm926_dma_inv_range:
  233. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  234. tst r0, #CACHE_DLINESIZE - 1
  235. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  236. tst r1, #CACHE_DLINESIZE - 1
  237. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  238. #endif
  239. bic r0, r0, #CACHE_DLINESIZE - 1
  240. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  241. add r0, r0, #CACHE_DLINESIZE
  242. cmp r0, r1
  243. blo 1b
  244. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  245. ret lr
  246. /*
  247. * dma_clean_range(start, end)
  248. *
  249. * Clean the specified virtual address range.
  250. *
  251. * - start - virtual start address
  252. * - end - virtual end address
  253. *
  254. * (same as v4wb)
  255. */
  256. arm926_dma_clean_range:
  257. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  258. bic r0, r0, #CACHE_DLINESIZE - 1
  259. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  260. add r0, r0, #CACHE_DLINESIZE
  261. cmp r0, r1
  262. blo 1b
  263. #endif
  264. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  265. ret lr
  266. /*
  267. * dma_flush_range(start, end)
  268. *
  269. * Clean and invalidate the specified virtual address range.
  270. *
  271. * - start - virtual start address
  272. * - end - virtual end address
  273. */
  274. ENTRY(arm926_dma_flush_range)
  275. bic r0, r0, #CACHE_DLINESIZE - 1
  276. 1:
  277. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  278. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  279. #else
  280. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  281. #endif
  282. add r0, r0, #CACHE_DLINESIZE
  283. cmp r0, r1
  284. blo 1b
  285. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  286. ret lr
  287. /*
  288. * dma_map_area(start, size, dir)
  289. * - start - kernel virtual start address
  290. * - size - size of region
  291. * - dir - DMA direction
  292. */
  293. ENTRY(arm926_dma_map_area)
  294. add r1, r1, r0
  295. cmp r2, #DMA_TO_DEVICE
  296. beq arm926_dma_clean_range
  297. bcs arm926_dma_inv_range
  298. b arm926_dma_flush_range
  299. ENDPROC(arm926_dma_map_area)
  300. /*
  301. * dma_unmap_area(start, size, dir)
  302. * - start - kernel virtual start address
  303. * - size - size of region
  304. * - dir - DMA direction
  305. */
  306. ENTRY(arm926_dma_unmap_area)
  307. ret lr
  308. ENDPROC(arm926_dma_unmap_area)
  309. .globl arm926_flush_kern_cache_louis
  310. .equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all
  311. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  312. define_cache_functions arm926
  313. ENTRY(cpu_arm926_dcache_clean_area)
  314. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  315. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  316. add r0, r0, #CACHE_DLINESIZE
  317. subs r1, r1, #CACHE_DLINESIZE
  318. bhi 1b
  319. #endif
  320. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  321. ret lr
  322. /* =============================== PageTable ============================== */
  323. /*
  324. * cpu_arm926_switch_mm(pgd)
  325. *
  326. * Set the translation base pointer to be as described by pgd.
  327. *
  328. * pgd: new page tables
  329. */
  330. .align 5
  331. ENTRY(cpu_arm926_switch_mm)
  332. #ifdef CONFIG_MMU
  333. mov ip, #0
  334. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  335. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  336. #else
  337. @ && 'Clean & Invalidate whole DCache'
  338. 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate
  339. bne 1b
  340. #endif
  341. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  342. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  343. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  344. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  345. #endif
  346. ret lr
  347. /*
  348. * cpu_arm926_set_pte_ext(ptep, pte, ext)
  349. *
  350. * Set a PTE and flush it out
  351. */
  352. .align 5
  353. ENTRY(cpu_arm926_set_pte_ext)
  354. #ifdef CONFIG_MMU
  355. armv3_set_pte_ext
  356. mov r0, r0
  357. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  358. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  359. #endif
  360. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  361. #endif
  362. ret lr
  363. /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
  364. .globl cpu_arm926_suspend_size
  365. .equ cpu_arm926_suspend_size, 4 * 3
  366. #ifdef CONFIG_ARM_CPU_SUSPEND
  367. ENTRY(cpu_arm926_do_suspend)
  368. stmfd sp!, {r4 - r6, lr}
  369. mrc p15, 0, r4, c13, c0, 0 @ PID
  370. mrc p15, 0, r5, c3, c0, 0 @ Domain ID
  371. mrc p15, 0, r6, c1, c0, 0 @ Control register
  372. stmia r0, {r4 - r6}
  373. ldmfd sp!, {r4 - r6, pc}
  374. ENDPROC(cpu_arm926_do_suspend)
  375. ENTRY(cpu_arm926_do_resume)
  376. mov ip, #0
  377. mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
  378. mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
  379. ldmia r0, {r4 - r6}
  380. mcr p15, 0, r4, c13, c0, 0 @ PID
  381. mcr p15, 0, r5, c3, c0, 0 @ Domain ID
  382. mcr p15, 0, r1, c2, c0, 0 @ TTB address
  383. mov r0, r6 @ control register
  384. b cpu_resume_mmu
  385. ENDPROC(cpu_arm926_do_resume)
  386. #endif
  387. .type __arm926_setup, #function
  388. __arm926_setup:
  389. mov r0, #0
  390. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  391. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  392. #ifdef CONFIG_MMU
  393. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  394. #endif
  395. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  396. mov r0, #4 @ disable write-back on caches explicitly
  397. mcr p15, 7, r0, c15, c0, 0
  398. #endif
  399. adr r5, arm926_crval
  400. ldmia r5, {r5, r6}
  401. mrc p15, 0, r0, c1, c0 @ get control register v4
  402. bic r0, r0, r5
  403. orr r0, r0, r6
  404. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  405. orr r0, r0, #0x4000 @ .1.. .... .... ....
  406. #endif
  407. ret lr
  408. .size __arm926_setup, . - __arm926_setup
  409. /*
  410. * R
  411. * .RVI ZFRS BLDP WCAM
  412. * .011 0001 ..11 0101
  413. *
  414. */
  415. .type arm926_crval, #object
  416. arm926_crval:
  417. crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
  418. __INITDATA
  419. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  420. define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
  421. .section ".rodata"
  422. string cpu_arch_name, "armv5tej"
  423. string cpu_elf_name, "v5"
  424. string cpu_arm926_name, "ARM926EJ-S"
  425. .align
  426. .section ".proc.info.init", "a"
  427. .type __arm926_proc_info,#object
  428. __arm926_proc_info:
  429. .long 0x41069260 @ ARM926EJ-S (v5TEJ)
  430. .long 0xff0ffff0
  431. .long PMD_TYPE_SECT | \
  432. PMD_SECT_BUFFERABLE | \
  433. PMD_SECT_CACHEABLE | \
  434. PMD_BIT4 | \
  435. PMD_SECT_AP_WRITE | \
  436. PMD_SECT_AP_READ
  437. .long PMD_TYPE_SECT | \
  438. PMD_BIT4 | \
  439. PMD_SECT_AP_WRITE | \
  440. PMD_SECT_AP_READ
  441. initfn __arm926_setup, __arm926_proc_info
  442. .long cpu_arch_name
  443. .long cpu_elf_name
  444. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
  445. .long cpu_arm926_name
  446. .long arm926_processor_functions
  447. .long v4wbi_tlb_fns
  448. .long v4wb_user_fns
  449. .long arm926_cache_fns
  450. .size __arm926_proc_info, . - __arm926_proc_info