proc-arm925.S 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
  4. *
  5. * Copyright (C) 1999,2000 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * Copyright (C) 2002 RidgeRun, Inc.
  8. * Copyright (C) 2002-2003 MontaVista Software, Inc.
  9. *
  10. * Update for Linux-2.6 and cache flush improvements
  11. * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <[email protected]>
  12. *
  13. * hacked for non-paged-MM by Hyok S. Choi, 2004.
  14. *
  15. * These are the low level assembler for performing cache and TLB
  16. * functions on the arm925.
  17. *
  18. * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
  19. *
  20. * Some additional notes based on deciphering the TI TRM on OMAP-5910:
  21. *
  22. * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
  23. * entry mode" must be 0 to flush the entries in both segments
  24. * at once. This is the default value. See TRM 2-20 and 2-24 for
  25. * more information.
  26. *
  27. * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
  28. * like the "Transparent mode" must be on for partial cache flushes
  29. * to work in this mode. This mode only works with 16-bit external
  30. * memory. See TRM 2-24 for more information.
  31. *
  32. * NOTE3: Write-back cache flushing seems to be flakey with devices using
  33. * direct memory access, such as USB OHCI. The workaround is to use
  34. * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
  35. * the default for OMAP-1510).
  36. */
  37. #include <linux/linkage.h>
  38. #include <linux/init.h>
  39. #include <linux/pgtable.h>
  40. #include <asm/assembler.h>
  41. #include <asm/hwcap.h>
  42. #include <asm/pgtable-hwdef.h>
  43. #include <asm/page.h>
  44. #include <asm/ptrace.h>
  45. #include "proc-macros.S"
  46. /*
  47. * The size of one data cache line.
  48. */
  49. #define CACHE_DLINESIZE 16
  50. /*
  51. * The number of data cache segments.
  52. */
  53. #define CACHE_DSEGMENTS 2
  54. /*
  55. * The number of lines in a cache segment.
  56. */
  57. #define CACHE_DENTRIES 256
  58. /*
  59. * This is the size at which it becomes more efficient to
  60. * clean the whole cache, rather than using the individual
  61. * cache line maintenance instructions.
  62. */
  63. #define CACHE_DLIMIT 8192
  64. .text
  65. /*
  66. * cpu_arm925_proc_init()
  67. */
  68. ENTRY(cpu_arm925_proc_init)
  69. ret lr
  70. /*
  71. * cpu_arm925_proc_fin()
  72. */
  73. ENTRY(cpu_arm925_proc_fin)
  74. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  75. bic r0, r0, #0x1000 @ ...i............
  76. bic r0, r0, #0x000e @ ............wca.
  77. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  78. ret lr
  79. /*
  80. * cpu_arm925_reset(loc)
  81. *
  82. * Perform a soft reset of the system. Put the CPU into the
  83. * same state as it would be if it had been reset, and branch
  84. * to what would be the reset vector.
  85. *
  86. * loc: location to jump to for soft reset
  87. */
  88. .align 5
  89. .pushsection .idmap.text, "ax"
  90. ENTRY(cpu_arm925_reset)
  91. /* Send software reset to MPU and DSP */
  92. mov ip, #0xff000000
  93. orr ip, ip, #0x00fe0000
  94. orr ip, ip, #0x0000ce00
  95. mov r4, #1
  96. strh r4, [ip, #0x10]
  97. ENDPROC(cpu_arm925_reset)
  98. .popsection
  99. mov ip, #0
  100. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  101. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  102. #ifdef CONFIG_MMU
  103. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  104. #endif
  105. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  106. bic ip, ip, #0x000f @ ............wcam
  107. bic ip, ip, #0x1100 @ ...i...s........
  108. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  109. ret r0
  110. /*
  111. * cpu_arm925_do_idle()
  112. *
  113. * Called with IRQs disabled
  114. */
  115. .align 10
  116. ENTRY(cpu_arm925_do_idle)
  117. mov r0, #0
  118. mrc p15, 0, r1, c1, c0, 0 @ Read control register
  119. mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
  120. bic r2, r1, #1 << 12
  121. mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
  122. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  123. mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
  124. ret lr
  125. /*
  126. * flush_icache_all()
  127. *
  128. * Unconditionally clean and invalidate the entire icache.
  129. */
  130. ENTRY(arm925_flush_icache_all)
  131. mov r0, #0
  132. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  133. ret lr
  134. ENDPROC(arm925_flush_icache_all)
  135. /*
  136. * flush_user_cache_all()
  137. *
  138. * Clean and invalidate all cache entries in a particular
  139. * address space.
  140. */
  141. ENTRY(arm925_flush_user_cache_all)
  142. /* FALLTHROUGH */
  143. /*
  144. * flush_kern_cache_all()
  145. *
  146. * Clean and invalidate the entire cache.
  147. */
  148. ENTRY(arm925_flush_kern_cache_all)
  149. mov r2, #VM_EXEC
  150. mov ip, #0
  151. __flush_whole_cache:
  152. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  153. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  154. #else
  155. /* Flush entries in both segments at once, see NOTE1 above */
  156. mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
  157. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  158. subs r3, r3, #1 << 4
  159. bcs 2b @ entries 255 to 0
  160. #endif
  161. tst r2, #VM_EXEC
  162. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  163. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  164. ret lr
  165. /*
  166. * flush_user_cache_range(start, end, flags)
  167. *
  168. * Clean and invalidate a range of cache entries in the
  169. * specified address range.
  170. *
  171. * - start - start address (inclusive)
  172. * - end - end address (exclusive)
  173. * - flags - vm_flags describing address space
  174. */
  175. ENTRY(arm925_flush_user_cache_range)
  176. mov ip, #0
  177. sub r3, r1, r0 @ calculate total size
  178. cmp r3, #CACHE_DLIMIT
  179. bgt __flush_whole_cache
  180. 1: tst r2, #VM_EXEC
  181. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  182. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  183. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  184. add r0, r0, #CACHE_DLINESIZE
  185. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  186. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  187. add r0, r0, #CACHE_DLINESIZE
  188. #else
  189. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  190. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  191. add r0, r0, #CACHE_DLINESIZE
  192. mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
  193. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  194. add r0, r0, #CACHE_DLINESIZE
  195. #endif
  196. cmp r0, r1
  197. blo 1b
  198. tst r2, #VM_EXEC
  199. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  200. ret lr
  201. /*
  202. * coherent_kern_range(start, end)
  203. *
  204. * Ensure coherency between the Icache and the Dcache in the
  205. * region described by start, end. If you have non-snooping
  206. * Harvard caches, you need to implement this function.
  207. *
  208. * - start - virtual start address
  209. * - end - virtual end address
  210. */
  211. ENTRY(arm925_coherent_kern_range)
  212. /* FALLTHROUGH */
  213. /*
  214. * coherent_user_range(start, end)
  215. *
  216. * Ensure coherency between the Icache and the Dcache in the
  217. * region described by start, end. If you have non-snooping
  218. * Harvard caches, you need to implement this function.
  219. *
  220. * - start - virtual start address
  221. * - end - virtual end address
  222. */
  223. ENTRY(arm925_coherent_user_range)
  224. bic r0, r0, #CACHE_DLINESIZE - 1
  225. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  226. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  227. add r0, r0, #CACHE_DLINESIZE
  228. cmp r0, r1
  229. blo 1b
  230. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  231. mov r0, #0
  232. ret lr
  233. /*
  234. * flush_kern_dcache_area(void *addr, size_t size)
  235. *
  236. * Ensure no D cache aliasing occurs, either with itself or
  237. * the I cache
  238. *
  239. * - addr - kernel address
  240. * - size - region size
  241. */
  242. ENTRY(arm925_flush_kern_dcache_area)
  243. add r1, r0, r1
  244. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  245. add r0, r0, #CACHE_DLINESIZE
  246. cmp r0, r1
  247. blo 1b
  248. mov r0, #0
  249. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  250. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  251. ret lr
  252. /*
  253. * dma_inv_range(start, end)
  254. *
  255. * Invalidate (discard) the specified virtual address range.
  256. * May not write back any entries. If 'start' or 'end'
  257. * are not cache line aligned, those lines must be written
  258. * back.
  259. *
  260. * - start - virtual start address
  261. * - end - virtual end address
  262. *
  263. * (same as v4wb)
  264. */
  265. arm925_dma_inv_range:
  266. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  267. tst r0, #CACHE_DLINESIZE - 1
  268. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  269. tst r1, #CACHE_DLINESIZE - 1
  270. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  271. #endif
  272. bic r0, r0, #CACHE_DLINESIZE - 1
  273. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  274. add r0, r0, #CACHE_DLINESIZE
  275. cmp r0, r1
  276. blo 1b
  277. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  278. ret lr
  279. /*
  280. * dma_clean_range(start, end)
  281. *
  282. * Clean the specified virtual address range.
  283. *
  284. * - start - virtual start address
  285. * - end - virtual end address
  286. *
  287. * (same as v4wb)
  288. */
  289. arm925_dma_clean_range:
  290. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  291. bic r0, r0, #CACHE_DLINESIZE - 1
  292. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  293. add r0, r0, #CACHE_DLINESIZE
  294. cmp r0, r1
  295. blo 1b
  296. #endif
  297. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  298. ret lr
  299. /*
  300. * dma_flush_range(start, end)
  301. *
  302. * Clean and invalidate the specified virtual address range.
  303. *
  304. * - start - virtual start address
  305. * - end - virtual end address
  306. */
  307. ENTRY(arm925_dma_flush_range)
  308. bic r0, r0, #CACHE_DLINESIZE - 1
  309. 1:
  310. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  311. mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  312. #else
  313. mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  314. #endif
  315. add r0, r0, #CACHE_DLINESIZE
  316. cmp r0, r1
  317. blo 1b
  318. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  319. ret lr
  320. /*
  321. * dma_map_area(start, size, dir)
  322. * - start - kernel virtual start address
  323. * - size - size of region
  324. * - dir - DMA direction
  325. */
  326. ENTRY(arm925_dma_map_area)
  327. add r1, r1, r0
  328. cmp r2, #DMA_TO_DEVICE
  329. beq arm925_dma_clean_range
  330. bcs arm925_dma_inv_range
  331. b arm925_dma_flush_range
  332. ENDPROC(arm925_dma_map_area)
  333. /*
  334. * dma_unmap_area(start, size, dir)
  335. * - start - kernel virtual start address
  336. * - size - size of region
  337. * - dir - DMA direction
  338. */
  339. ENTRY(arm925_dma_unmap_area)
  340. ret lr
  341. ENDPROC(arm925_dma_unmap_area)
  342. .globl arm925_flush_kern_cache_louis
  343. .equ arm925_flush_kern_cache_louis, arm925_flush_kern_cache_all
  344. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  345. define_cache_functions arm925
  346. ENTRY(cpu_arm925_dcache_clean_area)
  347. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  348. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  349. add r0, r0, #CACHE_DLINESIZE
  350. subs r1, r1, #CACHE_DLINESIZE
  351. bhi 1b
  352. #endif
  353. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  354. ret lr
  355. /* =============================== PageTable ============================== */
  356. /*
  357. * cpu_arm925_switch_mm(pgd)
  358. *
  359. * Set the translation base pointer to be as described by pgd.
  360. *
  361. * pgd: new page tables
  362. */
  363. .align 5
  364. ENTRY(cpu_arm925_switch_mm)
  365. #ifdef CONFIG_MMU
  366. mov ip, #0
  367. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  368. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  369. #else
  370. /* Flush entries in bothe segments at once, see NOTE1 above */
  371. mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
  372. 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
  373. subs r3, r3, #1 << 4
  374. bcs 2b @ entries 255 to 0
  375. #endif
  376. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  377. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  378. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  379. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  380. #endif
  381. ret lr
  382. /*
  383. * cpu_arm925_set_pte_ext(ptep, pte, ext)
  384. *
  385. * Set a PTE and flush it out
  386. */
  387. .align 5
  388. ENTRY(cpu_arm925_set_pte_ext)
  389. #ifdef CONFIG_MMU
  390. armv3_set_pte_ext
  391. mov r0, r0
  392. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  393. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  394. #endif
  395. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  396. #endif /* CONFIG_MMU */
  397. ret lr
  398. .type __arm925_setup, #function
  399. __arm925_setup:
  400. mov r0, #0
  401. /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
  402. orr r0,r0,#1 << 1 @ transparent mode on
  403. mcr p15, 0, r0, c15, c1, 0 @ write TI config register
  404. mov r0, #0
  405. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  406. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  407. #ifdef CONFIG_MMU
  408. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  409. #endif
  410. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  411. mov r0, #4 @ disable write-back on caches explicitly
  412. mcr p15, 7, r0, c15, c0, 0
  413. #endif
  414. adr r5, arm925_crval
  415. ldmia r5, {r5, r6}
  416. mrc p15, 0, r0, c1, c0 @ get control register v4
  417. bic r0, r0, r5
  418. orr r0, r0, r6
  419. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  420. orr r0, r0, #0x4000 @ .1.. .... .... ....
  421. #endif
  422. ret lr
  423. .size __arm925_setup, . - __arm925_setup
  424. /*
  425. * R
  426. * .RVI ZFRS BLDP WCAM
  427. * .011 0001 ..11 1101
  428. *
  429. */
  430. .type arm925_crval, #object
  431. arm925_crval:
  432. crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
  433. __INITDATA
  434. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  435. define_processor_functions arm925, dabort=v4t_early_abort, pabort=legacy_pabort
  436. .section ".rodata"
  437. string cpu_arch_name, "armv4t"
  438. string cpu_elf_name, "v4"
  439. string cpu_arm925_name, "ARM925T"
  440. .align
  441. .section ".proc.info.init", "a"
  442. .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache
  443. .type __\name\()_proc_info,#object
  444. __\name\()_proc_info:
  445. .long \cpu_val
  446. .long \cpu_mask
  447. .long PMD_TYPE_SECT | \
  448. PMD_SECT_CACHEABLE | \
  449. PMD_BIT4 | \
  450. PMD_SECT_AP_WRITE | \
  451. PMD_SECT_AP_READ
  452. .long PMD_TYPE_SECT | \
  453. PMD_BIT4 | \
  454. PMD_SECT_AP_WRITE | \
  455. PMD_SECT_AP_READ
  456. initfn __arm925_setup, __\name\()_proc_info
  457. .long cpu_arch_name
  458. .long cpu_elf_name
  459. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  460. .long cpu_arm925_name
  461. .long arm925_processor_functions
  462. .long v4wbi_tlb_fns
  463. .long v4wb_user_fns
  464. .long arm925_cache_fns
  465. .size __\name\()_proc_info, . - __\name\()_proc_info
  466. .endm
  467. arm925_proc_info arm925, 0x54029250, 0xfffffff0, cpu_arm925_name
  468. arm925_proc_info arm915, 0x54029150, 0xfffffff0, cpu_arm925_name