proc-arm922.S 10 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm922.S: MMU functions for ARM922
  4. *
  5. * Copyright (C) 1999,2000 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * Copyright (C) 2001 Altera Corporation
  8. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  9. *
  10. * These are the low level assembler for performing cache and TLB
  11. * functions on the arm922.
  12. *
  13. * CONFIG_CPU_ARM922_CPU_IDLE -> nohlt
  14. */
  15. #include <linux/linkage.h>
  16. #include <linux/init.h>
  17. #include <linux/pgtable.h>
  18. #include <asm/assembler.h>
  19. #include <asm/hwcap.h>
  20. #include <asm/pgtable-hwdef.h>
  21. #include <asm/page.h>
  22. #include <asm/ptrace.h>
  23. #include "proc-macros.S"
  24. /*
  25. * The size of one data cache line.
  26. */
  27. #define CACHE_DLINESIZE 32
  28. /*
  29. * The number of data cache segments.
  30. */
  31. #define CACHE_DSEGMENTS 4
  32. /*
  33. * The number of lines in a cache segment.
  34. */
  35. #define CACHE_DENTRIES 64
  36. /*
  37. * This is the size at which it becomes more efficient to
  38. * clean the whole cache, rather than using the individual
  39. * cache line maintenance instructions. (I think this should
  40. * be 32768).
  41. */
  42. #define CACHE_DLIMIT 8192
  43. .text
  44. /*
  45. * cpu_arm922_proc_init()
  46. */
  47. ENTRY(cpu_arm922_proc_init)
  48. ret lr
  49. /*
  50. * cpu_arm922_proc_fin()
  51. */
  52. ENTRY(cpu_arm922_proc_fin)
  53. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  54. bic r0, r0, #0x1000 @ ...i............
  55. bic r0, r0, #0x000e @ ............wca.
  56. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  57. ret lr
  58. /*
  59. * cpu_arm922_reset(loc)
  60. *
  61. * Perform a soft reset of the system. Put the CPU into the
  62. * same state as it would be if it had been reset, and branch
  63. * to what would be the reset vector.
  64. *
  65. * loc: location to jump to for soft reset
  66. */
  67. .align 5
  68. .pushsection .idmap.text, "ax"
  69. ENTRY(cpu_arm922_reset)
  70. mov ip, #0
  71. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  72. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  73. #ifdef CONFIG_MMU
  74. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  75. #endif
  76. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  77. bic ip, ip, #0x000f @ ............wcam
  78. bic ip, ip, #0x1100 @ ...i...s........
  79. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  80. ret r0
  81. ENDPROC(cpu_arm922_reset)
  82. .popsection
  83. /*
  84. * cpu_arm922_do_idle()
  85. */
  86. .align 5
  87. ENTRY(cpu_arm922_do_idle)
  88. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  89. ret lr
  90. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  91. /*
  92. * flush_icache_all()
  93. *
  94. * Unconditionally clean and invalidate the entire icache.
  95. */
  96. ENTRY(arm922_flush_icache_all)
  97. mov r0, #0
  98. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  99. ret lr
  100. ENDPROC(arm922_flush_icache_all)
  101. /*
  102. * flush_user_cache_all()
  103. *
  104. * Clean and invalidate all cache entries in a particular
  105. * address space.
  106. */
  107. ENTRY(arm922_flush_user_cache_all)
  108. /* FALLTHROUGH */
  109. /*
  110. * flush_kern_cache_all()
  111. *
  112. * Clean and invalidate the entire cache.
  113. */
  114. ENTRY(arm922_flush_kern_cache_all)
  115. mov r2, #VM_EXEC
  116. mov ip, #0
  117. __flush_whole_cache:
  118. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
  119. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  120. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  121. subs r3, r3, #1 << 26
  122. bcs 2b @ entries 63 to 0
  123. subs r1, r1, #1 << 5
  124. bcs 1b @ segments 7 to 0
  125. tst r2, #VM_EXEC
  126. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  127. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  128. ret lr
  129. /*
  130. * flush_user_cache_range(start, end, flags)
  131. *
  132. * Clean and invalidate a range of cache entries in the
  133. * specified address range.
  134. *
  135. * - start - start address (inclusive)
  136. * - end - end address (exclusive)
  137. * - flags - vm_flags describing address space
  138. */
  139. ENTRY(arm922_flush_user_cache_range)
  140. mov ip, #0
  141. sub r3, r1, r0 @ calculate total size
  142. cmp r3, #CACHE_DLIMIT
  143. bhs __flush_whole_cache
  144. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  145. tst r2, #VM_EXEC
  146. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  147. add r0, r0, #CACHE_DLINESIZE
  148. cmp r0, r1
  149. blo 1b
  150. tst r2, #VM_EXEC
  151. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  152. ret lr
  153. /*
  154. * coherent_kern_range(start, end)
  155. *
  156. * Ensure coherency between the Icache and the Dcache in the
  157. * region described by start, end. If you have non-snooping
  158. * Harvard caches, you need to implement this function.
  159. *
  160. * - start - virtual start address
  161. * - end - virtual end address
  162. */
  163. ENTRY(arm922_coherent_kern_range)
  164. /* FALLTHROUGH */
  165. /*
  166. * coherent_user_range(start, end)
  167. *
  168. * Ensure coherency between the Icache and the Dcache in the
  169. * region described by start, end. If you have non-snooping
  170. * Harvard caches, you need to implement this function.
  171. *
  172. * - start - virtual start address
  173. * - end - virtual end address
  174. */
  175. ENTRY(arm922_coherent_user_range)
  176. bic r0, r0, #CACHE_DLINESIZE - 1
  177. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  178. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  179. add r0, r0, #CACHE_DLINESIZE
  180. cmp r0, r1
  181. blo 1b
  182. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  183. mov r0, #0
  184. ret lr
  185. /*
  186. * flush_kern_dcache_area(void *addr, size_t size)
  187. *
  188. * Ensure no D cache aliasing occurs, either with itself or
  189. * the I cache
  190. *
  191. * - addr - kernel address
  192. * - size - region size
  193. */
  194. ENTRY(arm922_flush_kern_dcache_area)
  195. add r1, r0, r1
  196. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  197. add r0, r0, #CACHE_DLINESIZE
  198. cmp r0, r1
  199. blo 1b
  200. mov r0, #0
  201. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  202. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  203. ret lr
  204. /*
  205. * dma_inv_range(start, end)
  206. *
  207. * Invalidate (discard) the specified virtual address range.
  208. * May not write back any entries. If 'start' or 'end'
  209. * are not cache line aligned, those lines must be written
  210. * back.
  211. *
  212. * - start - virtual start address
  213. * - end - virtual end address
  214. *
  215. * (same as v4wb)
  216. */
  217. arm922_dma_inv_range:
  218. tst r0, #CACHE_DLINESIZE - 1
  219. bic r0, r0, #CACHE_DLINESIZE - 1
  220. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  221. tst r1, #CACHE_DLINESIZE - 1
  222. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  223. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  224. add r0, r0, #CACHE_DLINESIZE
  225. cmp r0, r1
  226. blo 1b
  227. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  228. ret lr
  229. /*
  230. * dma_clean_range(start, end)
  231. *
  232. * Clean the specified virtual address range.
  233. *
  234. * - start - virtual start address
  235. * - end - virtual end address
  236. *
  237. * (same as v4wb)
  238. */
  239. arm922_dma_clean_range:
  240. bic r0, r0, #CACHE_DLINESIZE - 1
  241. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  242. add r0, r0, #CACHE_DLINESIZE
  243. cmp r0, r1
  244. blo 1b
  245. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  246. ret lr
  247. /*
  248. * dma_flush_range(start, end)
  249. *
  250. * Clean and invalidate the specified virtual address range.
  251. *
  252. * - start - virtual start address
  253. * - end - virtual end address
  254. */
  255. ENTRY(arm922_dma_flush_range)
  256. bic r0, r0, #CACHE_DLINESIZE - 1
  257. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  258. add r0, r0, #CACHE_DLINESIZE
  259. cmp r0, r1
  260. blo 1b
  261. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  262. ret lr
  263. /*
  264. * dma_map_area(start, size, dir)
  265. * - start - kernel virtual start address
  266. * - size - size of region
  267. * - dir - DMA direction
  268. */
  269. ENTRY(arm922_dma_map_area)
  270. add r1, r1, r0
  271. cmp r2, #DMA_TO_DEVICE
  272. beq arm922_dma_clean_range
  273. bcs arm922_dma_inv_range
  274. b arm922_dma_flush_range
  275. ENDPROC(arm922_dma_map_area)
  276. /*
  277. * dma_unmap_area(start, size, dir)
  278. * - start - kernel virtual start address
  279. * - size - size of region
  280. * - dir - DMA direction
  281. */
  282. ENTRY(arm922_dma_unmap_area)
  283. ret lr
  284. ENDPROC(arm922_dma_unmap_area)
  285. .globl arm922_flush_kern_cache_louis
  286. .equ arm922_flush_kern_cache_louis, arm922_flush_kern_cache_all
  287. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  288. define_cache_functions arm922
  289. #endif
  290. ENTRY(cpu_arm922_dcache_clean_area)
  291. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  292. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  293. add r0, r0, #CACHE_DLINESIZE
  294. subs r1, r1, #CACHE_DLINESIZE
  295. bhi 1b
  296. #endif
  297. ret lr
  298. /* =============================== PageTable ============================== */
  299. /*
  300. * cpu_arm922_switch_mm(pgd)
  301. *
  302. * Set the translation base pointer to be as described by pgd.
  303. *
  304. * pgd: new page tables
  305. */
  306. .align 5
  307. ENTRY(cpu_arm922_switch_mm)
  308. #ifdef CONFIG_MMU
  309. mov ip, #0
  310. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  311. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  312. #else
  313. @ && 'Clean & Invalidate whole DCache'
  314. @ && Re-written to use Index Ops.
  315. @ && Uses registers r1, r3 and ip
  316. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 4 segments
  317. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  318. 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
  319. subs r3, r3, #1 << 26
  320. bcs 2b @ entries 63 to 0
  321. subs r1, r1, #1 << 5
  322. bcs 1b @ segments 7 to 0
  323. #endif
  324. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  325. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  326. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  327. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  328. #endif
  329. ret lr
  330. /*
  331. * cpu_arm922_set_pte_ext(ptep, pte, ext)
  332. *
  333. * Set a PTE and flush it out
  334. */
  335. .align 5
  336. ENTRY(cpu_arm922_set_pte_ext)
  337. #ifdef CONFIG_MMU
  338. armv3_set_pte_ext
  339. mov r0, r0
  340. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  341. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  342. #endif /* CONFIG_MMU */
  343. ret lr
  344. .type __arm922_setup, #function
  345. __arm922_setup:
  346. mov r0, #0
  347. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  348. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  349. #ifdef CONFIG_MMU
  350. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  351. #endif
  352. adr r5, arm922_crval
  353. ldmia r5, {r5, r6}
  354. mrc p15, 0, r0, c1, c0 @ get control register v4
  355. bic r0, r0, r5
  356. orr r0, r0, r6
  357. ret lr
  358. .size __arm922_setup, . - __arm922_setup
  359. /*
  360. * R
  361. * .RVI ZFRS BLDP WCAM
  362. * ..11 0001 ..11 0101
  363. *
  364. */
  365. .type arm922_crval, #object
  366. arm922_crval:
  367. crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
  368. __INITDATA
  369. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  370. define_processor_functions arm922, dabort=v4t_early_abort, pabort=legacy_pabort
  371. .section ".rodata"
  372. string cpu_arch_name, "armv4t"
  373. string cpu_elf_name, "v4"
  374. string cpu_arm922_name, "ARM922T"
  375. .align
  376. .section ".proc.info.init", "a"
  377. .type __arm922_proc_info,#object
  378. __arm922_proc_info:
  379. .long 0x41009220
  380. .long 0xff00fff0
  381. .long PMD_TYPE_SECT | \
  382. PMD_SECT_BUFFERABLE | \
  383. PMD_SECT_CACHEABLE | \
  384. PMD_BIT4 | \
  385. PMD_SECT_AP_WRITE | \
  386. PMD_SECT_AP_READ
  387. .long PMD_TYPE_SECT | \
  388. PMD_BIT4 | \
  389. PMD_SECT_AP_WRITE | \
  390. PMD_SECT_AP_READ
  391. initfn __arm922_setup, __arm922_proc_info
  392. .long cpu_arch_name
  393. .long cpu_elf_name
  394. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  395. .long cpu_arm922_name
  396. .long arm922_processor_functions
  397. .long v4wbi_tlb_fns
  398. .long v4wb_user_fns
  399. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  400. .long arm922_cache_fns
  401. #else
  402. .long v4wt_cache_fns
  403. #endif
  404. .size __arm922_proc_info, . - __arm922_proc_info