proc-arm920.S 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920
  4. *
  5. * Copyright (C) 1999,2000 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  8. *
  9. * These are the low level assembler for performing cache and TLB
  10. * functions on the arm920.
  11. *
  12. * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/init.h>
  16. #include <linux/pgtable.h>
  17. #include <asm/assembler.h>
  18. #include <asm/hwcap.h>
  19. #include <asm/pgtable-hwdef.h>
  20. #include <asm/page.h>
  21. #include <asm/ptrace.h>
  22. #include "proc-macros.S"
  23. /*
  24. * The size of one data cache line.
  25. */
  26. #define CACHE_DLINESIZE 32
  27. /*
  28. * The number of data cache segments.
  29. */
  30. #define CACHE_DSEGMENTS 8
  31. /*
  32. * The number of lines in a cache segment.
  33. */
  34. #define CACHE_DENTRIES 64
  35. /*
  36. * This is the size at which it becomes more efficient to
  37. * clean the whole cache, rather than using the individual
  38. * cache line maintenance instructions.
  39. */
  40. #define CACHE_DLIMIT 65536
  41. .text
  42. /*
  43. * cpu_arm920_proc_init()
  44. */
  45. ENTRY(cpu_arm920_proc_init)
  46. ret lr
  47. /*
  48. * cpu_arm920_proc_fin()
  49. */
  50. ENTRY(cpu_arm920_proc_fin)
  51. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  52. bic r0, r0, #0x1000 @ ...i............
  53. bic r0, r0, #0x000e @ ............wca.
  54. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  55. ret lr
  56. /*
  57. * cpu_arm920_reset(loc)
  58. *
  59. * Perform a soft reset of the system. Put the CPU into the
  60. * same state as it would be if it had been reset, and branch
  61. * to what would be the reset vector.
  62. *
  63. * loc: location to jump to for soft reset
  64. */
  65. .align 5
  66. .pushsection .idmap.text, "ax"
  67. ENTRY(cpu_arm920_reset)
  68. mov ip, #0
  69. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  70. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  71. #ifdef CONFIG_MMU
  72. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  73. #endif
  74. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  75. bic ip, ip, #0x000f @ ............wcam
  76. bic ip, ip, #0x1100 @ ...i...s........
  77. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  78. ret r0
  79. ENDPROC(cpu_arm920_reset)
  80. .popsection
  81. /*
  82. * cpu_arm920_do_idle()
  83. */
  84. .align 5
  85. ENTRY(cpu_arm920_do_idle)
  86. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  87. ret lr
  88. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  89. /*
  90. * flush_icache_all()
  91. *
  92. * Unconditionally clean and invalidate the entire icache.
  93. */
  94. ENTRY(arm920_flush_icache_all)
  95. mov r0, #0
  96. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  97. ret lr
  98. ENDPROC(arm920_flush_icache_all)
  99. /*
  100. * flush_user_cache_all()
  101. *
  102. * Invalidate all cache entries in a particular address
  103. * space.
  104. */
  105. ENTRY(arm920_flush_user_cache_all)
  106. /* FALLTHROUGH */
  107. /*
  108. * flush_kern_cache_all()
  109. *
  110. * Clean and invalidate the entire cache.
  111. */
  112. ENTRY(arm920_flush_kern_cache_all)
  113. mov r2, #VM_EXEC
  114. mov ip, #0
  115. __flush_whole_cache:
  116. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
  117. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  118. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  119. subs r3, r3, #1 << 26
  120. bcs 2b @ entries 63 to 0
  121. subs r1, r1, #1 << 5
  122. bcs 1b @ segments 7 to 0
  123. tst r2, #VM_EXEC
  124. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  125. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  126. ret lr
  127. /*
  128. * flush_user_cache_range(start, end, flags)
  129. *
  130. * Invalidate a range of cache entries in the specified
  131. * address space.
  132. *
  133. * - start - start address (inclusive)
  134. * - end - end address (exclusive)
  135. * - flags - vm_flags for address space
  136. */
  137. ENTRY(arm920_flush_user_cache_range)
  138. mov ip, #0
  139. sub r3, r1, r0 @ calculate total size
  140. cmp r3, #CACHE_DLIMIT
  141. bhs __flush_whole_cache
  142. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  143. tst r2, #VM_EXEC
  144. mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
  145. add r0, r0, #CACHE_DLINESIZE
  146. cmp r0, r1
  147. blo 1b
  148. tst r2, #VM_EXEC
  149. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  150. ret lr
  151. /*
  152. * coherent_kern_range(start, end)
  153. *
  154. * Ensure coherency between the Icache and the Dcache in the
  155. * region described by start, end. If you have non-snooping
  156. * Harvard caches, you need to implement this function.
  157. *
  158. * - start - virtual start address
  159. * - end - virtual end address
  160. */
  161. ENTRY(arm920_coherent_kern_range)
  162. /* FALLTHROUGH */
  163. /*
  164. * coherent_user_range(start, end)
  165. *
  166. * Ensure coherency between the Icache and the Dcache in the
  167. * region described by start, end. If you have non-snooping
  168. * Harvard caches, you need to implement this function.
  169. *
  170. * - start - virtual start address
  171. * - end - virtual end address
  172. */
  173. ENTRY(arm920_coherent_user_range)
  174. bic r0, r0, #CACHE_DLINESIZE - 1
  175. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  176. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  177. add r0, r0, #CACHE_DLINESIZE
  178. cmp r0, r1
  179. blo 1b
  180. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  181. mov r0, #0
  182. ret lr
  183. /*
  184. * flush_kern_dcache_area(void *addr, size_t size)
  185. *
  186. * Ensure no D cache aliasing occurs, either with itself or
  187. * the I cache
  188. *
  189. * - addr - kernel address
  190. * - size - region size
  191. */
  192. ENTRY(arm920_flush_kern_dcache_area)
  193. add r1, r0, r1
  194. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  195. add r0, r0, #CACHE_DLINESIZE
  196. cmp r0, r1
  197. blo 1b
  198. mov r0, #0
  199. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  200. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  201. ret lr
  202. /*
  203. * dma_inv_range(start, end)
  204. *
  205. * Invalidate (discard) the specified virtual address range.
  206. * May not write back any entries. If 'start' or 'end'
  207. * are not cache line aligned, those lines must be written
  208. * back.
  209. *
  210. * - start - virtual start address
  211. * - end - virtual end address
  212. *
  213. * (same as v4wb)
  214. */
  215. arm920_dma_inv_range:
  216. tst r0, #CACHE_DLINESIZE - 1
  217. bic r0, r0, #CACHE_DLINESIZE - 1
  218. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  219. tst r1, #CACHE_DLINESIZE - 1
  220. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  221. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  222. add r0, r0, #CACHE_DLINESIZE
  223. cmp r0, r1
  224. blo 1b
  225. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  226. ret lr
  227. /*
  228. * dma_clean_range(start, end)
  229. *
  230. * Clean the specified virtual address range.
  231. *
  232. * - start - virtual start address
  233. * - end - virtual end address
  234. *
  235. * (same as v4wb)
  236. */
  237. arm920_dma_clean_range:
  238. bic r0, r0, #CACHE_DLINESIZE - 1
  239. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  240. add r0, r0, #CACHE_DLINESIZE
  241. cmp r0, r1
  242. blo 1b
  243. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  244. ret lr
  245. /*
  246. * dma_flush_range(start, end)
  247. *
  248. * Clean and invalidate the specified virtual address range.
  249. *
  250. * - start - virtual start address
  251. * - end - virtual end address
  252. */
  253. ENTRY(arm920_dma_flush_range)
  254. bic r0, r0, #CACHE_DLINESIZE - 1
  255. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  256. add r0, r0, #CACHE_DLINESIZE
  257. cmp r0, r1
  258. blo 1b
  259. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  260. ret lr
  261. /*
  262. * dma_map_area(start, size, dir)
  263. * - start - kernel virtual start address
  264. * - size - size of region
  265. * - dir - DMA direction
  266. */
  267. ENTRY(arm920_dma_map_area)
  268. add r1, r1, r0
  269. cmp r2, #DMA_TO_DEVICE
  270. beq arm920_dma_clean_range
  271. bcs arm920_dma_inv_range
  272. b arm920_dma_flush_range
  273. ENDPROC(arm920_dma_map_area)
  274. /*
  275. * dma_unmap_area(start, size, dir)
  276. * - start - kernel virtual start address
  277. * - size - size of region
  278. * - dir - DMA direction
  279. */
  280. ENTRY(arm920_dma_unmap_area)
  281. ret lr
  282. ENDPROC(arm920_dma_unmap_area)
  283. .globl arm920_flush_kern_cache_louis
  284. .equ arm920_flush_kern_cache_louis, arm920_flush_kern_cache_all
  285. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  286. define_cache_functions arm920
  287. #endif
  288. ENTRY(cpu_arm920_dcache_clean_area)
  289. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  290. add r0, r0, #CACHE_DLINESIZE
  291. subs r1, r1, #CACHE_DLINESIZE
  292. bhi 1b
  293. ret lr
  294. /* =============================== PageTable ============================== */
  295. /*
  296. * cpu_arm920_switch_mm(pgd)
  297. *
  298. * Set the translation base pointer to be as described by pgd.
  299. *
  300. * pgd: new page tables
  301. */
  302. .align 5
  303. ENTRY(cpu_arm920_switch_mm)
  304. #ifdef CONFIG_MMU
  305. mov ip, #0
  306. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  307. mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
  308. #else
  309. @ && 'Clean & Invalidate whole DCache'
  310. @ && Re-written to use Index Ops.
  311. @ && Uses registers r1, r3 and ip
  312. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments
  313. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  314. 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
  315. subs r3, r3, #1 << 26
  316. bcs 2b @ entries 63 to 0
  317. subs r1, r1, #1 << 5
  318. bcs 1b @ segments 7 to 0
  319. #endif
  320. mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
  321. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  322. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  323. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  324. #endif
  325. ret lr
  326. /*
  327. * cpu_arm920_set_pte(ptep, pte, ext)
  328. *
  329. * Set a PTE and flush it out
  330. */
  331. .align 5
  332. ENTRY(cpu_arm920_set_pte_ext)
  333. #ifdef CONFIG_MMU
  334. armv3_set_pte_ext
  335. mov r0, r0
  336. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  337. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  338. #endif
  339. ret lr
  340. /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
  341. .globl cpu_arm920_suspend_size
  342. .equ cpu_arm920_suspend_size, 4 * 3
  343. #ifdef CONFIG_ARM_CPU_SUSPEND
  344. ENTRY(cpu_arm920_do_suspend)
  345. stmfd sp!, {r4 - r6, lr}
  346. mrc p15, 0, r4, c13, c0, 0 @ PID
  347. mrc p15, 0, r5, c3, c0, 0 @ Domain ID
  348. mrc p15, 0, r6, c1, c0, 0 @ Control register
  349. stmia r0, {r4 - r6}
  350. ldmfd sp!, {r4 - r6, pc}
  351. ENDPROC(cpu_arm920_do_suspend)
  352. ENTRY(cpu_arm920_do_resume)
  353. mov ip, #0
  354. mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
  355. mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
  356. ldmia r0, {r4 - r6}
  357. mcr p15, 0, r4, c13, c0, 0 @ PID
  358. mcr p15, 0, r5, c3, c0, 0 @ Domain ID
  359. mcr p15, 0, r1, c2, c0, 0 @ TTB address
  360. mov r0, r6 @ control register
  361. b cpu_resume_mmu
  362. ENDPROC(cpu_arm920_do_resume)
  363. #endif
  364. .type __arm920_setup, #function
  365. __arm920_setup:
  366. mov r0, #0
  367. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  368. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  369. #ifdef CONFIG_MMU
  370. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  371. #endif
  372. adr r5, arm920_crval
  373. ldmia r5, {r5, r6}
  374. mrc p15, 0, r0, c1, c0 @ get control register v4
  375. bic r0, r0, r5
  376. orr r0, r0, r6
  377. ret lr
  378. .size __arm920_setup, . - __arm920_setup
  379. /*
  380. * R
  381. * .RVI ZFRS BLDP WCAM
  382. * ..11 0001 ..11 0101
  383. *
  384. */
  385. .type arm920_crval, #object
  386. arm920_crval:
  387. crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
  388. __INITDATA
  389. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  390. define_processor_functions arm920, dabort=v4t_early_abort, pabort=legacy_pabort, suspend=1
  391. .section ".rodata"
  392. string cpu_arch_name, "armv4t"
  393. string cpu_elf_name, "v4"
  394. string cpu_arm920_name, "ARM920T"
  395. .align
  396. .section ".proc.info.init", "a"
  397. .type __arm920_proc_info,#object
  398. __arm920_proc_info:
  399. .long 0x41009200
  400. .long 0xff00fff0
  401. .long PMD_TYPE_SECT | \
  402. PMD_SECT_BUFFERABLE | \
  403. PMD_SECT_CACHEABLE | \
  404. PMD_BIT4 | \
  405. PMD_SECT_AP_WRITE | \
  406. PMD_SECT_AP_READ
  407. .long PMD_TYPE_SECT | \
  408. PMD_BIT4 | \
  409. PMD_SECT_AP_WRITE | \
  410. PMD_SECT_AP_READ
  411. initfn __arm920_setup, __arm920_proc_info
  412. .long cpu_arch_name
  413. .long cpu_elf_name
  414. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  415. .long cpu_arm920_name
  416. .long arm920_processor_functions
  417. .long v4wbi_tlb_fns
  418. .long v4wb_user_fns
  419. #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
  420. .long arm920_cache_fns
  421. #else
  422. .long v4wt_cache_fns
  423. #endif
  424. .size __arm920_proc_info, . - __arm920_proc_info