proc-arm740.S 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * linux/arch/arm/mm/arm740.S: utility functions for ARM740
  4. *
  5. * Copyright (C) 2004-2006 Hyok S. Choi ([email protected])
  6. */
  7. #include <linux/linkage.h>
  8. #include <linux/init.h>
  9. #include <linux/pgtable.h>
  10. #include <asm/assembler.h>
  11. #include <asm/asm-offsets.h>
  12. #include <asm/hwcap.h>
  13. #include <asm/pgtable-hwdef.h>
  14. #include <asm/ptrace.h>
  15. #include "proc-macros.S"
  16. .text
  17. /*
  18. * cpu_arm740_proc_init()
  19. * cpu_arm740_do_idle()
  20. * cpu_arm740_dcache_clean_area()
  21. * cpu_arm740_switch_mm()
  22. *
  23. * These are not required.
  24. */
  25. ENTRY(cpu_arm740_proc_init)
  26. ENTRY(cpu_arm740_do_idle)
  27. ENTRY(cpu_arm740_dcache_clean_area)
  28. ENTRY(cpu_arm740_switch_mm)
  29. ret lr
  30. /*
  31. * cpu_arm740_proc_fin()
  32. */
  33. ENTRY(cpu_arm740_proc_fin)
  34. mrc p15, 0, r0, c1, c0, 0
  35. bic r0, r0, #0x3f000000 @ bank/f/lock/s
  36. bic r0, r0, #0x0000000c @ w-buffer/cache
  37. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  38. ret lr
  39. /*
  40. * cpu_arm740_reset(loc)
  41. * Params : r0 = address to jump to
  42. * Notes : This sets up everything for a reset
  43. */
  44. .pushsection .idmap.text, "ax"
  45. ENTRY(cpu_arm740_reset)
  46. mov ip, #0
  47. mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
  48. mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
  49. bic ip, ip, #0x0000000c @ ............wc..
  50. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  51. ret r0
  52. ENDPROC(cpu_arm740_reset)
  53. .popsection
  54. .type __arm740_setup, #function
  55. __arm740_setup:
  56. mov r0, #0
  57. mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
  58. mcr p15, 0, r0, c6, c3 @ disable area 3~7
  59. mcr p15, 0, r0, c6, c4
  60. mcr p15, 0, r0, c6, c5
  61. mcr p15, 0, r0, c6, c6
  62. mcr p15, 0, r0, c6, c7
  63. mov r0, #0x0000003F @ base = 0, size = 4GB
  64. mcr p15, 0, r0, c6, c0 @ set area 0, default
  65. ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  66. ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
  67. mov r4, #10 @ 11 is the minimum (4KB)
  68. 1: add r4, r4, #1 @ area size *= 2
  69. movs r3, r3, lsr #1
  70. bne 1b @ count not zero r-shift
  71. orr r0, r0, r4, lsl #1 @ the area register value
  72. orr r0, r0, #1 @ set enable bit
  73. mcr p15, 0, r0, c6, c1 @ set area 1, RAM
  74. ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  75. ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
  76. cmp r3, #0
  77. moveq r0, #0
  78. beq 2f
  79. mov r4, #10 @ 11 is the minimum (4KB)
  80. 1: add r4, r4, #1 @ area size *= 2
  81. movs r3, r3, lsr #1
  82. bne 1b @ count not zero r-shift
  83. orr r0, r0, r4, lsl #1 @ the area register value
  84. orr r0, r0, #1 @ set enable bit
  85. 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
  86. mov r0, #0x06
  87. mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
  88. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  89. mov r0, #0x00 @ disable whole write buffer
  90. #else
  91. mov r0, #0x02 @ Region 1 write bufferred
  92. #endif
  93. mcr p15, 0, r0, c3, c0
  94. mov r0, #0x10000
  95. sub r0, r0, #1 @ r0 = 0xffff
  96. mcr p15, 0, r0, c5, c0 @ all read/write access
  97. mrc p15, 0, r0, c1, c0 @ get control register
  98. bic r0, r0, #0x3F000000 @ set to standard caching mode
  99. @ need some benchmark
  100. orr r0, r0, #0x0000000d @ MPU/Cache/WB
  101. ret lr
  102. .size __arm740_setup, . - __arm740_setup
  103. __INITDATA
  104. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  105. define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
  106. .section ".rodata"
  107. string cpu_arch_name, "armv4"
  108. string cpu_elf_name, "v4"
  109. string cpu_arm740_name, "ARM740T"
  110. .align
  111. .section ".proc.info.init", "a"
  112. .type __arm740_proc_info,#object
  113. __arm740_proc_info:
  114. .long 0x41807400
  115. .long 0xfffffff0
  116. .long 0
  117. .long 0
  118. initfn __arm740_setup, __arm740_proc_info
  119. .long cpu_arch_name
  120. .long cpu_elf_name
  121. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
  122. .long cpu_arm740_name
  123. .long arm740_processor_functions
  124. .long 0
  125. .long 0
  126. .long v4_cache_fns @ cache model
  127. .size __arm740_proc_info, . - __arm740_proc_info