proc-arm720.S 5.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
  4. *
  5. * Copyright (C) 2000 Steve Hill ([email protected])
  6. * Rob Scott ([email protected])
  7. * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
  8. * hacked for non-paged-MM by Hyok S. Choi, 2004.
  9. *
  10. * These are the low level assembler for performing cache and TLB
  11. * functions on the ARM720T. The ARM720T has a writethrough IDC
  12. * cache, so we don't need to clean it.
  13. *
  14. * Changelog:
  15. * 05-09-2000 SJH Created by moving 720 specific functions
  16. * out of 'proc-arm6,7.S' per RMK discussion
  17. * 07-25-2000 SJH Added idle function.
  18. * 08-25-2000 DBS Updated for integration of ARM Ltd version.
  19. * 04-20-2004 HSC modified for non-paged memory management mode.
  20. */
  21. #include <linux/linkage.h>
  22. #include <linux/init.h>
  23. #include <linux/pgtable.h>
  24. #include <asm/assembler.h>
  25. #include <asm/asm-offsets.h>
  26. #include <asm/hwcap.h>
  27. #include <asm/pgtable-hwdef.h>
  28. #include <asm/ptrace.h>
  29. #include "proc-macros.S"
  30. /*
  31. * Function: arm720_proc_init (void)
  32. * : arm720_proc_fin (void)
  33. *
  34. * Notes : This processor does not require these
  35. */
  36. ENTRY(cpu_arm720_dcache_clean_area)
  37. ENTRY(cpu_arm720_proc_init)
  38. ret lr
  39. ENTRY(cpu_arm720_proc_fin)
  40. mrc p15, 0, r0, c1, c0, 0
  41. bic r0, r0, #0x1000 @ ...i............
  42. bic r0, r0, #0x000e @ ............wca.
  43. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  44. ret lr
  45. /*
  46. * Function: arm720_proc_do_idle(void)
  47. * Params : r0 = unused
  48. * Purpose : put the processor in proper idle mode
  49. */
  50. ENTRY(cpu_arm720_do_idle)
  51. ret lr
  52. /*
  53. * Function: arm720_switch_mm(unsigned long pgd_phys)
  54. * Params : pgd_phys Physical address of page table
  55. * Purpose : Perform a task switch, saving the old process' state and restoring
  56. * the new.
  57. */
  58. ENTRY(cpu_arm720_switch_mm)
  59. #ifdef CONFIG_MMU
  60. mov r1, #0
  61. mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
  62. mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
  63. mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
  64. #endif
  65. ret lr
  66. /*
  67. * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
  68. * Params : r0 = Address to set
  69. * : r1 = value to set
  70. * Purpose : Set a PTE and flush it out of any WB cache
  71. */
  72. .align 5
  73. ENTRY(cpu_arm720_set_pte_ext)
  74. #ifdef CONFIG_MMU
  75. armv3_set_pte_ext wc_disable=0
  76. #endif
  77. ret lr
  78. /*
  79. * Function: arm720_reset
  80. * Params : r0 = address to jump to
  81. * Notes : This sets up everything for a reset
  82. */
  83. .pushsection .idmap.text, "ax"
  84. ENTRY(cpu_arm720_reset)
  85. mov ip, #0
  86. mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
  87. #ifdef CONFIG_MMU
  88. mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
  89. #endif
  90. mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
  91. bic ip, ip, #0x000f @ ............wcam
  92. bic ip, ip, #0x2100 @ ..v....s........
  93. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  94. ret r0
  95. ENDPROC(cpu_arm720_reset)
  96. .popsection
  97. .type __arm710_setup, #function
  98. __arm710_setup:
  99. mov r0, #0
  100. mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
  101. #ifdef CONFIG_MMU
  102. mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
  103. #endif
  104. mrc p15, 0, r0, c1, c0 @ get control register
  105. ldr r5, arm710_cr1_clear
  106. bic r0, r0, r5
  107. ldr r5, arm710_cr1_set
  108. orr r0, r0, r5
  109. ret lr @ __ret (head.S)
  110. .size __arm710_setup, . - __arm710_setup
  111. /*
  112. * R
  113. * .RVI ZFRS BLDP WCAM
  114. * .... 0001 ..11 1101
  115. *
  116. */
  117. .type arm710_cr1_clear, #object
  118. .type arm710_cr1_set, #object
  119. arm710_cr1_clear:
  120. .word 0x0f3f
  121. arm710_cr1_set:
  122. .word 0x013d
  123. .type __arm720_setup, #function
  124. __arm720_setup:
  125. mov r0, #0
  126. mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
  127. #ifdef CONFIG_MMU
  128. mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
  129. #endif
  130. adr r5, arm720_crval
  131. ldmia r5, {r5, r6}
  132. mrc p15, 0, r0, c1, c0 @ get control register
  133. bic r0, r0, r5
  134. orr r0, r0, r6
  135. ret lr @ __ret (head.S)
  136. .size __arm720_setup, . - __arm720_setup
  137. /*
  138. * R
  139. * .RVI ZFRS BLDP WCAM
  140. * ..1. 1001 ..11 1101
  141. *
  142. */
  143. .type arm720_crval, #object
  144. arm720_crval:
  145. crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
  146. __INITDATA
  147. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  148. define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort
  149. .section ".rodata"
  150. string cpu_arch_name, "armv4t"
  151. string cpu_elf_name, "v4"
  152. string cpu_arm710_name, "ARM710T"
  153. string cpu_arm720_name, "ARM720T"
  154. .align
  155. /*
  156. * See <asm/procinfo.h> for a definition of this structure.
  157. */
  158. .section ".proc.info.init", "a"
  159. .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req
  160. .type __\name\()_proc_info,#object
  161. __\name\()_proc_info:
  162. .long \cpu_val
  163. .long \cpu_mask
  164. .long PMD_TYPE_SECT | \
  165. PMD_SECT_BUFFERABLE | \
  166. PMD_SECT_CACHEABLE | \
  167. PMD_BIT4 | \
  168. PMD_SECT_AP_WRITE | \
  169. PMD_SECT_AP_READ
  170. .long PMD_TYPE_SECT | \
  171. PMD_BIT4 | \
  172. PMD_SECT_AP_WRITE | \
  173. PMD_SECT_AP_READ
  174. initfn \cpu_flush, __\name\()_proc_info @ cpu_flush
  175. .long cpu_arch_name @ arch_name
  176. .long cpu_elf_name @ elf_name
  177. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap
  178. .long \cpu_name
  179. .long arm720_processor_functions
  180. .long v4_tlb_fns
  181. .long v4wt_user_fns
  182. .long v4_cache_fns
  183. .size __\name\()_proc_info, . - __\name\()_proc_info
  184. .endm
  185. arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup
  186. arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup