proc-arm1026.S 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463
  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
  4. *
  5. * Copyright (C) 2000 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  8. *
  9. * These are the low level assembler for performing cache and TLB
  10. * functions on the ARM1026EJ-S.
  11. */
  12. #include <linux/linkage.h>
  13. #include <linux/init.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/assembler.h>
  16. #include <asm/asm-offsets.h>
  17. #include <asm/hwcap.h>
  18. #include <asm/pgtable-hwdef.h>
  19. #include <asm/ptrace.h>
  20. #include "proc-macros.S"
  21. /*
  22. * This is the maximum size of an area which will be invalidated
  23. * using the single invalidate entry instructions. Anything larger
  24. * than this, and we go for the whole cache.
  25. *
  26. * This value should be chosen such that we choose the cheapest
  27. * alternative.
  28. */
  29. #define MAX_AREA_SIZE 32768
  30. /*
  31. * The size of one data cache line.
  32. */
  33. #define CACHE_DLINESIZE 32
  34. /*
  35. * The number of data cache segments.
  36. */
  37. #define CACHE_DSEGMENTS 16
  38. /*
  39. * The number of lines in a cache segment.
  40. */
  41. #define CACHE_DENTRIES 64
  42. /*
  43. * This is the size at which it becomes more efficient to
  44. * clean the whole cache, rather than using the individual
  45. * cache line maintenance instructions.
  46. */
  47. #define CACHE_DLIMIT 32768
  48. .text
  49. /*
  50. * cpu_arm1026_proc_init()
  51. */
  52. ENTRY(cpu_arm1026_proc_init)
  53. ret lr
  54. /*
  55. * cpu_arm1026_proc_fin()
  56. */
  57. ENTRY(cpu_arm1026_proc_fin)
  58. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  59. bic r0, r0, #0x1000 @ ...i............
  60. bic r0, r0, #0x000e @ ............wca.
  61. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  62. ret lr
  63. /*
  64. * cpu_arm1026_reset(loc)
  65. *
  66. * Perform a soft reset of the system. Put the CPU into the
  67. * same state as it would be if it had been reset, and branch
  68. * to what would be the reset vector.
  69. *
  70. * loc: location to jump to for soft reset
  71. */
  72. .align 5
  73. .pushsection .idmap.text, "ax"
  74. ENTRY(cpu_arm1026_reset)
  75. mov ip, #0
  76. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  77. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  78. #ifdef CONFIG_MMU
  79. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  80. #endif
  81. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  82. bic ip, ip, #0x000f @ ............wcam
  83. bic ip, ip, #0x1100 @ ...i...s........
  84. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  85. ret r0
  86. ENDPROC(cpu_arm1026_reset)
  87. .popsection
  88. /*
  89. * cpu_arm1026_do_idle()
  90. */
  91. .align 5
  92. ENTRY(cpu_arm1026_do_idle)
  93. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  94. ret lr
  95. /* ================================= CACHE ================================ */
  96. .align 5
  97. /*
  98. * flush_icache_all()
  99. *
  100. * Unconditionally clean and invalidate the entire icache.
  101. */
  102. ENTRY(arm1026_flush_icache_all)
  103. #ifndef CONFIG_CPU_ICACHE_DISABLE
  104. mov r0, #0
  105. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  106. #endif
  107. ret lr
  108. ENDPROC(arm1026_flush_icache_all)
  109. /*
  110. * flush_user_cache_all()
  111. *
  112. * Invalidate all cache entries in a particular address
  113. * space.
  114. */
  115. ENTRY(arm1026_flush_user_cache_all)
  116. /* FALLTHROUGH */
  117. /*
  118. * flush_kern_cache_all()
  119. *
  120. * Clean and invalidate the entire cache.
  121. */
  122. ENTRY(arm1026_flush_kern_cache_all)
  123. mov r2, #VM_EXEC
  124. mov ip, #0
  125. __flush_whole_cache:
  126. #ifndef CONFIG_CPU_DCACHE_DISABLE
  127. 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
  128. bne 1b
  129. #endif
  130. tst r2, #VM_EXEC
  131. #ifndef CONFIG_CPU_ICACHE_DISABLE
  132. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  133. #endif
  134. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  135. ret lr
  136. /*
  137. * flush_user_cache_range(start, end, flags)
  138. *
  139. * Invalidate a range of cache entries in the specified
  140. * address space.
  141. *
  142. * - start - start address (inclusive)
  143. * - end - end address (exclusive)
  144. * - flags - vm_flags for this space
  145. */
  146. ENTRY(arm1026_flush_user_cache_range)
  147. mov ip, #0
  148. sub r3, r1, r0 @ calculate total size
  149. cmp r3, #CACHE_DLIMIT
  150. bhs __flush_whole_cache
  151. #ifndef CONFIG_CPU_DCACHE_DISABLE
  152. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  153. add r0, r0, #CACHE_DLINESIZE
  154. cmp r0, r1
  155. blo 1b
  156. #endif
  157. tst r2, #VM_EXEC
  158. #ifndef CONFIG_CPU_ICACHE_DISABLE
  159. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  160. #endif
  161. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  162. ret lr
  163. /*
  164. * coherent_kern_range(start, end)
  165. *
  166. * Ensure coherency between the Icache and the Dcache in the
  167. * region described by start. If you have non-snooping
  168. * Harvard caches, you need to implement this function.
  169. *
  170. * - start - virtual start address
  171. * - end - virtual end address
  172. */
  173. ENTRY(arm1026_coherent_kern_range)
  174. /* FALLTHROUGH */
  175. /*
  176. * coherent_user_range(start, end)
  177. *
  178. * Ensure coherency between the Icache and the Dcache in the
  179. * region described by start. If you have non-snooping
  180. * Harvard caches, you need to implement this function.
  181. *
  182. * - start - virtual start address
  183. * - end - virtual end address
  184. */
  185. ENTRY(arm1026_coherent_user_range)
  186. mov ip, #0
  187. bic r0, r0, #CACHE_DLINESIZE - 1
  188. 1:
  189. #ifndef CONFIG_CPU_DCACHE_DISABLE
  190. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  191. #endif
  192. #ifndef CONFIG_CPU_ICACHE_DISABLE
  193. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  194. #endif
  195. add r0, r0, #CACHE_DLINESIZE
  196. cmp r0, r1
  197. blo 1b
  198. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  199. mov r0, #0
  200. ret lr
  201. /*
  202. * flush_kern_dcache_area(void *addr, size_t size)
  203. *
  204. * Ensure no D cache aliasing occurs, either with itself or
  205. * the I cache
  206. *
  207. * - addr - kernel address
  208. * - size - region size
  209. */
  210. ENTRY(arm1026_flush_kern_dcache_area)
  211. mov ip, #0
  212. #ifndef CONFIG_CPU_DCACHE_DISABLE
  213. add r1, r0, r1
  214. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  215. add r0, r0, #CACHE_DLINESIZE
  216. cmp r0, r1
  217. blo 1b
  218. #endif
  219. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  220. ret lr
  221. /*
  222. * dma_inv_range(start, end)
  223. *
  224. * Invalidate (discard) the specified virtual address range.
  225. * May not write back any entries. If 'start' or 'end'
  226. * are not cache line aligned, those lines must be written
  227. * back.
  228. *
  229. * - start - virtual start address
  230. * - end - virtual end address
  231. *
  232. * (same as v4wb)
  233. */
  234. arm1026_dma_inv_range:
  235. mov ip, #0
  236. #ifndef CONFIG_CPU_DCACHE_DISABLE
  237. tst r0, #CACHE_DLINESIZE - 1
  238. bic r0, r0, #CACHE_DLINESIZE - 1
  239. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  240. tst r1, #CACHE_DLINESIZE - 1
  241. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  242. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  243. add r0, r0, #CACHE_DLINESIZE
  244. cmp r0, r1
  245. blo 1b
  246. #endif
  247. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  248. ret lr
  249. /*
  250. * dma_clean_range(start, end)
  251. *
  252. * Clean the specified virtual address range.
  253. *
  254. * - start - virtual start address
  255. * - end - virtual end address
  256. *
  257. * (same as v4wb)
  258. */
  259. arm1026_dma_clean_range:
  260. mov ip, #0
  261. #ifndef CONFIG_CPU_DCACHE_DISABLE
  262. bic r0, r0, #CACHE_DLINESIZE - 1
  263. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  264. add r0, r0, #CACHE_DLINESIZE
  265. cmp r0, r1
  266. blo 1b
  267. #endif
  268. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  269. ret lr
  270. /*
  271. * dma_flush_range(start, end)
  272. *
  273. * Clean and invalidate the specified virtual address range.
  274. *
  275. * - start - virtual start address
  276. * - end - virtual end address
  277. */
  278. ENTRY(arm1026_dma_flush_range)
  279. mov ip, #0
  280. #ifndef CONFIG_CPU_DCACHE_DISABLE
  281. bic r0, r0, #CACHE_DLINESIZE - 1
  282. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  283. add r0, r0, #CACHE_DLINESIZE
  284. cmp r0, r1
  285. blo 1b
  286. #endif
  287. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  288. ret lr
  289. /*
  290. * dma_map_area(start, size, dir)
  291. * - start - kernel virtual start address
  292. * - size - size of region
  293. * - dir - DMA direction
  294. */
  295. ENTRY(arm1026_dma_map_area)
  296. add r1, r1, r0
  297. cmp r2, #DMA_TO_DEVICE
  298. beq arm1026_dma_clean_range
  299. bcs arm1026_dma_inv_range
  300. b arm1026_dma_flush_range
  301. ENDPROC(arm1026_dma_map_area)
  302. /*
  303. * dma_unmap_area(start, size, dir)
  304. * - start - kernel virtual start address
  305. * - size - size of region
  306. * - dir - DMA direction
  307. */
  308. ENTRY(arm1026_dma_unmap_area)
  309. ret lr
  310. ENDPROC(arm1026_dma_unmap_area)
  311. .globl arm1026_flush_kern_cache_louis
  312. .equ arm1026_flush_kern_cache_louis, arm1026_flush_kern_cache_all
  313. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  314. define_cache_functions arm1026
  315. .align 5
  316. ENTRY(cpu_arm1026_dcache_clean_area)
  317. #ifndef CONFIG_CPU_DCACHE_DISABLE
  318. mov ip, #0
  319. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  320. add r0, r0, #CACHE_DLINESIZE
  321. subs r1, r1, #CACHE_DLINESIZE
  322. bhi 1b
  323. #endif
  324. ret lr
  325. /* =============================== PageTable ============================== */
  326. /*
  327. * cpu_arm1026_switch_mm(pgd)
  328. *
  329. * Set the translation base pointer to be as described by pgd.
  330. *
  331. * pgd: new page tables
  332. */
  333. .align 5
  334. ENTRY(cpu_arm1026_switch_mm)
  335. #ifdef CONFIG_MMU
  336. mov r1, #0
  337. #ifndef CONFIG_CPU_DCACHE_DISABLE
  338. 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate
  339. bne 1b
  340. #endif
  341. #ifndef CONFIG_CPU_ICACHE_DISABLE
  342. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  343. #endif
  344. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  345. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  346. mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
  347. #endif
  348. ret lr
  349. /*
  350. * cpu_arm1026_set_pte_ext(ptep, pte, ext)
  351. *
  352. * Set a PTE and flush it out
  353. */
  354. .align 5
  355. ENTRY(cpu_arm1026_set_pte_ext)
  356. #ifdef CONFIG_MMU
  357. armv3_set_pte_ext
  358. mov r0, r0
  359. #ifndef CONFIG_CPU_DCACHE_DISABLE
  360. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  361. #endif
  362. #endif /* CONFIG_MMU */
  363. ret lr
  364. .type __arm1026_setup, #function
  365. __arm1026_setup:
  366. mov r0, #0
  367. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  368. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  369. #ifdef CONFIG_MMU
  370. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  371. mcr p15, 0, r4, c2, c0 @ load page table pointer
  372. #endif
  373. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  374. mov r0, #4 @ explicitly disable writeback
  375. mcr p15, 7, r0, c15, c0, 0
  376. #endif
  377. adr r5, arm1026_crval
  378. ldmia r5, {r5, r6}
  379. mrc p15, 0, r0, c1, c0 @ get control register v4
  380. bic r0, r0, r5
  381. orr r0, r0, r6
  382. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  383. orr r0, r0, #0x4000 @ .R.. .... .... ....
  384. #endif
  385. ret lr
  386. .size __arm1026_setup, . - __arm1026_setup
  387. /*
  388. * R
  389. * .RVI ZFRS BLDP WCAM
  390. * .011 1001 ..11 0101
  391. *
  392. */
  393. .type arm1026_crval, #object
  394. arm1026_crval:
  395. crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
  396. __INITDATA
  397. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  398. define_processor_functions arm1026, dabort=v5t_early_abort, pabort=legacy_pabort
  399. .section .rodata
  400. string cpu_arch_name, "armv5tej"
  401. string cpu_elf_name, "v5"
  402. .align
  403. string cpu_arm1026_name, "ARM1026EJ-S"
  404. .align
  405. .section ".proc.info.init", "a"
  406. .type __arm1026_proc_info,#object
  407. __arm1026_proc_info:
  408. .long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
  409. .long 0xff0ffff0
  410. .long PMD_TYPE_SECT | \
  411. PMD_BIT4 | \
  412. PMD_SECT_AP_WRITE | \
  413. PMD_SECT_AP_READ
  414. .long PMD_TYPE_SECT | \
  415. PMD_BIT4 | \
  416. PMD_SECT_AP_WRITE | \
  417. PMD_SECT_AP_READ
  418. initfn __arm1026_setup, __arm1026_proc_info
  419. .long cpu_arch_name
  420. .long cpu_elf_name
  421. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
  422. .long cpu_arm1026_name
  423. .long arm1026_processor_functions
  424. .long v4wbi_tlb_fns
  425. .long v4wb_user_fns
  426. .long arm1026_cache_fns
  427. .size __arm1026_proc_info, . - __arm1026_proc_info