proc-arm1022.S 11 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
  4. *
  5. * Copyright (C) 2000 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  8. *
  9. * These are the low level assembler for performing cache and TLB
  10. * functions on the ARM1022E.
  11. */
  12. #include <linux/linkage.h>
  13. #include <linux/init.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/assembler.h>
  16. #include <asm/asm-offsets.h>
  17. #include <asm/hwcap.h>
  18. #include <asm/pgtable-hwdef.h>
  19. #include <asm/ptrace.h>
  20. #include "proc-macros.S"
  21. /*
  22. * This is the maximum size of an area which will be invalidated
  23. * using the single invalidate entry instructions. Anything larger
  24. * than this, and we go for the whole cache.
  25. *
  26. * This value should be chosen such that we choose the cheapest
  27. * alternative.
  28. */
  29. #define MAX_AREA_SIZE 32768
  30. /*
  31. * The size of one data cache line.
  32. */
  33. #define CACHE_DLINESIZE 32
  34. /*
  35. * The number of data cache segments.
  36. */
  37. #define CACHE_DSEGMENTS 16
  38. /*
  39. * The number of lines in a cache segment.
  40. */
  41. #define CACHE_DENTRIES 64
  42. /*
  43. * This is the size at which it becomes more efficient to
  44. * clean the whole cache, rather than using the individual
  45. * cache line maintenance instructions.
  46. */
  47. #define CACHE_DLIMIT 32768
  48. .text
  49. /*
  50. * cpu_arm1022_proc_init()
  51. */
  52. ENTRY(cpu_arm1022_proc_init)
  53. ret lr
  54. /*
  55. * cpu_arm1022_proc_fin()
  56. */
  57. ENTRY(cpu_arm1022_proc_fin)
  58. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  59. bic r0, r0, #0x1000 @ ...i............
  60. bic r0, r0, #0x000e @ ............wca.
  61. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  62. ret lr
  63. /*
  64. * cpu_arm1022_reset(loc)
  65. *
  66. * Perform a soft reset of the system. Put the CPU into the
  67. * same state as it would be if it had been reset, and branch
  68. * to what would be the reset vector.
  69. *
  70. * loc: location to jump to for soft reset
  71. */
  72. .align 5
  73. .pushsection .idmap.text, "ax"
  74. ENTRY(cpu_arm1022_reset)
  75. mov ip, #0
  76. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  77. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  78. #ifdef CONFIG_MMU
  79. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  80. #endif
  81. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  82. bic ip, ip, #0x000f @ ............wcam
  83. bic ip, ip, #0x1100 @ ...i...s........
  84. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  85. ret r0
  86. ENDPROC(cpu_arm1022_reset)
  87. .popsection
  88. /*
  89. * cpu_arm1022_do_idle()
  90. */
  91. .align 5
  92. ENTRY(cpu_arm1022_do_idle)
  93. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  94. ret lr
  95. /* ================================= CACHE ================================ */
  96. .align 5
  97. /*
  98. * flush_icache_all()
  99. *
  100. * Unconditionally clean and invalidate the entire icache.
  101. */
  102. ENTRY(arm1022_flush_icache_all)
  103. #ifndef CONFIG_CPU_ICACHE_DISABLE
  104. mov r0, #0
  105. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  106. #endif
  107. ret lr
  108. ENDPROC(arm1022_flush_icache_all)
  109. /*
  110. * flush_user_cache_all()
  111. *
  112. * Invalidate all cache entries in a particular address
  113. * space.
  114. */
  115. ENTRY(arm1022_flush_user_cache_all)
  116. /* FALLTHROUGH */
  117. /*
  118. * flush_kern_cache_all()
  119. *
  120. * Clean and invalidate the entire cache.
  121. */
  122. ENTRY(arm1022_flush_kern_cache_all)
  123. mov r2, #VM_EXEC
  124. mov ip, #0
  125. __flush_whole_cache:
  126. #ifndef CONFIG_CPU_DCACHE_DISABLE
  127. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
  128. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  129. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  130. subs r3, r3, #1 << 26
  131. bcs 2b @ entries 63 to 0
  132. subs r1, r1, #1 << 5
  133. bcs 1b @ segments 15 to 0
  134. #endif
  135. tst r2, #VM_EXEC
  136. #ifndef CONFIG_CPU_ICACHE_DISABLE
  137. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  138. #endif
  139. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  140. ret lr
  141. /*
  142. * flush_user_cache_range(start, end, flags)
  143. *
  144. * Invalidate a range of cache entries in the specified
  145. * address space.
  146. *
  147. * - start - start address (inclusive)
  148. * - end - end address (exclusive)
  149. * - flags - vm_flags for this space
  150. */
  151. ENTRY(arm1022_flush_user_cache_range)
  152. mov ip, #0
  153. sub r3, r1, r0 @ calculate total size
  154. cmp r3, #CACHE_DLIMIT
  155. bhs __flush_whole_cache
  156. #ifndef CONFIG_CPU_DCACHE_DISABLE
  157. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  158. add r0, r0, #CACHE_DLINESIZE
  159. cmp r0, r1
  160. blo 1b
  161. #endif
  162. tst r2, #VM_EXEC
  163. #ifndef CONFIG_CPU_ICACHE_DISABLE
  164. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  165. #endif
  166. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  167. ret lr
  168. /*
  169. * coherent_kern_range(start, end)
  170. *
  171. * Ensure coherency between the Icache and the Dcache in the
  172. * region described by start. If you have non-snooping
  173. * Harvard caches, you need to implement this function.
  174. *
  175. * - start - virtual start address
  176. * - end - virtual end address
  177. */
  178. ENTRY(arm1022_coherent_kern_range)
  179. /* FALLTHROUGH */
  180. /*
  181. * coherent_user_range(start, end)
  182. *
  183. * Ensure coherency between the Icache and the Dcache in the
  184. * region described by start. If you have non-snooping
  185. * Harvard caches, you need to implement this function.
  186. *
  187. * - start - virtual start address
  188. * - end - virtual end address
  189. */
  190. ENTRY(arm1022_coherent_user_range)
  191. mov ip, #0
  192. bic r0, r0, #CACHE_DLINESIZE - 1
  193. 1:
  194. #ifndef CONFIG_CPU_DCACHE_DISABLE
  195. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  196. #endif
  197. #ifndef CONFIG_CPU_ICACHE_DISABLE
  198. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  199. #endif
  200. add r0, r0, #CACHE_DLINESIZE
  201. cmp r0, r1
  202. blo 1b
  203. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  204. mov r0, #0
  205. ret lr
  206. /*
  207. * flush_kern_dcache_area(void *addr, size_t size)
  208. *
  209. * Ensure no D cache aliasing occurs, either with itself or
  210. * the I cache
  211. *
  212. * - addr - kernel address
  213. * - size - region size
  214. */
  215. ENTRY(arm1022_flush_kern_dcache_area)
  216. mov ip, #0
  217. #ifndef CONFIG_CPU_DCACHE_DISABLE
  218. add r1, r0, r1
  219. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  220. add r0, r0, #CACHE_DLINESIZE
  221. cmp r0, r1
  222. blo 1b
  223. #endif
  224. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  225. ret lr
  226. /*
  227. * dma_inv_range(start, end)
  228. *
  229. * Invalidate (discard) the specified virtual address range.
  230. * May not write back any entries. If 'start' or 'end'
  231. * are not cache line aligned, those lines must be written
  232. * back.
  233. *
  234. * - start - virtual start address
  235. * - end - virtual end address
  236. *
  237. * (same as v4wb)
  238. */
  239. arm1022_dma_inv_range:
  240. mov ip, #0
  241. #ifndef CONFIG_CPU_DCACHE_DISABLE
  242. tst r0, #CACHE_DLINESIZE - 1
  243. bic r0, r0, #CACHE_DLINESIZE - 1
  244. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  245. tst r1, #CACHE_DLINESIZE - 1
  246. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  247. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  248. add r0, r0, #CACHE_DLINESIZE
  249. cmp r0, r1
  250. blo 1b
  251. #endif
  252. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  253. ret lr
  254. /*
  255. * dma_clean_range(start, end)
  256. *
  257. * Clean the specified virtual address range.
  258. *
  259. * - start - virtual start address
  260. * - end - virtual end address
  261. *
  262. * (same as v4wb)
  263. */
  264. arm1022_dma_clean_range:
  265. mov ip, #0
  266. #ifndef CONFIG_CPU_DCACHE_DISABLE
  267. bic r0, r0, #CACHE_DLINESIZE - 1
  268. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  269. add r0, r0, #CACHE_DLINESIZE
  270. cmp r0, r1
  271. blo 1b
  272. #endif
  273. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  274. ret lr
  275. /*
  276. * dma_flush_range(start, end)
  277. *
  278. * Clean and invalidate the specified virtual address range.
  279. *
  280. * - start - virtual start address
  281. * - end - virtual end address
  282. */
  283. ENTRY(arm1022_dma_flush_range)
  284. mov ip, #0
  285. #ifndef CONFIG_CPU_DCACHE_DISABLE
  286. bic r0, r0, #CACHE_DLINESIZE - 1
  287. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  288. add r0, r0, #CACHE_DLINESIZE
  289. cmp r0, r1
  290. blo 1b
  291. #endif
  292. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  293. ret lr
  294. /*
  295. * dma_map_area(start, size, dir)
  296. * - start - kernel virtual start address
  297. * - size - size of region
  298. * - dir - DMA direction
  299. */
  300. ENTRY(arm1022_dma_map_area)
  301. add r1, r1, r0
  302. cmp r2, #DMA_TO_DEVICE
  303. beq arm1022_dma_clean_range
  304. bcs arm1022_dma_inv_range
  305. b arm1022_dma_flush_range
  306. ENDPROC(arm1022_dma_map_area)
  307. /*
  308. * dma_unmap_area(start, size, dir)
  309. * - start - kernel virtual start address
  310. * - size - size of region
  311. * - dir - DMA direction
  312. */
  313. ENTRY(arm1022_dma_unmap_area)
  314. ret lr
  315. ENDPROC(arm1022_dma_unmap_area)
  316. .globl arm1022_flush_kern_cache_louis
  317. .equ arm1022_flush_kern_cache_louis, arm1022_flush_kern_cache_all
  318. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  319. define_cache_functions arm1022
  320. .align 5
  321. ENTRY(cpu_arm1022_dcache_clean_area)
  322. #ifndef CONFIG_CPU_DCACHE_DISABLE
  323. mov ip, #0
  324. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  325. add r0, r0, #CACHE_DLINESIZE
  326. subs r1, r1, #CACHE_DLINESIZE
  327. bhi 1b
  328. #endif
  329. ret lr
  330. /* =============================== PageTable ============================== */
  331. /*
  332. * cpu_arm1022_switch_mm(pgd)
  333. *
  334. * Set the translation base pointer to be as described by pgd.
  335. *
  336. * pgd: new page tables
  337. */
  338. .align 5
  339. ENTRY(cpu_arm1022_switch_mm)
  340. #ifdef CONFIG_MMU
  341. #ifndef CONFIG_CPU_DCACHE_DISABLE
  342. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
  343. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  344. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  345. subs r3, r3, #1 << 26
  346. bcs 2b @ entries 63 to 0
  347. subs r1, r1, #1 << 5
  348. bcs 1b @ segments 15 to 0
  349. #endif
  350. mov r1, #0
  351. #ifndef CONFIG_CPU_ICACHE_DISABLE
  352. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  353. #endif
  354. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  355. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  356. mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
  357. #endif
  358. ret lr
  359. /*
  360. * cpu_arm1022_set_pte_ext(ptep, pte, ext)
  361. *
  362. * Set a PTE and flush it out
  363. */
  364. .align 5
  365. ENTRY(cpu_arm1022_set_pte_ext)
  366. #ifdef CONFIG_MMU
  367. armv3_set_pte_ext
  368. mov r0, r0
  369. #ifndef CONFIG_CPU_DCACHE_DISABLE
  370. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  371. #endif
  372. #endif /* CONFIG_MMU */
  373. ret lr
  374. .type __arm1022_setup, #function
  375. __arm1022_setup:
  376. mov r0, #0
  377. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  378. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  379. #ifdef CONFIG_MMU
  380. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  381. #endif
  382. adr r5, arm1022_crval
  383. ldmia r5, {r5, r6}
  384. mrc p15, 0, r0, c1, c0 @ get control register v4
  385. bic r0, r0, r5
  386. orr r0, r0, r6
  387. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  388. orr r0, r0, #0x4000 @ .R..............
  389. #endif
  390. ret lr
  391. .size __arm1022_setup, . - __arm1022_setup
  392. /*
  393. * R
  394. * .RVI ZFRS BLDP WCAM
  395. * .011 1001 ..11 0101
  396. *
  397. */
  398. .type arm1022_crval, #object
  399. arm1022_crval:
  400. crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
  401. __INITDATA
  402. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  403. define_processor_functions arm1022, dabort=v4t_early_abort, pabort=legacy_pabort
  404. .section ".rodata"
  405. string cpu_arch_name, "armv5te"
  406. string cpu_elf_name, "v5"
  407. string cpu_arm1022_name, "ARM1022"
  408. .align
  409. .section ".proc.info.init", "a"
  410. .type __arm1022_proc_info,#object
  411. __arm1022_proc_info:
  412. .long 0x4105a220 @ ARM 1022E (v5TE)
  413. .long 0xff0ffff0
  414. .long PMD_TYPE_SECT | \
  415. PMD_BIT4 | \
  416. PMD_SECT_AP_WRITE | \
  417. PMD_SECT_AP_READ
  418. .long PMD_TYPE_SECT | \
  419. PMD_BIT4 | \
  420. PMD_SECT_AP_WRITE | \
  421. PMD_SECT_AP_READ
  422. initfn __arm1022_setup, __arm1022_proc_info
  423. .long cpu_arch_name
  424. .long cpu_elf_name
  425. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
  426. .long cpu_arm1022_name
  427. .long arm1022_processor_functions
  428. .long v4wbi_tlb_fns
  429. .long v4wb_user_fns
  430. .long arm1022_cache_fns
  431. .size __arm1022_proc_info, . - __arm1022_proc_info