proc-arm1020.S 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
  4. *
  5. * Copyright (C) 2000 ARM Limited
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. * hacked for non-paged-MM by Hyok S. Choi, 2003.
  8. *
  9. * These are the low level assembler for performing cache and TLB
  10. * functions on the arm1020.
  11. */
  12. #include <linux/linkage.h>
  13. #include <linux/init.h>
  14. #include <linux/pgtable.h>
  15. #include <asm/assembler.h>
  16. #include <asm/asm-offsets.h>
  17. #include <asm/hwcap.h>
  18. #include <asm/pgtable-hwdef.h>
  19. #include <asm/ptrace.h>
  20. #include "proc-macros.S"
  21. /*
  22. * This is the maximum size of an area which will be invalidated
  23. * using the single invalidate entry instructions. Anything larger
  24. * than this, and we go for the whole cache.
  25. *
  26. * This value should be chosen such that we choose the cheapest
  27. * alternative.
  28. */
  29. #define MAX_AREA_SIZE 32768
  30. /*
  31. * The size of one data cache line.
  32. */
  33. #define CACHE_DLINESIZE 32
  34. /*
  35. * The number of data cache segments.
  36. */
  37. #define CACHE_DSEGMENTS 16
  38. /*
  39. * The number of lines in a cache segment.
  40. */
  41. #define CACHE_DENTRIES 64
  42. /*
  43. * This is the size at which it becomes more efficient to
  44. * clean the whole cache, rather than using the individual
  45. * cache line maintenance instructions.
  46. */
  47. #define CACHE_DLIMIT 32768
  48. .text
  49. /*
  50. * cpu_arm1020_proc_init()
  51. */
  52. ENTRY(cpu_arm1020_proc_init)
  53. ret lr
  54. /*
  55. * cpu_arm1020_proc_fin()
  56. */
  57. ENTRY(cpu_arm1020_proc_fin)
  58. mrc p15, 0, r0, c1, c0, 0 @ ctrl register
  59. bic r0, r0, #0x1000 @ ...i............
  60. bic r0, r0, #0x000e @ ............wca.
  61. mcr p15, 0, r0, c1, c0, 0 @ disable caches
  62. ret lr
  63. /*
  64. * cpu_arm1020_reset(loc)
  65. *
  66. * Perform a soft reset of the system. Put the CPU into the
  67. * same state as it would be if it had been reset, and branch
  68. * to what would be the reset vector.
  69. *
  70. * loc: location to jump to for soft reset
  71. */
  72. .align 5
  73. .pushsection .idmap.text, "ax"
  74. ENTRY(cpu_arm1020_reset)
  75. mov ip, #0
  76. mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
  77. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  78. #ifdef CONFIG_MMU
  79. mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
  80. #endif
  81. mrc p15, 0, ip, c1, c0, 0 @ ctrl register
  82. bic ip, ip, #0x000f @ ............wcam
  83. bic ip, ip, #0x1100 @ ...i...s........
  84. mcr p15, 0, ip, c1, c0, 0 @ ctrl register
  85. ret r0
  86. ENDPROC(cpu_arm1020_reset)
  87. .popsection
  88. /*
  89. * cpu_arm1020_do_idle()
  90. */
  91. .align 5
  92. ENTRY(cpu_arm1020_do_idle)
  93. mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
  94. ret lr
  95. /* ================================= CACHE ================================ */
  96. .align 5
  97. /*
  98. * flush_icache_all()
  99. *
  100. * Unconditionally clean and invalidate the entire icache.
  101. */
  102. ENTRY(arm1020_flush_icache_all)
  103. #ifndef CONFIG_CPU_ICACHE_DISABLE
  104. mov r0, #0
  105. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  106. #endif
  107. ret lr
  108. ENDPROC(arm1020_flush_icache_all)
  109. /*
  110. * flush_user_cache_all()
  111. *
  112. * Invalidate all cache entries in a particular address
  113. * space.
  114. */
  115. ENTRY(arm1020_flush_user_cache_all)
  116. /* FALLTHROUGH */
  117. /*
  118. * flush_kern_cache_all()
  119. *
  120. * Clean and invalidate the entire cache.
  121. */
  122. ENTRY(arm1020_flush_kern_cache_all)
  123. mov r2, #VM_EXEC
  124. mov ip, #0
  125. __flush_whole_cache:
  126. #ifndef CONFIG_CPU_DCACHE_DISABLE
  127. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  128. mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
  129. 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
  130. 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
  131. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  132. subs r3, r3, #1 << 26
  133. bcs 2b @ entries 63 to 0
  134. subs r1, r1, #1 << 5
  135. bcs 1b @ segments 15 to 0
  136. #endif
  137. tst r2, #VM_EXEC
  138. #ifndef CONFIG_CPU_ICACHE_DISABLE
  139. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  140. #endif
  141. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  142. ret lr
  143. /*
  144. * flush_user_cache_range(start, end, flags)
  145. *
  146. * Invalidate a range of cache entries in the specified
  147. * address space.
  148. *
  149. * - start - start address (inclusive)
  150. * - end - end address (exclusive)
  151. * - flags - vm_flags for this space
  152. */
  153. ENTRY(arm1020_flush_user_cache_range)
  154. mov ip, #0
  155. sub r3, r1, r0 @ calculate total size
  156. cmp r3, #CACHE_DLIMIT
  157. bhs __flush_whole_cache
  158. #ifndef CONFIG_CPU_DCACHE_DISABLE
  159. mcr p15, 0, ip, c7, c10, 4
  160. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  161. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  162. add r0, r0, #CACHE_DLINESIZE
  163. cmp r0, r1
  164. blo 1b
  165. #endif
  166. tst r2, #VM_EXEC
  167. #ifndef CONFIG_CPU_ICACHE_DISABLE
  168. mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
  169. #endif
  170. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  171. ret lr
  172. /*
  173. * coherent_kern_range(start, end)
  174. *
  175. * Ensure coherency between the Icache and the Dcache in the
  176. * region described by start. If you have non-snooping
  177. * Harvard caches, you need to implement this function.
  178. *
  179. * - start - virtual start address
  180. * - end - virtual end address
  181. */
  182. ENTRY(arm1020_coherent_kern_range)
  183. /* FALLTRHOUGH */
  184. /*
  185. * coherent_user_range(start, end)
  186. *
  187. * Ensure coherency between the Icache and the Dcache in the
  188. * region described by start. If you have non-snooping
  189. * Harvard caches, you need to implement this function.
  190. *
  191. * - start - virtual start address
  192. * - end - virtual end address
  193. */
  194. ENTRY(arm1020_coherent_user_range)
  195. mov ip, #0
  196. bic r0, r0, #CACHE_DLINESIZE - 1
  197. mcr p15, 0, ip, c7, c10, 4
  198. 1:
  199. #ifndef CONFIG_CPU_DCACHE_DISABLE
  200. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  201. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  202. #endif
  203. #ifndef CONFIG_CPU_ICACHE_DISABLE
  204. mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
  205. #endif
  206. add r0, r0, #CACHE_DLINESIZE
  207. cmp r0, r1
  208. blo 1b
  209. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  210. mov r0, #0
  211. ret lr
  212. /*
  213. * flush_kern_dcache_area(void *addr, size_t size)
  214. *
  215. * Ensure no D cache aliasing occurs, either with itself or
  216. * the I cache
  217. *
  218. * - addr - kernel address
  219. * - size - region size
  220. */
  221. ENTRY(arm1020_flush_kern_dcache_area)
  222. mov ip, #0
  223. #ifndef CONFIG_CPU_DCACHE_DISABLE
  224. add r1, r0, r1
  225. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  226. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  227. add r0, r0, #CACHE_DLINESIZE
  228. cmp r0, r1
  229. blo 1b
  230. #endif
  231. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  232. ret lr
  233. /*
  234. * dma_inv_range(start, end)
  235. *
  236. * Invalidate (discard) the specified virtual address range.
  237. * May not write back any entries. If 'start' or 'end'
  238. * are not cache line aligned, those lines must be written
  239. * back.
  240. *
  241. * - start - virtual start address
  242. * - end - virtual end address
  243. *
  244. * (same as v4wb)
  245. */
  246. arm1020_dma_inv_range:
  247. mov ip, #0
  248. #ifndef CONFIG_CPU_DCACHE_DISABLE
  249. tst r0, #CACHE_DLINESIZE - 1
  250. bic r0, r0, #CACHE_DLINESIZE - 1
  251. mcrne p15, 0, ip, c7, c10, 4
  252. mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
  253. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  254. tst r1, #CACHE_DLINESIZE - 1
  255. mcrne p15, 0, ip, c7, c10, 4
  256. mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
  257. mcrne p15, 0, ip, c7, c10, 4 @ drain WB
  258. 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
  259. add r0, r0, #CACHE_DLINESIZE
  260. cmp r0, r1
  261. blo 1b
  262. #endif
  263. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  264. ret lr
  265. /*
  266. * dma_clean_range(start, end)
  267. *
  268. * Clean the specified virtual address range.
  269. *
  270. * - start - virtual start address
  271. * - end - virtual end address
  272. *
  273. * (same as v4wb)
  274. */
  275. arm1020_dma_clean_range:
  276. mov ip, #0
  277. #ifndef CONFIG_CPU_DCACHE_DISABLE
  278. bic r0, r0, #CACHE_DLINESIZE - 1
  279. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  280. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  281. add r0, r0, #CACHE_DLINESIZE
  282. cmp r0, r1
  283. blo 1b
  284. #endif
  285. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  286. ret lr
  287. /*
  288. * dma_flush_range(start, end)
  289. *
  290. * Clean and invalidate the specified virtual address range.
  291. *
  292. * - start - virtual start address
  293. * - end - virtual end address
  294. */
  295. ENTRY(arm1020_dma_flush_range)
  296. mov ip, #0
  297. #ifndef CONFIG_CPU_DCACHE_DISABLE
  298. bic r0, r0, #CACHE_DLINESIZE - 1
  299. mcr p15, 0, ip, c7, c10, 4
  300. 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
  301. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  302. add r0, r0, #CACHE_DLINESIZE
  303. cmp r0, r1
  304. blo 1b
  305. #endif
  306. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  307. ret lr
  308. /*
  309. * dma_map_area(start, size, dir)
  310. * - start - kernel virtual start address
  311. * - size - size of region
  312. * - dir - DMA direction
  313. */
  314. ENTRY(arm1020_dma_map_area)
  315. add r1, r1, r0
  316. cmp r2, #DMA_TO_DEVICE
  317. beq arm1020_dma_clean_range
  318. bcs arm1020_dma_inv_range
  319. b arm1020_dma_flush_range
  320. ENDPROC(arm1020_dma_map_area)
  321. /*
  322. * dma_unmap_area(start, size, dir)
  323. * - start - kernel virtual start address
  324. * - size - size of region
  325. * - dir - DMA direction
  326. */
  327. ENTRY(arm1020_dma_unmap_area)
  328. ret lr
  329. ENDPROC(arm1020_dma_unmap_area)
  330. .globl arm1020_flush_kern_cache_louis
  331. .equ arm1020_flush_kern_cache_louis, arm1020_flush_kern_cache_all
  332. @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
  333. define_cache_functions arm1020
  334. .align 5
  335. ENTRY(cpu_arm1020_dcache_clean_area)
  336. #ifndef CONFIG_CPU_DCACHE_DISABLE
  337. mov ip, #0
  338. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  339. mcr p15, 0, ip, c7, c10, 4 @ drain WB
  340. add r0, r0, #CACHE_DLINESIZE
  341. subs r1, r1, #CACHE_DLINESIZE
  342. bhi 1b
  343. #endif
  344. ret lr
  345. /* =============================== PageTable ============================== */
  346. /*
  347. * cpu_arm1020_switch_mm(pgd)
  348. *
  349. * Set the translation base pointer to be as described by pgd.
  350. *
  351. * pgd: new page tables
  352. */
  353. .align 5
  354. ENTRY(cpu_arm1020_switch_mm)
  355. #ifdef CONFIG_MMU
  356. #ifndef CONFIG_CPU_DCACHE_DISABLE
  357. mcr p15, 0, r3, c7, c10, 4
  358. mov r1, #0xF @ 16 segments
  359. 1: mov r3, #0x3F @ 64 entries
  360. 2: mov ip, r3, LSL #26 @ shift up entry
  361. orr ip, ip, r1, LSL #5 @ shift in/up index
  362. mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
  363. mov ip, #0
  364. mcr p15, 0, ip, c7, c10, 4
  365. subs r3, r3, #1
  366. cmp r3, #0
  367. bge 2b @ entries 3F to 0
  368. subs r1, r1, #1
  369. cmp r1, #0
  370. bge 1b @ segments 15 to 0
  371. #endif
  372. mov r1, #0
  373. #ifndef CONFIG_CPU_ICACHE_DISABLE
  374. mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
  375. #endif
  376. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  377. mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
  378. mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
  379. #endif /* CONFIG_MMU */
  380. ret lr
  381. /*
  382. * cpu_arm1020_set_pte(ptep, pte)
  383. *
  384. * Set a PTE and flush it out
  385. */
  386. .align 5
  387. ENTRY(cpu_arm1020_set_pte_ext)
  388. #ifdef CONFIG_MMU
  389. armv3_set_pte_ext
  390. mov r0, r0
  391. #ifndef CONFIG_CPU_DCACHE_DISABLE
  392. mcr p15, 0, r0, c7, c10, 4
  393. mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  394. #endif
  395. mcr p15, 0, r0, c7, c10, 4 @ drain WB
  396. #endif /* CONFIG_MMU */
  397. ret lr
  398. .type __arm1020_setup, #function
  399. __arm1020_setup:
  400. mov r0, #0
  401. mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
  402. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
  403. #ifdef CONFIG_MMU
  404. mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
  405. #endif
  406. adr r5, arm1020_crval
  407. ldmia r5, {r5, r6}
  408. mrc p15, 0, r0, c1, c0 @ get control register v4
  409. bic r0, r0, r5
  410. orr r0, r0, r6
  411. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  412. orr r0, r0, #0x4000 @ .R.. .... .... ....
  413. #endif
  414. ret lr
  415. .size __arm1020_setup, . - __arm1020_setup
  416. /*
  417. * R
  418. * .RVI ZFRS BLDP WCAM
  419. * .011 1001 ..11 0101
  420. */
  421. .type arm1020_crval, #object
  422. arm1020_crval:
  423. crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
  424. __INITDATA
  425. @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
  426. define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
  427. .section ".rodata"
  428. string cpu_arch_name, "armv5t"
  429. string cpu_elf_name, "v5"
  430. .type cpu_arm1020_name, #object
  431. cpu_arm1020_name:
  432. .ascii "ARM1020"
  433. #ifndef CONFIG_CPU_ICACHE_DISABLE
  434. .ascii "i"
  435. #endif
  436. #ifndef CONFIG_CPU_DCACHE_DISABLE
  437. .ascii "d"
  438. #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
  439. .ascii "(wt)"
  440. #else
  441. .ascii "(wb)"
  442. #endif
  443. #endif
  444. #ifndef CONFIG_CPU_BPREDICT_DISABLE
  445. .ascii "B"
  446. #endif
  447. #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
  448. .ascii "RR"
  449. #endif
  450. .ascii "\0"
  451. .size cpu_arm1020_name, . - cpu_arm1020_name
  452. .align
  453. .section ".proc.info.init", "a"
  454. .type __arm1020_proc_info,#object
  455. __arm1020_proc_info:
  456. .long 0x4104a200 @ ARM 1020T (Architecture v5T)
  457. .long 0xff0ffff0
  458. .long PMD_TYPE_SECT | \
  459. PMD_SECT_AP_WRITE | \
  460. PMD_SECT_AP_READ
  461. .long PMD_TYPE_SECT | \
  462. PMD_SECT_AP_WRITE | \
  463. PMD_SECT_AP_READ
  464. initfn __arm1020_setup, __arm1020_proc_info
  465. .long cpu_arch_name
  466. .long cpu_elf_name
  467. .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
  468. .long cpu_arm1020_name
  469. .long arm1020_processor_functions
  470. .long v4wbi_tlb_fns
  471. .long v4wb_user_fns
  472. .long arm1020_cache_fns
  473. .size __arm1020_proc_info, . - __arm1020_proc_info