copypage-v4wt.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mm/copypage-v4wt.S
  4. *
  5. * Copyright (C) 1995-1999 Russell King
  6. *
  7. * This is for CPUs with a writethrough cache and 'flush ID cache' is
  8. * the only supported cache operation.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/highmem.h>
  12. /*
  13. * ARMv4 optimised copy_user_highpage
  14. *
  15. * Since we have writethrough caches, we don't have to worry about
  16. * dirty data in the cache. However, we do have to ensure that
  17. * subsequent reads are up to date.
  18. */
  19. static void v4wt_copy_user_page(void *kto, const void *kfrom)
  20. {
  21. int tmp;
  22. asm volatile ("\
  23. .syntax unified\n\
  24. ldmia %1!, {r3, r4, ip, lr} @ 4\n\
  25. 1: stmia %0!, {r3, r4, ip, lr} @ 4\n\
  26. ldmia %1!, {r3, r4, ip, lr} @ 4+1\n\
  27. stmia %0!, {r3, r4, ip, lr} @ 4\n\
  28. ldmia %1!, {r3, r4, ip, lr} @ 4\n\
  29. stmia %0!, {r3, r4, ip, lr} @ 4\n\
  30. ldmia %1!, {r3, r4, ip, lr} @ 4\n\
  31. subs %2, %2, #1 @ 1\n\
  32. stmia %0!, {r3, r4, ip, lr} @ 4\n\
  33. ldmiane %1!, {r3, r4, ip, lr} @ 4\n\
  34. bne 1b @ 1\n\
  35. mcr p15, 0, %2, c7, c7, 0 @ flush ID cache"
  36. : "+&r" (kto), "+&r" (kfrom), "=&r" (tmp)
  37. : "2" (PAGE_SIZE / 64)
  38. : "r3", "r4", "ip", "lr");
  39. }
  40. void v4wt_copy_user_highpage(struct page *to, struct page *from,
  41. unsigned long vaddr, struct vm_area_struct *vma)
  42. {
  43. void *kto, *kfrom;
  44. kto = kmap_atomic(to);
  45. kfrom = kmap_atomic(from);
  46. v4wt_copy_user_page(kto, kfrom);
  47. kunmap_atomic(kfrom);
  48. kunmap_atomic(kto);
  49. }
  50. /*
  51. * ARMv4 optimised clear_user_page
  52. *
  53. * Same story as above.
  54. */
  55. void v4wt_clear_user_highpage(struct page *page, unsigned long vaddr)
  56. {
  57. void *ptr, *kaddr = kmap_atomic(page);
  58. asm volatile("\
  59. mov r1, %2 @ 1\n\
  60. mov r2, #0 @ 1\n\
  61. mov r3, #0 @ 1\n\
  62. mov ip, #0 @ 1\n\
  63. mov lr, #0 @ 1\n\
  64. 1: stmia %0!, {r2, r3, ip, lr} @ 4\n\
  65. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  66. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  67. stmia %0!, {r2, r3, ip, lr} @ 4\n\
  68. subs r1, r1, #1 @ 1\n\
  69. bne 1b @ 1\n\
  70. mcr p15, 0, r2, c7, c7, 0 @ flush ID cache"
  71. : "=r" (ptr)
  72. : "0" (kaddr), "I" (PAGE_SIZE / 64)
  73. : "r1", "r2", "r3", "ip", "lr");
  74. kunmap_atomic(kaddr);
  75. }
  76. struct cpu_user_fns v4wt_user_fns __initdata = {
  77. .cpu_clear_user_highpage = v4wt_clear_user_highpage,
  78. .cpu_copy_user_highpage = v4wt_copy_user_highpage,
  79. };