cache-l2x0.c 49 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
  4. *
  5. * Copyright (C) 2007 ARM Limited
  6. */
  7. #include <linux/cpu.h>
  8. #include <linux/err.h>
  9. #include <linux/init.h>
  10. #include <linux/smp.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/log2.h>
  13. #include <linux/io.h>
  14. #include <linux/of.h>
  15. #include <linux/of_address.h>
  16. #include <asm/cacheflush.h>
  17. #include <asm/cp15.h>
  18. #include <asm/cputype.h>
  19. #include <asm/hardware/cache-l2x0.h>
  20. #include <asm/hardware/cache-aurora-l2.h>
  21. #include "cache-tauros3.h"
  22. struct l2c_init_data {
  23. const char *type;
  24. unsigned way_size_0;
  25. unsigned num_lock;
  26. void (*of_parse)(const struct device_node *, u32 *, u32 *);
  27. void (*enable)(void __iomem *, unsigned);
  28. void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
  29. void (*save)(void __iomem *);
  30. void (*configure)(void __iomem *);
  31. void (*unlock)(void __iomem *, unsigned);
  32. struct outer_cache_fns outer_cache;
  33. };
  34. #define CACHE_LINE_SIZE 32
  35. static void __iomem *l2x0_base;
  36. static const struct l2c_init_data *l2x0_data;
  37. static DEFINE_RAW_SPINLOCK(l2x0_lock);
  38. static u32 l2x0_way_mask; /* Bitmask of active ways */
  39. static u32 l2x0_size;
  40. static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
  41. struct l2x0_regs l2x0_saved_regs;
  42. static bool l2x0_bresp_disable;
  43. static bool l2x0_flz_disable;
  44. /*
  45. * Common code for all cache controllers.
  46. */
  47. static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
  48. {
  49. /* wait for cache operation by line or way to complete */
  50. while (readl_relaxed(reg) & mask)
  51. cpu_relax();
  52. }
  53. /*
  54. * By default, we write directly to secure registers. Platforms must
  55. * override this if they are running non-secure.
  56. */
  57. static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg)
  58. {
  59. if (val == readl_relaxed(base + reg))
  60. return;
  61. if (outer_cache.write_sec)
  62. outer_cache.write_sec(val, reg);
  63. else
  64. writel_relaxed(val, base + reg);
  65. }
  66. /*
  67. * This should only be called when we have a requirement that the
  68. * register be written due to a work-around, as platforms running
  69. * in non-secure mode may not be able to access this register.
  70. */
  71. static inline void l2c_set_debug(void __iomem *base, unsigned long val)
  72. {
  73. l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
  74. }
  75. static void __l2c_op_way(void __iomem *reg)
  76. {
  77. writel_relaxed(l2x0_way_mask, reg);
  78. l2c_wait_mask(reg, l2x0_way_mask);
  79. }
  80. static inline void l2c_unlock(void __iomem *base, unsigned num)
  81. {
  82. unsigned i;
  83. for (i = 0; i < num; i++) {
  84. writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
  85. i * L2X0_LOCKDOWN_STRIDE);
  86. writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
  87. i * L2X0_LOCKDOWN_STRIDE);
  88. }
  89. }
  90. static void l2c_configure(void __iomem *base)
  91. {
  92. l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL);
  93. }
  94. /*
  95. * Enable the L2 cache controller. This function must only be
  96. * called when the cache controller is known to be disabled.
  97. */
  98. static void l2c_enable(void __iomem *base, unsigned num_lock)
  99. {
  100. unsigned long flags;
  101. if (outer_cache.configure)
  102. outer_cache.configure(&l2x0_saved_regs);
  103. else
  104. l2x0_data->configure(base);
  105. l2x0_data->unlock(base, num_lock);
  106. local_irq_save(flags);
  107. __l2c_op_way(base + L2X0_INV_WAY);
  108. writel_relaxed(0, base + sync_reg_offset);
  109. l2c_wait_mask(base + sync_reg_offset, 1);
  110. local_irq_restore(flags);
  111. l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
  112. }
  113. static void l2c_disable(void)
  114. {
  115. void __iomem *base = l2x0_base;
  116. l2x0_pmu_suspend();
  117. outer_cache.flush_all();
  118. l2c_write_sec(0, base, L2X0_CTRL);
  119. dsb(st);
  120. }
  121. static void l2c_save(void __iomem *base)
  122. {
  123. l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  124. }
  125. static void l2c_resume(void)
  126. {
  127. void __iomem *base = l2x0_base;
  128. /* Do not touch the controller if already enabled. */
  129. if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
  130. l2c_enable(base, l2x0_data->num_lock);
  131. l2x0_pmu_resume();
  132. }
  133. /*
  134. * L2C-210 specific code.
  135. *
  136. * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
  137. * ensure that no background operation is running. The way operations
  138. * are all background tasks.
  139. *
  140. * While a background operation is in progress, any new operation is
  141. * ignored (unspecified whether this causes an error.) Thankfully, not
  142. * used on SMP.
  143. *
  144. * Never has a different sync register other than L2X0_CACHE_SYNC, but
  145. * we use sync_reg_offset here so we can share some of this with L2C-310.
  146. */
  147. static void __l2c210_cache_sync(void __iomem *base)
  148. {
  149. writel_relaxed(0, base + sync_reg_offset);
  150. }
  151. static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
  152. unsigned long end)
  153. {
  154. while (start < end) {
  155. writel_relaxed(start, reg);
  156. start += CACHE_LINE_SIZE;
  157. }
  158. }
  159. static void l2c210_inv_range(unsigned long start, unsigned long end)
  160. {
  161. void __iomem *base = l2x0_base;
  162. if (start & (CACHE_LINE_SIZE - 1)) {
  163. start &= ~(CACHE_LINE_SIZE - 1);
  164. writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
  165. start += CACHE_LINE_SIZE;
  166. }
  167. if (end & (CACHE_LINE_SIZE - 1)) {
  168. end &= ~(CACHE_LINE_SIZE - 1);
  169. writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
  170. }
  171. __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
  172. __l2c210_cache_sync(base);
  173. }
  174. static void l2c210_clean_range(unsigned long start, unsigned long end)
  175. {
  176. void __iomem *base = l2x0_base;
  177. start &= ~(CACHE_LINE_SIZE - 1);
  178. __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
  179. __l2c210_cache_sync(base);
  180. }
  181. static void l2c210_flush_range(unsigned long start, unsigned long end)
  182. {
  183. void __iomem *base = l2x0_base;
  184. start &= ~(CACHE_LINE_SIZE - 1);
  185. __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
  186. __l2c210_cache_sync(base);
  187. }
  188. static void l2c210_flush_all(void)
  189. {
  190. void __iomem *base = l2x0_base;
  191. BUG_ON(!irqs_disabled());
  192. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  193. __l2c210_cache_sync(base);
  194. }
  195. static void l2c210_sync(void)
  196. {
  197. __l2c210_cache_sync(l2x0_base);
  198. }
  199. static const struct l2c_init_data l2c210_data __initconst = {
  200. .type = "L2C-210",
  201. .way_size_0 = SZ_8K,
  202. .num_lock = 1,
  203. .enable = l2c_enable,
  204. .save = l2c_save,
  205. .configure = l2c_configure,
  206. .unlock = l2c_unlock,
  207. .outer_cache = {
  208. .inv_range = l2c210_inv_range,
  209. .clean_range = l2c210_clean_range,
  210. .flush_range = l2c210_flush_range,
  211. .flush_all = l2c210_flush_all,
  212. .disable = l2c_disable,
  213. .sync = l2c210_sync,
  214. .resume = l2c_resume,
  215. },
  216. };
  217. /*
  218. * L2C-220 specific code.
  219. *
  220. * All operations are background operations: they have to be waited for.
  221. * Conflicting requests generate a slave error (which will cause an
  222. * imprecise abort.) Never uses sync_reg_offset, so we hard-code the
  223. * sync register here.
  224. *
  225. * However, we can re-use the l2c210_resume call.
  226. */
  227. static inline void __l2c220_cache_sync(void __iomem *base)
  228. {
  229. writel_relaxed(0, base + L2X0_CACHE_SYNC);
  230. l2c_wait_mask(base + L2X0_CACHE_SYNC, 1);
  231. }
  232. static void l2c220_op_way(void __iomem *base, unsigned reg)
  233. {
  234. unsigned long flags;
  235. raw_spin_lock_irqsave(&l2x0_lock, flags);
  236. __l2c_op_way(base + reg);
  237. __l2c220_cache_sync(base);
  238. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  239. }
  240. static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
  241. unsigned long end, unsigned long flags)
  242. {
  243. raw_spinlock_t *lock = &l2x0_lock;
  244. while (start < end) {
  245. unsigned long blk_end = start + min(end - start, 4096UL);
  246. while (start < blk_end) {
  247. l2c_wait_mask(reg, 1);
  248. writel_relaxed(start, reg);
  249. start += CACHE_LINE_SIZE;
  250. }
  251. if (blk_end < end) {
  252. raw_spin_unlock_irqrestore(lock, flags);
  253. raw_spin_lock_irqsave(lock, flags);
  254. }
  255. }
  256. return flags;
  257. }
  258. static void l2c220_inv_range(unsigned long start, unsigned long end)
  259. {
  260. void __iomem *base = l2x0_base;
  261. unsigned long flags;
  262. raw_spin_lock_irqsave(&l2x0_lock, flags);
  263. if ((start | end) & (CACHE_LINE_SIZE - 1)) {
  264. if (start & (CACHE_LINE_SIZE - 1)) {
  265. start &= ~(CACHE_LINE_SIZE - 1);
  266. writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
  267. start += CACHE_LINE_SIZE;
  268. }
  269. if (end & (CACHE_LINE_SIZE - 1)) {
  270. end &= ~(CACHE_LINE_SIZE - 1);
  271. l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
  272. writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
  273. }
  274. }
  275. flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA,
  276. start, end, flags);
  277. l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
  278. __l2c220_cache_sync(base);
  279. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  280. }
  281. static void l2c220_clean_range(unsigned long start, unsigned long end)
  282. {
  283. void __iomem *base = l2x0_base;
  284. unsigned long flags;
  285. start &= ~(CACHE_LINE_SIZE - 1);
  286. if ((end - start) >= l2x0_size) {
  287. l2c220_op_way(base, L2X0_CLEAN_WAY);
  288. return;
  289. }
  290. raw_spin_lock_irqsave(&l2x0_lock, flags);
  291. flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
  292. start, end, flags);
  293. l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
  294. __l2c220_cache_sync(base);
  295. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  296. }
  297. static void l2c220_flush_range(unsigned long start, unsigned long end)
  298. {
  299. void __iomem *base = l2x0_base;
  300. unsigned long flags;
  301. start &= ~(CACHE_LINE_SIZE - 1);
  302. if ((end - start) >= l2x0_size) {
  303. l2c220_op_way(base, L2X0_CLEAN_INV_WAY);
  304. return;
  305. }
  306. raw_spin_lock_irqsave(&l2x0_lock, flags);
  307. flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
  308. start, end, flags);
  309. l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
  310. __l2c220_cache_sync(base);
  311. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  312. }
  313. static void l2c220_flush_all(void)
  314. {
  315. l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
  316. }
  317. static void l2c220_sync(void)
  318. {
  319. unsigned long flags;
  320. raw_spin_lock_irqsave(&l2x0_lock, flags);
  321. __l2c220_cache_sync(l2x0_base);
  322. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  323. }
  324. static void l2c220_enable(void __iomem *base, unsigned num_lock)
  325. {
  326. /*
  327. * Always enable non-secure access to the lockdown registers -
  328. * we write to them as part of the L2C enable sequence so they
  329. * need to be accessible.
  330. */
  331. l2x0_saved_regs.aux_ctrl |= L220_AUX_CTRL_NS_LOCKDOWN;
  332. l2c_enable(base, num_lock);
  333. }
  334. static void l2c220_unlock(void __iomem *base, unsigned num_lock)
  335. {
  336. if (readl_relaxed(base + L2X0_AUX_CTRL) & L220_AUX_CTRL_NS_LOCKDOWN)
  337. l2c_unlock(base, num_lock);
  338. }
  339. static const struct l2c_init_data l2c220_data = {
  340. .type = "L2C-220",
  341. .way_size_0 = SZ_8K,
  342. .num_lock = 1,
  343. .enable = l2c220_enable,
  344. .save = l2c_save,
  345. .configure = l2c_configure,
  346. .unlock = l2c220_unlock,
  347. .outer_cache = {
  348. .inv_range = l2c220_inv_range,
  349. .clean_range = l2c220_clean_range,
  350. .flush_range = l2c220_flush_range,
  351. .flush_all = l2c220_flush_all,
  352. .disable = l2c_disable,
  353. .sync = l2c220_sync,
  354. .resume = l2c_resume,
  355. },
  356. };
  357. /*
  358. * L2C-310 specific code.
  359. *
  360. * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
  361. * and the way operations are all background tasks. However, issuing an
  362. * operation while a background operation is in progress results in a
  363. * SLVERR response. We can reuse:
  364. *
  365. * __l2c210_cache_sync (using sync_reg_offset)
  366. * l2c210_sync
  367. * l2c210_inv_range (if 588369 is not applicable)
  368. * l2c210_clean_range
  369. * l2c210_flush_range (if 588369 is not applicable)
  370. * l2c210_flush_all (if 727915 is not applicable)
  371. *
  372. * Errata:
  373. * 588369: PL310 R0P0->R1P0, fixed R2P0.
  374. * Affects: all clean+invalidate operations
  375. * clean and invalidate skips the invalidate step, so we need to issue
  376. * separate operations. We also require the above debug workaround
  377. * enclosing this code fragment on affected parts. On unaffected parts,
  378. * we must not use this workaround without the debug register writes
  379. * to avoid exposing a problem similar to 727915.
  380. *
  381. * 727915: PL310 R2P0->R3P0, fixed R3P1.
  382. * Affects: clean+invalidate by way
  383. * clean and invalidate by way runs in the background, and a store can
  384. * hit the line between the clean operation and invalidate operation,
  385. * resulting in the store being lost.
  386. *
  387. * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
  388. * Affects: 8x64-bit (double fill) line fetches
  389. * double fill line fetches can fail to cause dirty data to be evicted
  390. * from the cache before the new data overwrites the second line.
  391. *
  392. * 753970: PL310 R3P0, fixed R3P1.
  393. * Affects: sync
  394. * prevents merging writes after the sync operation, until another L2C
  395. * operation is performed (or a number of other conditions.)
  396. *
  397. * 769419: PL310 R0P0->R3P1, fixed R3P2.
  398. * Affects: store buffer
  399. * store buffer is not automatically drained.
  400. */
  401. static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
  402. {
  403. void __iomem *base = l2x0_base;
  404. if ((start | end) & (CACHE_LINE_SIZE - 1)) {
  405. unsigned long flags;
  406. /* Erratum 588369 for both clean+invalidate operations */
  407. raw_spin_lock_irqsave(&l2x0_lock, flags);
  408. l2c_set_debug(base, 0x03);
  409. if (start & (CACHE_LINE_SIZE - 1)) {
  410. start &= ~(CACHE_LINE_SIZE - 1);
  411. writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
  412. writel_relaxed(start, base + L2X0_INV_LINE_PA);
  413. start += CACHE_LINE_SIZE;
  414. }
  415. if (end & (CACHE_LINE_SIZE - 1)) {
  416. end &= ~(CACHE_LINE_SIZE - 1);
  417. writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
  418. writel_relaxed(end, base + L2X0_INV_LINE_PA);
  419. }
  420. l2c_set_debug(base, 0x00);
  421. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  422. }
  423. __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
  424. __l2c210_cache_sync(base);
  425. }
  426. static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
  427. {
  428. raw_spinlock_t *lock = &l2x0_lock;
  429. unsigned long flags;
  430. void __iomem *base = l2x0_base;
  431. raw_spin_lock_irqsave(lock, flags);
  432. while (start < end) {
  433. unsigned long blk_end = start + min(end - start, 4096UL);
  434. l2c_set_debug(base, 0x03);
  435. while (start < blk_end) {
  436. writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
  437. writel_relaxed(start, base + L2X0_INV_LINE_PA);
  438. start += CACHE_LINE_SIZE;
  439. }
  440. l2c_set_debug(base, 0x00);
  441. if (blk_end < end) {
  442. raw_spin_unlock_irqrestore(lock, flags);
  443. raw_spin_lock_irqsave(lock, flags);
  444. }
  445. }
  446. raw_spin_unlock_irqrestore(lock, flags);
  447. __l2c210_cache_sync(base);
  448. }
  449. static void l2c310_flush_all_erratum(void)
  450. {
  451. void __iomem *base = l2x0_base;
  452. unsigned long flags;
  453. raw_spin_lock_irqsave(&l2x0_lock, flags);
  454. l2c_set_debug(base, 0x03);
  455. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  456. l2c_set_debug(base, 0x00);
  457. __l2c210_cache_sync(base);
  458. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  459. }
  460. static void __init l2c310_save(void __iomem *base)
  461. {
  462. unsigned revision;
  463. l2c_save(base);
  464. l2x0_saved_regs.tag_latency = readl_relaxed(base +
  465. L310_TAG_LATENCY_CTRL);
  466. l2x0_saved_regs.data_latency = readl_relaxed(base +
  467. L310_DATA_LATENCY_CTRL);
  468. l2x0_saved_regs.filter_end = readl_relaxed(base +
  469. L310_ADDR_FILTER_END);
  470. l2x0_saved_regs.filter_start = readl_relaxed(base +
  471. L310_ADDR_FILTER_START);
  472. revision = readl_relaxed(base + L2X0_CACHE_ID) &
  473. L2X0_CACHE_ID_RTL_MASK;
  474. /* From r2p0, there is Prefetch offset/control register */
  475. if (revision >= L310_CACHE_ID_RTL_R2P0)
  476. l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
  477. L310_PREFETCH_CTRL);
  478. /* From r3p0, there is Power control register */
  479. if (revision >= L310_CACHE_ID_RTL_R3P0)
  480. l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
  481. L310_POWER_CTRL);
  482. }
  483. static void l2c310_configure(void __iomem *base)
  484. {
  485. unsigned revision;
  486. l2c_configure(base);
  487. /* restore pl310 setup */
  488. l2c_write_sec(l2x0_saved_regs.tag_latency, base,
  489. L310_TAG_LATENCY_CTRL);
  490. l2c_write_sec(l2x0_saved_regs.data_latency, base,
  491. L310_DATA_LATENCY_CTRL);
  492. l2c_write_sec(l2x0_saved_regs.filter_end, base,
  493. L310_ADDR_FILTER_END);
  494. l2c_write_sec(l2x0_saved_regs.filter_start, base,
  495. L310_ADDR_FILTER_START);
  496. revision = readl_relaxed(base + L2X0_CACHE_ID) &
  497. L2X0_CACHE_ID_RTL_MASK;
  498. if (revision >= L310_CACHE_ID_RTL_R2P0)
  499. l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
  500. L310_PREFETCH_CTRL);
  501. if (revision >= L310_CACHE_ID_RTL_R3P0)
  502. l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
  503. L310_POWER_CTRL);
  504. }
  505. static int l2c310_starting_cpu(unsigned int cpu)
  506. {
  507. set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
  508. return 0;
  509. }
  510. static int l2c310_dying_cpu(unsigned int cpu)
  511. {
  512. set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
  513. return 0;
  514. }
  515. static void __init l2c310_enable(void __iomem *base, unsigned num_lock)
  516. {
  517. unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK;
  518. bool cortex_a9 = read_cpuid_part() == ARM_CPU_PART_CORTEX_A9;
  519. u32 aux = l2x0_saved_regs.aux_ctrl;
  520. if (rev >= L310_CACHE_ID_RTL_R2P0) {
  521. if (cortex_a9 && !l2x0_bresp_disable) {
  522. aux |= L310_AUX_CTRL_EARLY_BRESP;
  523. pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
  524. } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
  525. pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n");
  526. aux &= ~L310_AUX_CTRL_EARLY_BRESP;
  527. }
  528. }
  529. if (cortex_a9 && !l2x0_flz_disable) {
  530. u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
  531. u32 acr = get_auxcr();
  532. pr_debug("Cortex-A9 ACR=0x%08x\n", acr);
  533. if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO))
  534. pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n");
  535. if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3)))
  536. pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n");
  537. if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) {
  538. aux |= L310_AUX_CTRL_FULL_LINE_ZERO;
  539. pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n");
  540. }
  541. } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) {
  542. pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n");
  543. aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
  544. }
  545. /*
  546. * Always enable non-secure access to the lockdown registers -
  547. * we write to them as part of the L2C enable sequence so they
  548. * need to be accessible.
  549. */
  550. l2x0_saved_regs.aux_ctrl = aux | L310_AUX_CTRL_NS_LOCKDOWN;
  551. l2c_enable(base, num_lock);
  552. /* Read back resulting AUX_CTRL value as it could have been altered. */
  553. aux = readl_relaxed(base + L2X0_AUX_CTRL);
  554. if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) {
  555. u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL);
  556. pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n",
  557. aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "",
  558. aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "",
  559. 1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK));
  560. }
  561. /* r3p0 or later has power control register */
  562. if (rev >= L310_CACHE_ID_RTL_R3P0) {
  563. u32 power_ctrl;
  564. power_ctrl = readl_relaxed(base + L310_POWER_CTRL);
  565. pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n",
  566. power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis",
  567. power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
  568. }
  569. if (aux & L310_AUX_CTRL_FULL_LINE_ZERO)
  570. cpuhp_setup_state(CPUHP_AP_ARM_L2X0_STARTING,
  571. "arm/l2x0:starting", l2c310_starting_cpu,
  572. l2c310_dying_cpu);
  573. }
  574. static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
  575. struct outer_cache_fns *fns)
  576. {
  577. unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
  578. const char *errata[8];
  579. unsigned n = 0;
  580. if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) &&
  581. revision < L310_CACHE_ID_RTL_R2P0 &&
  582. /* For bcm compatibility */
  583. fns->inv_range == l2c210_inv_range) {
  584. fns->inv_range = l2c310_inv_range_erratum;
  585. fns->flush_range = l2c310_flush_range_erratum;
  586. errata[n++] = "588369";
  587. }
  588. if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) &&
  589. revision >= L310_CACHE_ID_RTL_R2P0 &&
  590. revision < L310_CACHE_ID_RTL_R3P1) {
  591. fns->flush_all = l2c310_flush_all_erratum;
  592. errata[n++] = "727915";
  593. }
  594. if (revision >= L310_CACHE_ID_RTL_R3P0 &&
  595. revision < L310_CACHE_ID_RTL_R3P2) {
  596. u32 val = l2x0_saved_regs.prefetch_ctrl;
  597. if (val & L310_PREFETCH_CTRL_DBL_LINEFILL) {
  598. val &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
  599. l2x0_saved_regs.prefetch_ctrl = val;
  600. errata[n++] = "752271";
  601. }
  602. }
  603. if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
  604. revision == L310_CACHE_ID_RTL_R3P0) {
  605. sync_reg_offset = L2X0_DUMMY_REG;
  606. errata[n++] = "753970";
  607. }
  608. if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
  609. errata[n++] = "769419";
  610. if (n) {
  611. unsigned i;
  612. pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
  613. for (i = 0; i < n; i++)
  614. pr_cont(" %s", errata[i]);
  615. pr_cont(" enabled\n");
  616. }
  617. }
  618. static void l2c310_disable(void)
  619. {
  620. /*
  621. * If full-line-of-zeros is enabled, we must first disable it in the
  622. * Cortex-A9 auxiliary control register before disabling the L2 cache.
  623. */
  624. if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
  625. set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
  626. l2c_disable();
  627. }
  628. static void l2c310_resume(void)
  629. {
  630. l2c_resume();
  631. /* Re-enable full-line-of-zeros for Cortex-A9 */
  632. if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
  633. set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
  634. }
  635. static void l2c310_unlock(void __iomem *base, unsigned num_lock)
  636. {
  637. if (readl_relaxed(base + L2X0_AUX_CTRL) & L310_AUX_CTRL_NS_LOCKDOWN)
  638. l2c_unlock(base, num_lock);
  639. }
  640. static const struct l2c_init_data l2c310_init_fns __initconst = {
  641. .type = "L2C-310",
  642. .way_size_0 = SZ_8K,
  643. .num_lock = 8,
  644. .enable = l2c310_enable,
  645. .fixup = l2c310_fixup,
  646. .save = l2c310_save,
  647. .configure = l2c310_configure,
  648. .unlock = l2c310_unlock,
  649. .outer_cache = {
  650. .inv_range = l2c210_inv_range,
  651. .clean_range = l2c210_clean_range,
  652. .flush_range = l2c210_flush_range,
  653. .flush_all = l2c210_flush_all,
  654. .disable = l2c310_disable,
  655. .sync = l2c210_sync,
  656. .resume = l2c310_resume,
  657. },
  658. };
  659. static int __init __l2c_init(const struct l2c_init_data *data,
  660. u32 aux_val, u32 aux_mask, u32 cache_id, bool nosync)
  661. {
  662. struct outer_cache_fns fns;
  663. unsigned way_size_bits, ways;
  664. u32 aux, old_aux;
  665. /*
  666. * Save the pointer globally so that callbacks which do not receive
  667. * context from callers can access the structure.
  668. */
  669. l2x0_data = kmemdup(data, sizeof(*data), GFP_KERNEL);
  670. if (!l2x0_data)
  671. return -ENOMEM;
  672. /*
  673. * Sanity check the aux values. aux_mask is the bits we preserve
  674. * from reading the hardware register, and aux_val is the bits we
  675. * set.
  676. */
  677. if (aux_val & aux_mask)
  678. pr_alert("L2C: platform provided aux values permit register corruption.\n");
  679. old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  680. aux &= aux_mask;
  681. aux |= aux_val;
  682. if (old_aux != aux)
  683. pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n",
  684. old_aux, aux);
  685. /* Determine the number of ways */
  686. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  687. case L2X0_CACHE_ID_PART_L310:
  688. if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16))
  689. pr_warn("L2C: DT/platform tries to modify or specify cache size\n");
  690. if (aux & (1 << 16))
  691. ways = 16;
  692. else
  693. ways = 8;
  694. break;
  695. case L2X0_CACHE_ID_PART_L210:
  696. case L2X0_CACHE_ID_PART_L220:
  697. ways = (aux >> 13) & 0xf;
  698. break;
  699. case AURORA_CACHE_ID:
  700. ways = (aux >> 13) & 0xf;
  701. ways = 2 << ((ways + 1) >> 2);
  702. break;
  703. default:
  704. /* Assume unknown chips have 8 ways */
  705. ways = 8;
  706. break;
  707. }
  708. l2x0_way_mask = (1 << ways) - 1;
  709. /*
  710. * way_size_0 is the size that a way_size value of zero would be
  711. * given the calculation: way_size = way_size_0 << way_size_bits.
  712. * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k,
  713. * then way_size_0 would be 8k.
  714. *
  715. * L2 cache size = number of ways * way size.
  716. */
  717. way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
  718. L2C_AUX_CTRL_WAY_SIZE_SHIFT;
  719. l2x0_size = ways * (data->way_size_0 << way_size_bits);
  720. fns = data->outer_cache;
  721. fns.write_sec = outer_cache.write_sec;
  722. fns.configure = outer_cache.configure;
  723. if (data->fixup)
  724. data->fixup(l2x0_base, cache_id, &fns);
  725. if (nosync) {
  726. pr_info("L2C: disabling outer sync\n");
  727. fns.sync = NULL;
  728. }
  729. /*
  730. * Check if l2x0 controller is already enabled. If we are booting
  731. * in non-secure mode accessing the below registers will fault.
  732. */
  733. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  734. l2x0_saved_regs.aux_ctrl = aux;
  735. data->enable(l2x0_base, data->num_lock);
  736. }
  737. outer_cache = fns;
  738. /*
  739. * It is strange to save the register state before initialisation,
  740. * but hey, this is what the DT implementations decided to do.
  741. */
  742. if (data->save)
  743. data->save(l2x0_base);
  744. /* Re-read it in case some bits are reserved. */
  745. aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  746. pr_info("%s cache controller enabled, %d ways, %d kB\n",
  747. data->type, ways, l2x0_size >> 10);
  748. pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
  749. data->type, cache_id, aux);
  750. l2x0_pmu_register(l2x0_base, cache_id);
  751. return 0;
  752. }
  753. void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
  754. {
  755. const struct l2c_init_data *data;
  756. u32 cache_id;
  757. l2x0_base = base;
  758. cache_id = readl_relaxed(base + L2X0_CACHE_ID);
  759. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  760. default:
  761. case L2X0_CACHE_ID_PART_L210:
  762. data = &l2c210_data;
  763. break;
  764. case L2X0_CACHE_ID_PART_L220:
  765. data = &l2c220_data;
  766. break;
  767. case L2X0_CACHE_ID_PART_L310:
  768. data = &l2c310_init_fns;
  769. break;
  770. }
  771. /* Read back current (default) hardware configuration */
  772. if (data->save)
  773. data->save(l2x0_base);
  774. __l2c_init(data, aux_val, aux_mask, cache_id, false);
  775. }
  776. #ifdef CONFIG_OF
  777. static int l2_wt_override;
  778. /* Aurora don't have the cache ID register available, so we have to
  779. * pass it though the device tree */
  780. static u32 cache_id_part_number_from_dt;
  781. /**
  782. * l2x0_cache_size_of_parse() - read cache size parameters from DT
  783. * @np: the device tree node for the l2 cache
  784. * @aux_val: pointer to machine-supplied auxilary register value, to
  785. * be augmented by the call (bits to be set to 1)
  786. * @aux_mask: pointer to machine-supplied auxilary register mask, to
  787. * be augmented by the call (bits to be set to 0)
  788. * @associativity: variable to return the calculated associativity in
  789. * @max_way_size: the maximum size in bytes for the cache ways
  790. */
  791. static int __init l2x0_cache_size_of_parse(const struct device_node *np,
  792. u32 *aux_val, u32 *aux_mask,
  793. u32 *associativity,
  794. u32 max_way_size)
  795. {
  796. u32 mask = 0, val = 0;
  797. u32 cache_size = 0, sets = 0;
  798. u32 way_size_bits = 1;
  799. u32 way_size = 0;
  800. u32 block_size = 0;
  801. u32 line_size = 0;
  802. of_property_read_u32(np, "cache-size", &cache_size);
  803. of_property_read_u32(np, "cache-sets", &sets);
  804. of_property_read_u32(np, "cache-block-size", &block_size);
  805. of_property_read_u32(np, "cache-line-size", &line_size);
  806. if (!cache_size || !sets)
  807. return -ENODEV;
  808. /* All these l2 caches have the same line = block size actually */
  809. if (!line_size) {
  810. if (block_size) {
  811. /* If linesize is not given, it is equal to blocksize */
  812. line_size = block_size;
  813. } else {
  814. /* Fall back to known size */
  815. pr_warn("L2C OF: no cache block/line size given: "
  816. "falling back to default size %d bytes\n",
  817. CACHE_LINE_SIZE);
  818. line_size = CACHE_LINE_SIZE;
  819. }
  820. }
  821. if (line_size != CACHE_LINE_SIZE)
  822. pr_warn("L2C OF: DT supplied line size %d bytes does "
  823. "not match hardware line size of %d bytes\n",
  824. line_size,
  825. CACHE_LINE_SIZE);
  826. /*
  827. * Since:
  828. * set size = cache size / sets
  829. * ways = cache size / (sets * line size)
  830. * way size = cache size / (cache size / (sets * line size))
  831. * way size = sets * line size
  832. * associativity = ways = cache size / way size
  833. */
  834. way_size = sets * line_size;
  835. *associativity = cache_size / way_size;
  836. if (way_size > max_way_size) {
  837. pr_err("L2C OF: set size %dKB is too large\n", way_size);
  838. return -EINVAL;
  839. }
  840. pr_info("L2C OF: override cache size: %d bytes (%dKB)\n",
  841. cache_size, cache_size >> 10);
  842. pr_info("L2C OF: override line size: %d bytes\n", line_size);
  843. pr_info("L2C OF: override way size: %d bytes (%dKB)\n",
  844. way_size, way_size >> 10);
  845. pr_info("L2C OF: override associativity: %d\n", *associativity);
  846. /*
  847. * Calculates the bits 17:19 to set for way size:
  848. * 512KB -> 6, 256KB -> 5, ... 16KB -> 1
  849. */
  850. way_size_bits = ilog2(way_size >> 10) - 3;
  851. if (way_size_bits < 1 || way_size_bits > 6) {
  852. pr_err("L2C OF: cache way size illegal: %dKB is not mapped\n",
  853. way_size);
  854. return -EINVAL;
  855. }
  856. mask |= L2C_AUX_CTRL_WAY_SIZE_MASK;
  857. val |= (way_size_bits << L2C_AUX_CTRL_WAY_SIZE_SHIFT);
  858. *aux_val &= ~mask;
  859. *aux_val |= val;
  860. *aux_mask &= ~mask;
  861. return 0;
  862. }
  863. static void __init l2x0_of_parse(const struct device_node *np,
  864. u32 *aux_val, u32 *aux_mask)
  865. {
  866. u32 data[2] = { 0, 0 };
  867. u32 tag = 0;
  868. u32 dirty = 0;
  869. u32 val = 0, mask = 0;
  870. u32 assoc;
  871. int ret;
  872. of_property_read_u32(np, "arm,tag-latency", &tag);
  873. if (tag) {
  874. mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
  875. val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
  876. }
  877. of_property_read_u32_array(np, "arm,data-latency",
  878. data, ARRAY_SIZE(data));
  879. if (data[0] && data[1]) {
  880. mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
  881. L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
  882. val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
  883. ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
  884. }
  885. of_property_read_u32(np, "arm,dirty-latency", &dirty);
  886. if (dirty) {
  887. mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
  888. val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
  889. }
  890. if (of_property_read_bool(np, "arm,parity-enable")) {
  891. mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
  892. val |= L2C_AUX_CTRL_PARITY_ENABLE;
  893. } else if (of_property_read_bool(np, "arm,parity-disable")) {
  894. mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
  895. }
  896. if (of_property_read_bool(np, "arm,shared-override")) {
  897. mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
  898. val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
  899. }
  900. ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_256K);
  901. if (ret)
  902. return;
  903. if (assoc > 8) {
  904. pr_err("l2x0 of: cache setting yield too high associativity\n");
  905. pr_err("l2x0 of: %d calculated, max 8\n", assoc);
  906. } else {
  907. mask |= L2X0_AUX_CTRL_ASSOC_MASK;
  908. val |= (assoc << L2X0_AUX_CTRL_ASSOC_SHIFT);
  909. }
  910. *aux_val &= ~mask;
  911. *aux_val |= val;
  912. *aux_mask &= ~mask;
  913. }
  914. static const struct l2c_init_data of_l2c210_data __initconst = {
  915. .type = "L2C-210",
  916. .way_size_0 = SZ_8K,
  917. .num_lock = 1,
  918. .of_parse = l2x0_of_parse,
  919. .enable = l2c_enable,
  920. .save = l2c_save,
  921. .configure = l2c_configure,
  922. .unlock = l2c_unlock,
  923. .outer_cache = {
  924. .inv_range = l2c210_inv_range,
  925. .clean_range = l2c210_clean_range,
  926. .flush_range = l2c210_flush_range,
  927. .flush_all = l2c210_flush_all,
  928. .disable = l2c_disable,
  929. .sync = l2c210_sync,
  930. .resume = l2c_resume,
  931. },
  932. };
  933. static const struct l2c_init_data of_l2c220_data __initconst = {
  934. .type = "L2C-220",
  935. .way_size_0 = SZ_8K,
  936. .num_lock = 1,
  937. .of_parse = l2x0_of_parse,
  938. .enable = l2c220_enable,
  939. .save = l2c_save,
  940. .configure = l2c_configure,
  941. .unlock = l2c220_unlock,
  942. .outer_cache = {
  943. .inv_range = l2c220_inv_range,
  944. .clean_range = l2c220_clean_range,
  945. .flush_range = l2c220_flush_range,
  946. .flush_all = l2c220_flush_all,
  947. .disable = l2c_disable,
  948. .sync = l2c220_sync,
  949. .resume = l2c_resume,
  950. },
  951. };
  952. static void __init l2c310_of_parse(const struct device_node *np,
  953. u32 *aux_val, u32 *aux_mask)
  954. {
  955. u32 data[3] = { 0, 0, 0 };
  956. u32 tag[3] = { 0, 0, 0 };
  957. u32 filter[2] = { 0, 0 };
  958. u32 assoc;
  959. u32 prefetch;
  960. u32 power;
  961. u32 val;
  962. int ret;
  963. of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
  964. if (tag[0] && tag[1] && tag[2])
  965. l2x0_saved_regs.tag_latency =
  966. L310_LATENCY_CTRL_RD(tag[0] - 1) |
  967. L310_LATENCY_CTRL_WR(tag[1] - 1) |
  968. L310_LATENCY_CTRL_SETUP(tag[2] - 1);
  969. of_property_read_u32_array(np, "arm,data-latency",
  970. data, ARRAY_SIZE(data));
  971. if (data[0] && data[1] && data[2])
  972. l2x0_saved_regs.data_latency =
  973. L310_LATENCY_CTRL_RD(data[0] - 1) |
  974. L310_LATENCY_CTRL_WR(data[1] - 1) |
  975. L310_LATENCY_CTRL_SETUP(data[2] - 1);
  976. of_property_read_u32_array(np, "arm,filter-ranges",
  977. filter, ARRAY_SIZE(filter));
  978. if (filter[1]) {
  979. l2x0_saved_regs.filter_end =
  980. ALIGN(filter[0] + filter[1], SZ_1M);
  981. l2x0_saved_regs.filter_start = (filter[0] & ~(SZ_1M - 1))
  982. | L310_ADDR_FILTER_EN;
  983. }
  984. ret = l2x0_cache_size_of_parse(np, aux_val, aux_mask, &assoc, SZ_512K);
  985. if (!ret) {
  986. switch (assoc) {
  987. case 16:
  988. *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  989. *aux_val |= L310_AUX_CTRL_ASSOCIATIVITY_16;
  990. *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  991. break;
  992. case 8:
  993. *aux_val &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  994. *aux_mask &= ~L2X0_AUX_CTRL_ASSOC_MASK;
  995. break;
  996. default:
  997. pr_err("L2C-310 OF cache associativity %d invalid, only 8 or 16 permitted\n",
  998. assoc);
  999. break;
  1000. }
  1001. }
  1002. if (of_property_read_bool(np, "arm,shared-override")) {
  1003. *aux_val |= L2C_AUX_CTRL_SHARED_OVERRIDE;
  1004. *aux_mask &= ~L2C_AUX_CTRL_SHARED_OVERRIDE;
  1005. }
  1006. if (of_property_read_bool(np, "arm,parity-enable")) {
  1007. *aux_val |= L2C_AUX_CTRL_PARITY_ENABLE;
  1008. *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
  1009. } else if (of_property_read_bool(np, "arm,parity-disable")) {
  1010. *aux_val &= ~L2C_AUX_CTRL_PARITY_ENABLE;
  1011. *aux_mask &= ~L2C_AUX_CTRL_PARITY_ENABLE;
  1012. }
  1013. if (of_property_read_bool(np, "arm,early-bresp-disable"))
  1014. l2x0_bresp_disable = true;
  1015. if (of_property_read_bool(np, "arm,full-line-zero-disable"))
  1016. l2x0_flz_disable = true;
  1017. prefetch = l2x0_saved_regs.prefetch_ctrl;
  1018. ret = of_property_read_u32(np, "arm,double-linefill", &val);
  1019. if (ret == 0) {
  1020. if (val)
  1021. prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL;
  1022. else
  1023. prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL;
  1024. } else if (ret != -EINVAL) {
  1025. pr_err("L2C-310 OF arm,double-linefill property value is missing\n");
  1026. }
  1027. ret = of_property_read_u32(np, "arm,double-linefill-incr", &val);
  1028. if (ret == 0) {
  1029. if (val)
  1030. prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
  1031. else
  1032. prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_INCR;
  1033. } else if (ret != -EINVAL) {
  1034. pr_err("L2C-310 OF arm,double-linefill-incr property value is missing\n");
  1035. }
  1036. ret = of_property_read_u32(np, "arm,double-linefill-wrap", &val);
  1037. if (ret == 0) {
  1038. if (!val)
  1039. prefetch |= L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
  1040. else
  1041. prefetch &= ~L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP;
  1042. } else if (ret != -EINVAL) {
  1043. pr_err("L2C-310 OF arm,double-linefill-wrap property value is missing\n");
  1044. }
  1045. ret = of_property_read_u32(np, "arm,prefetch-drop", &val);
  1046. if (ret == 0) {
  1047. if (val)
  1048. prefetch |= L310_PREFETCH_CTRL_PREFETCH_DROP;
  1049. else
  1050. prefetch &= ~L310_PREFETCH_CTRL_PREFETCH_DROP;
  1051. } else if (ret != -EINVAL) {
  1052. pr_err("L2C-310 OF arm,prefetch-drop property value is missing\n");
  1053. }
  1054. ret = of_property_read_u32(np, "arm,prefetch-offset", &val);
  1055. if (ret == 0) {
  1056. prefetch &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
  1057. prefetch |= val & L310_PREFETCH_CTRL_OFFSET_MASK;
  1058. } else if (ret != -EINVAL) {
  1059. pr_err("L2C-310 OF arm,prefetch-offset property value is missing\n");
  1060. }
  1061. ret = of_property_read_u32(np, "prefetch-data", &val);
  1062. if (ret == 0) {
  1063. if (val) {
  1064. prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH;
  1065. *aux_val |= L310_PREFETCH_CTRL_DATA_PREFETCH;
  1066. } else {
  1067. prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH;
  1068. *aux_val &= ~L310_PREFETCH_CTRL_DATA_PREFETCH;
  1069. }
  1070. *aux_mask &= ~L310_PREFETCH_CTRL_DATA_PREFETCH;
  1071. } else if (ret != -EINVAL) {
  1072. pr_err("L2C-310 OF prefetch-data property value is missing\n");
  1073. }
  1074. ret = of_property_read_u32(np, "prefetch-instr", &val);
  1075. if (ret == 0) {
  1076. if (val) {
  1077. prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1078. *aux_val |= L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1079. } else {
  1080. prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1081. *aux_val &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1082. }
  1083. *aux_mask &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH;
  1084. } else if (ret != -EINVAL) {
  1085. pr_err("L2C-310 OF prefetch-instr property value is missing\n");
  1086. }
  1087. l2x0_saved_regs.prefetch_ctrl = prefetch;
  1088. power = l2x0_saved_regs.pwr_ctrl |
  1089. L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN;
  1090. ret = of_property_read_u32(np, "arm,dynamic-clock-gating", &val);
  1091. if (!ret) {
  1092. if (!val)
  1093. power &= ~L310_DYNAMIC_CLK_GATING_EN;
  1094. } else if (ret != -EINVAL) {
  1095. pr_err("L2C-310 OF dynamic-clock-gating property value is missing or invalid\n");
  1096. }
  1097. ret = of_property_read_u32(np, "arm,standby-mode", &val);
  1098. if (!ret) {
  1099. if (!val)
  1100. power &= ~L310_STNDBY_MODE_EN;
  1101. } else if (ret != -EINVAL) {
  1102. pr_err("L2C-310 OF standby-mode property value is missing or invalid\n");
  1103. }
  1104. l2x0_saved_regs.pwr_ctrl = power;
  1105. }
  1106. static const struct l2c_init_data of_l2c310_data __initconst = {
  1107. .type = "L2C-310",
  1108. .way_size_0 = SZ_8K,
  1109. .num_lock = 8,
  1110. .of_parse = l2c310_of_parse,
  1111. .enable = l2c310_enable,
  1112. .fixup = l2c310_fixup,
  1113. .save = l2c310_save,
  1114. .configure = l2c310_configure,
  1115. .unlock = l2c310_unlock,
  1116. .outer_cache = {
  1117. .inv_range = l2c210_inv_range,
  1118. .clean_range = l2c210_clean_range,
  1119. .flush_range = l2c210_flush_range,
  1120. .flush_all = l2c210_flush_all,
  1121. .disable = l2c310_disable,
  1122. .sync = l2c210_sync,
  1123. .resume = l2c310_resume,
  1124. },
  1125. };
  1126. /*
  1127. * This is a variant of the of_l2c310_data with .sync set to
  1128. * NULL. Outer sync operations are not needed when the system is I/O
  1129. * coherent, and potentially harmful in certain situations (PCIe/PL310
  1130. * deadlock on Armada 375/38x due to hardware I/O coherency). The
  1131. * other operations are kept because they are infrequent (therefore do
  1132. * not cause the deadlock in practice) and needed for secondary CPU
  1133. * boot and other power management activities.
  1134. */
  1135. static const struct l2c_init_data of_l2c310_coherent_data __initconst = {
  1136. .type = "L2C-310 Coherent",
  1137. .way_size_0 = SZ_8K,
  1138. .num_lock = 8,
  1139. .of_parse = l2c310_of_parse,
  1140. .enable = l2c310_enable,
  1141. .fixup = l2c310_fixup,
  1142. .save = l2c310_save,
  1143. .configure = l2c310_configure,
  1144. .unlock = l2c310_unlock,
  1145. .outer_cache = {
  1146. .inv_range = l2c210_inv_range,
  1147. .clean_range = l2c210_clean_range,
  1148. .flush_range = l2c210_flush_range,
  1149. .flush_all = l2c210_flush_all,
  1150. .disable = l2c310_disable,
  1151. .resume = l2c310_resume,
  1152. },
  1153. };
  1154. /*
  1155. * Note that the end addresses passed to Linux primitives are
  1156. * noninclusive, while the hardware cache range operations use
  1157. * inclusive start and end addresses.
  1158. */
  1159. static unsigned long aurora_range_end(unsigned long start, unsigned long end)
  1160. {
  1161. /*
  1162. * Limit the number of cache lines processed at once,
  1163. * since cache range operations stall the CPU pipeline
  1164. * until completion.
  1165. */
  1166. if (end > start + AURORA_MAX_RANGE_SIZE)
  1167. end = start + AURORA_MAX_RANGE_SIZE;
  1168. /*
  1169. * Cache range operations can't straddle a page boundary.
  1170. */
  1171. if (end > PAGE_ALIGN(start+1))
  1172. end = PAGE_ALIGN(start+1);
  1173. return end;
  1174. }
  1175. static void aurora_pa_range(unsigned long start, unsigned long end,
  1176. unsigned long offset)
  1177. {
  1178. void __iomem *base = l2x0_base;
  1179. unsigned long range_end;
  1180. unsigned long flags;
  1181. /*
  1182. * round start and end adresses up to cache line size
  1183. */
  1184. start &= ~(CACHE_LINE_SIZE - 1);
  1185. end = ALIGN(end, CACHE_LINE_SIZE);
  1186. /*
  1187. * perform operation on all full cache lines between 'start' and 'end'
  1188. */
  1189. while (start < end) {
  1190. range_end = aurora_range_end(start, end);
  1191. raw_spin_lock_irqsave(&l2x0_lock, flags);
  1192. writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG);
  1193. writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset);
  1194. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  1195. writel_relaxed(0, base + AURORA_SYNC_REG);
  1196. start = range_end;
  1197. }
  1198. }
  1199. static void aurora_inv_range(unsigned long start, unsigned long end)
  1200. {
  1201. aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
  1202. }
  1203. static void aurora_clean_range(unsigned long start, unsigned long end)
  1204. {
  1205. /*
  1206. * If L2 is forced to WT, the L2 will always be clean and we
  1207. * don't need to do anything here.
  1208. */
  1209. if (!l2_wt_override)
  1210. aurora_pa_range(start, end, AURORA_CLEAN_RANGE_REG);
  1211. }
  1212. static void aurora_flush_range(unsigned long start, unsigned long end)
  1213. {
  1214. if (l2_wt_override)
  1215. aurora_pa_range(start, end, AURORA_INVAL_RANGE_REG);
  1216. else
  1217. aurora_pa_range(start, end, AURORA_FLUSH_RANGE_REG);
  1218. }
  1219. static void aurora_flush_all(void)
  1220. {
  1221. void __iomem *base = l2x0_base;
  1222. unsigned long flags;
  1223. /* clean all ways */
  1224. raw_spin_lock_irqsave(&l2x0_lock, flags);
  1225. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  1226. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  1227. writel_relaxed(0, base + AURORA_SYNC_REG);
  1228. }
  1229. static void aurora_cache_sync(void)
  1230. {
  1231. writel_relaxed(0, l2x0_base + AURORA_SYNC_REG);
  1232. }
  1233. static void aurora_disable(void)
  1234. {
  1235. void __iomem *base = l2x0_base;
  1236. unsigned long flags;
  1237. raw_spin_lock_irqsave(&l2x0_lock, flags);
  1238. __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
  1239. writel_relaxed(0, base + AURORA_SYNC_REG);
  1240. l2c_write_sec(0, base, L2X0_CTRL);
  1241. dsb(st);
  1242. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  1243. }
  1244. static void aurora_save(void __iomem *base)
  1245. {
  1246. l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
  1247. l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
  1248. }
  1249. /*
  1250. * For Aurora cache in no outer mode, enable via the CP15 coprocessor
  1251. * broadcasting of cache commands to L2.
  1252. */
  1253. static void __init aurora_enable_no_outer(void __iomem *base,
  1254. unsigned num_lock)
  1255. {
  1256. u32 u;
  1257. asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
  1258. u |= AURORA_CTRL_FW; /* Set the FW bit */
  1259. asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
  1260. isb();
  1261. l2c_enable(base, num_lock);
  1262. }
  1263. static void __init aurora_fixup(void __iomem *base, u32 cache_id,
  1264. struct outer_cache_fns *fns)
  1265. {
  1266. sync_reg_offset = AURORA_SYNC_REG;
  1267. }
  1268. static void __init aurora_of_parse(const struct device_node *np,
  1269. u32 *aux_val, u32 *aux_mask)
  1270. {
  1271. u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
  1272. u32 mask = AURORA_ACR_REPLACEMENT_MASK;
  1273. of_property_read_u32(np, "cache-id-part",
  1274. &cache_id_part_number_from_dt);
  1275. /* Determine and save the write policy */
  1276. l2_wt_override = of_property_read_bool(np, "wt-override");
  1277. if (l2_wt_override) {
  1278. val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
  1279. mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
  1280. }
  1281. if (of_property_read_bool(np, "marvell,ecc-enable")) {
  1282. mask |= AURORA_ACR_ECC_EN;
  1283. val |= AURORA_ACR_ECC_EN;
  1284. }
  1285. if (of_property_read_bool(np, "arm,parity-enable")) {
  1286. mask |= AURORA_ACR_PARITY_EN;
  1287. val |= AURORA_ACR_PARITY_EN;
  1288. } else if (of_property_read_bool(np, "arm,parity-disable")) {
  1289. mask |= AURORA_ACR_PARITY_EN;
  1290. }
  1291. *aux_val &= ~mask;
  1292. *aux_val |= val;
  1293. *aux_mask &= ~mask;
  1294. }
  1295. static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
  1296. .type = "Aurora",
  1297. .way_size_0 = SZ_4K,
  1298. .num_lock = 4,
  1299. .of_parse = aurora_of_parse,
  1300. .enable = l2c_enable,
  1301. .fixup = aurora_fixup,
  1302. .save = aurora_save,
  1303. .configure = l2c_configure,
  1304. .unlock = l2c_unlock,
  1305. .outer_cache = {
  1306. .inv_range = aurora_inv_range,
  1307. .clean_range = aurora_clean_range,
  1308. .flush_range = aurora_flush_range,
  1309. .flush_all = aurora_flush_all,
  1310. .disable = aurora_disable,
  1311. .sync = aurora_cache_sync,
  1312. .resume = l2c_resume,
  1313. },
  1314. };
  1315. static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
  1316. .type = "Aurora",
  1317. .way_size_0 = SZ_4K,
  1318. .num_lock = 4,
  1319. .of_parse = aurora_of_parse,
  1320. .enable = aurora_enable_no_outer,
  1321. .fixup = aurora_fixup,
  1322. .save = aurora_save,
  1323. .configure = l2c_configure,
  1324. .unlock = l2c_unlock,
  1325. .outer_cache = {
  1326. .resume = l2c_resume,
  1327. },
  1328. };
  1329. /*
  1330. * For certain Broadcom SoCs, depending on the address range, different offsets
  1331. * need to be added to the address before passing it to L2 for
  1332. * invalidation/clean/flush
  1333. *
  1334. * Section Address Range Offset EMI
  1335. * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC
  1336. * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS
  1337. * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC
  1338. *
  1339. * When the start and end addresses have crossed two different sections, we
  1340. * need to break the L2 operation into two, each within its own section.
  1341. * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
  1342. * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
  1343. * 0xC0000000 - 0xC0001000
  1344. *
  1345. * Note 1:
  1346. * By breaking a single L2 operation into two, we may potentially suffer some
  1347. * performance hit, but keep in mind the cross section case is very rare
  1348. *
  1349. * Note 2:
  1350. * We do not need to handle the case when the start address is in
  1351. * Section 1 and the end address is in Section 3, since it is not a valid use
  1352. * case
  1353. *
  1354. * Note 3:
  1355. * Section 1 in practical terms can no longer be used on rev A2. Because of
  1356. * that the code does not need to handle section 1 at all.
  1357. *
  1358. */
  1359. #define BCM_SYS_EMI_START_ADDR 0x40000000UL
  1360. #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL
  1361. #define BCM_SYS_EMI_OFFSET 0x40000000UL
  1362. #define BCM_VC_EMI_OFFSET 0x80000000UL
  1363. static inline int bcm_addr_is_sys_emi(unsigned long addr)
  1364. {
  1365. return (addr >= BCM_SYS_EMI_START_ADDR) &&
  1366. (addr < BCM_VC_EMI_SEC3_START_ADDR);
  1367. }
  1368. static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
  1369. {
  1370. if (bcm_addr_is_sys_emi(addr))
  1371. return addr + BCM_SYS_EMI_OFFSET;
  1372. else
  1373. return addr + BCM_VC_EMI_OFFSET;
  1374. }
  1375. static void bcm_inv_range(unsigned long start, unsigned long end)
  1376. {
  1377. unsigned long new_start, new_end;
  1378. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  1379. if (unlikely(end <= start))
  1380. return;
  1381. new_start = bcm_l2_phys_addr(start);
  1382. new_end = bcm_l2_phys_addr(end);
  1383. /* normal case, no cross section between start and end */
  1384. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  1385. l2c210_inv_range(new_start, new_end);
  1386. return;
  1387. }
  1388. /* They cross sections, so it can only be a cross from section
  1389. * 2 to section 3
  1390. */
  1391. l2c210_inv_range(new_start,
  1392. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  1393. l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  1394. new_end);
  1395. }
  1396. static void bcm_clean_range(unsigned long start, unsigned long end)
  1397. {
  1398. unsigned long new_start, new_end;
  1399. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  1400. if (unlikely(end <= start))
  1401. return;
  1402. new_start = bcm_l2_phys_addr(start);
  1403. new_end = bcm_l2_phys_addr(end);
  1404. /* normal case, no cross section between start and end */
  1405. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  1406. l2c210_clean_range(new_start, new_end);
  1407. return;
  1408. }
  1409. /* They cross sections, so it can only be a cross from section
  1410. * 2 to section 3
  1411. */
  1412. l2c210_clean_range(new_start,
  1413. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  1414. l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  1415. new_end);
  1416. }
  1417. static void bcm_flush_range(unsigned long start, unsigned long end)
  1418. {
  1419. unsigned long new_start, new_end;
  1420. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  1421. if (unlikely(end <= start))
  1422. return;
  1423. if ((end - start) >= l2x0_size) {
  1424. outer_cache.flush_all();
  1425. return;
  1426. }
  1427. new_start = bcm_l2_phys_addr(start);
  1428. new_end = bcm_l2_phys_addr(end);
  1429. /* normal case, no cross section between start and end */
  1430. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  1431. l2c210_flush_range(new_start, new_end);
  1432. return;
  1433. }
  1434. /* They cross sections, so it can only be a cross from section
  1435. * 2 to section 3
  1436. */
  1437. l2c210_flush_range(new_start,
  1438. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  1439. l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  1440. new_end);
  1441. }
  1442. /* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
  1443. static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
  1444. .type = "BCM-L2C-310",
  1445. .way_size_0 = SZ_8K,
  1446. .num_lock = 8,
  1447. .of_parse = l2c310_of_parse,
  1448. .enable = l2c310_enable,
  1449. .save = l2c310_save,
  1450. .configure = l2c310_configure,
  1451. .unlock = l2c310_unlock,
  1452. .outer_cache = {
  1453. .inv_range = bcm_inv_range,
  1454. .clean_range = bcm_clean_range,
  1455. .flush_range = bcm_flush_range,
  1456. .flush_all = l2c210_flush_all,
  1457. .disable = l2c310_disable,
  1458. .sync = l2c210_sync,
  1459. .resume = l2c310_resume,
  1460. },
  1461. };
  1462. static void __init tauros3_save(void __iomem *base)
  1463. {
  1464. l2c_save(base);
  1465. l2x0_saved_regs.aux2_ctrl =
  1466. readl_relaxed(base + TAUROS3_AUX2_CTRL);
  1467. l2x0_saved_regs.prefetch_ctrl =
  1468. readl_relaxed(base + L310_PREFETCH_CTRL);
  1469. }
  1470. static void tauros3_configure(void __iomem *base)
  1471. {
  1472. l2c_configure(base);
  1473. writel_relaxed(l2x0_saved_regs.aux2_ctrl,
  1474. base + TAUROS3_AUX2_CTRL);
  1475. writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
  1476. base + L310_PREFETCH_CTRL);
  1477. }
  1478. static const struct l2c_init_data of_tauros3_data __initconst = {
  1479. .type = "Tauros3",
  1480. .way_size_0 = SZ_8K,
  1481. .num_lock = 8,
  1482. .enable = l2c_enable,
  1483. .save = tauros3_save,
  1484. .configure = tauros3_configure,
  1485. .unlock = l2c_unlock,
  1486. /* Tauros3 broadcasts L1 cache operations to L2 */
  1487. .outer_cache = {
  1488. .resume = l2c_resume,
  1489. },
  1490. };
  1491. #define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
  1492. static const struct of_device_id l2x0_ids[] __initconst = {
  1493. L2C_ID("arm,l210-cache", of_l2c210_data),
  1494. L2C_ID("arm,l220-cache", of_l2c220_data),
  1495. L2C_ID("arm,pl310-cache", of_l2c310_data),
  1496. L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
  1497. L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data),
  1498. L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data),
  1499. L2C_ID("marvell,tauros3-cache", of_tauros3_data),
  1500. /* Deprecated IDs */
  1501. L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
  1502. {}
  1503. };
  1504. int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
  1505. {
  1506. const struct l2c_init_data *data;
  1507. struct device_node *np;
  1508. struct resource res;
  1509. u32 cache_id, old_aux;
  1510. u32 cache_level = 2;
  1511. bool nosync = false;
  1512. np = of_find_matching_node(NULL, l2x0_ids);
  1513. if (!np)
  1514. return -ENODEV;
  1515. if (of_address_to_resource(np, 0, &res))
  1516. return -ENODEV;
  1517. l2x0_base = ioremap(res.start, resource_size(&res));
  1518. if (!l2x0_base)
  1519. return -ENOMEM;
  1520. l2x0_saved_regs.phy_base = res.start;
  1521. data = of_match_node(l2x0_ids, np)->data;
  1522. if (of_device_is_compatible(np, "arm,pl310-cache") &&
  1523. of_property_read_bool(np, "arm,io-coherent"))
  1524. data = &of_l2c310_coherent_data;
  1525. old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  1526. if (old_aux != ((old_aux & aux_mask) | aux_val)) {
  1527. pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
  1528. old_aux, (old_aux & aux_mask) | aux_val);
  1529. } else if (aux_mask != ~0U && aux_val != 0) {
  1530. pr_alert("L2C: platform provided aux values match the hardware, so have no effect. Please remove them.\n");
  1531. }
  1532. /* All L2 caches are unified, so this property should be specified */
  1533. if (!of_property_read_bool(np, "cache-unified"))
  1534. pr_err("L2C: device tree omits to specify unified cache\n");
  1535. if (of_property_read_u32(np, "cache-level", &cache_level))
  1536. pr_err("L2C: device tree omits to specify cache-level\n");
  1537. if (cache_level != 2)
  1538. pr_err("L2C: device tree specifies invalid cache level\n");
  1539. nosync = of_property_read_bool(np, "arm,outer-sync-disable");
  1540. /* Read back current (default) hardware configuration */
  1541. if (data->save)
  1542. data->save(l2x0_base);
  1543. /* L2 configuration can only be changed if the cache is disabled */
  1544. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
  1545. if (data->of_parse)
  1546. data->of_parse(np, &aux_val, &aux_mask);
  1547. if (cache_id_part_number_from_dt)
  1548. cache_id = cache_id_part_number_from_dt;
  1549. else
  1550. cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
  1551. return __l2c_init(data, aux_val, aux_mask, cache_id, nosync);
  1552. }
  1553. #endif