slcr.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Xilinx SLCR driver
  4. *
  5. * Copyright (c) 2011-2013 Xilinx Inc.
  6. */
  7. #include <linux/io.h>
  8. #include <linux/reboot.h>
  9. #include <linux/mfd/syscon.h>
  10. #include <linux/of_address.h>
  11. #include <linux/regmap.h>
  12. #include <linux/clk/zynq.h>
  13. #include "common.h"
  14. /* register offsets */
  15. #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
  16. #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
  17. #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
  18. #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
  19. #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
  20. #define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
  21. #define SLCR_UNLOCK_MAGIC 0xDF0D
  22. #define SLCR_A9_CPU_CLKSTOP 0x10
  23. #define SLCR_A9_CPU_RST 0x1
  24. #define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
  25. #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
  26. static void __iomem *zynq_slcr_base;
  27. static struct regmap *zynq_slcr_regmap;
  28. /**
  29. * zynq_slcr_write - Write to a register in SLCR block
  30. *
  31. * @val: Value to write to the register
  32. * @offset: Register offset in SLCR block
  33. *
  34. * Return: a negative value on error, 0 on success
  35. */
  36. static int zynq_slcr_write(u32 val, u32 offset)
  37. {
  38. return regmap_write(zynq_slcr_regmap, offset, val);
  39. }
  40. /**
  41. * zynq_slcr_read - Read a register in SLCR block
  42. *
  43. * @val: Pointer to value to be read from SLCR
  44. * @offset: Register offset in SLCR block
  45. *
  46. * Return: a negative value on error, 0 on success
  47. */
  48. static int zynq_slcr_read(u32 *val, u32 offset)
  49. {
  50. return regmap_read(zynq_slcr_regmap, offset, val);
  51. }
  52. /**
  53. * zynq_slcr_unlock - Unlock SLCR registers
  54. *
  55. * Return: a negative value on error, 0 on success
  56. */
  57. static inline int zynq_slcr_unlock(void)
  58. {
  59. zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
  60. return 0;
  61. }
  62. /**
  63. * zynq_slcr_get_device_id - Read device code id
  64. *
  65. * Return: Device code id
  66. */
  67. u32 zynq_slcr_get_device_id(void)
  68. {
  69. u32 val;
  70. zynq_slcr_read(&val, SLCR_PSS_IDCODE);
  71. val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
  72. val &= SLCR_PSS_IDCODE_DEVICE_MASK;
  73. return val;
  74. }
  75. /**
  76. * zynq_slcr_system_restart - Restart the entire system.
  77. *
  78. * @nb: Pointer to restart notifier block (unused)
  79. * @action: Reboot mode (unused)
  80. * @data: Restart handler private data (unused)
  81. *
  82. * Return: 0 always
  83. */
  84. static
  85. int zynq_slcr_system_restart(struct notifier_block *nb,
  86. unsigned long action, void *data)
  87. {
  88. u32 reboot;
  89. /*
  90. * Clear 0x0F000000 bits of reboot status register to workaround
  91. * the FSBL not loading the bitstream after soft-reboot
  92. * This is a temporary solution until we know more.
  93. */
  94. zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
  95. zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
  96. zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
  97. return 0;
  98. }
  99. static struct notifier_block zynq_slcr_restart_nb = {
  100. .notifier_call = zynq_slcr_system_restart,
  101. .priority = 192,
  102. };
  103. /**
  104. * zynq_slcr_cpu_start - Start cpu
  105. * @cpu: cpu number
  106. */
  107. void zynq_slcr_cpu_start(int cpu)
  108. {
  109. u32 reg;
  110. zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
  111. reg &= ~(SLCR_A9_CPU_RST << cpu);
  112. zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
  113. reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
  114. zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
  115. zynq_slcr_cpu_state_write(cpu, false);
  116. }
  117. /**
  118. * zynq_slcr_cpu_stop - Stop cpu
  119. * @cpu: cpu number
  120. */
  121. void zynq_slcr_cpu_stop(int cpu)
  122. {
  123. u32 reg;
  124. zynq_slcr_read(&reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
  125. reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
  126. zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
  127. }
  128. /**
  129. * zynq_slcr_cpu_state - Read/write cpu state
  130. * @cpu: cpu number
  131. *
  132. * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
  133. * 0 means cpu is running, 1 cpu is going to die.
  134. *
  135. * Return: true if cpu is running, false if cpu is going to die
  136. */
  137. bool zynq_slcr_cpu_state_read(int cpu)
  138. {
  139. u32 state;
  140. state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
  141. state &= 1 << (31 - cpu);
  142. return !state;
  143. }
  144. /**
  145. * zynq_slcr_cpu_state - Read/write cpu state
  146. * @cpu: cpu number
  147. * @die: cpu state - true if cpu is going to die
  148. *
  149. * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1)
  150. * 0 means cpu is running, 1 cpu is going to die.
  151. */
  152. void zynq_slcr_cpu_state_write(int cpu, bool die)
  153. {
  154. u32 state, mask;
  155. state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
  156. mask = 1 << (31 - cpu);
  157. if (die)
  158. state |= mask;
  159. else
  160. state &= ~mask;
  161. writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
  162. }
  163. /**
  164. * zynq_early_slcr_init - Early slcr init function
  165. *
  166. * Return: 0 on success, negative errno otherwise.
  167. *
  168. * Called very early during boot from platform code to unlock SLCR.
  169. */
  170. int __init zynq_early_slcr_init(void)
  171. {
  172. struct device_node *np;
  173. np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr");
  174. if (!np) {
  175. pr_err("%s: no slcr node found\n", __func__);
  176. BUG();
  177. }
  178. zynq_slcr_base = of_iomap(np, 0);
  179. if (!zynq_slcr_base) {
  180. pr_err("%s: Unable to map I/O memory\n", __func__);
  181. BUG();
  182. }
  183. np->data = (__force void *)zynq_slcr_base;
  184. zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
  185. if (IS_ERR(zynq_slcr_regmap)) {
  186. pr_err("%s: failed to find zynq-slcr\n", __func__);
  187. of_node_put(np);
  188. return -ENODEV;
  189. }
  190. /* unlock the SLCR so that registers can be changed */
  191. zynq_slcr_unlock();
  192. /* See AR#54190 design advisory */
  193. regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202);
  194. register_restart_handler(&zynq_slcr_restart_nb);
  195. pr_info("%pOFn mapped to %p\n", np, zynq_slcr_base);
  196. of_node_put(np);
  197. return 0;
  198. }