reset.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * arch/arm/mach-tegra/reset.h
  4. *
  5. * CPU reset dispatcher.
  6. *
  7. * Copyright (c) 2011, NVIDIA Corporation.
  8. */
  9. #ifndef __MACH_TEGRA_RESET_H
  10. #define __MACH_TEGRA_RESET_H
  11. #define TEGRA_RESET_MASK_PRESENT 0
  12. #define TEGRA_RESET_MASK_LP1 1
  13. #define TEGRA_RESET_MASK_LP2 2
  14. #define TEGRA_RESET_STARTUP_SECONDARY 3
  15. #define TEGRA_RESET_STARTUP_LP2 4
  16. #define TEGRA_RESET_STARTUP_LP1 5
  17. #define TEGRA_RESET_TF_PRESENT 6
  18. #define TEGRA_RESET_DATA_SIZE 7
  19. #define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
  20. #ifndef __ASSEMBLY__
  21. #include "irammap.h"
  22. extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
  23. void __tegra_cpu_reset_handler_start(void);
  24. void __tegra_cpu_reset_handler(void);
  25. void __tegra20_cpu1_resettable_status_offset(void);
  26. void __tegra_cpu_reset_handler_end(void);
  27. #ifdef CONFIG_PM_SLEEP
  28. #define tegra_cpu_lp1_mask \
  29. (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
  30. ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
  31. (u32)__tegra_cpu_reset_handler_start)))
  32. #define tegra_cpu_lp2_mask \
  33. (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
  34. ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
  35. (u32)__tegra_cpu_reset_handler_start)))
  36. #endif
  37. #define tegra_cpu_reset_handler_offset \
  38. ((u32)__tegra_cpu_reset_handler - \
  39. (u32)__tegra_cpu_reset_handler_start)
  40. #define tegra_cpu_reset_handler_size \
  41. (__tegra_cpu_reset_handler_end - \
  42. __tegra_cpu_reset_handler_start)
  43. void __init tegra_cpu_reset_handler_init(void);
  44. #endif
  45. #endif