pm.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * CPU complex suspend & resume functions for Tegra SoCs
  4. *
  5. * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
  6. */
  7. #include <linux/clk/tegra.h>
  8. #include <linux/cpumask.h>
  9. #include <linux/cpu_pm.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/io.h>
  13. #include <linux/kernel.h>
  14. #include <linux/slab.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/suspend.h>
  17. #include <linux/firmware/trusted_foundations.h>
  18. #include <soc/tegra/flowctrl.h>
  19. #include <soc/tegra/fuse.h>
  20. #include <soc/tegra/pm.h>
  21. #include <soc/tegra/pmc.h>
  22. #include <asm/cacheflush.h>
  23. #include <asm/firmware.h>
  24. #include <asm/idmap.h>
  25. #include <asm/proc-fns.h>
  26. #include <asm/smp_plat.h>
  27. #include <asm/suspend.h>
  28. #include <asm/tlbflush.h>
  29. #include "iomap.h"
  30. #include "pm.h"
  31. #include "reset.h"
  32. #include "sleep.h"
  33. #ifdef CONFIG_PM_SLEEP
  34. static DEFINE_SPINLOCK(tegra_lp2_lock);
  35. static u32 iram_save_size;
  36. static void *iram_save_addr;
  37. struct tegra_lp1_iram tegra_lp1_iram;
  38. void (*tegra_tear_down_cpu)(void);
  39. void (*tegra_sleep_core_finish)(unsigned long v2p);
  40. static int (*tegra_sleep_func)(unsigned long v2p);
  41. static void tegra_tear_down_cpu_init(void)
  42. {
  43. switch (tegra_get_chip_id()) {
  44. case TEGRA20:
  45. if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
  46. tegra_tear_down_cpu = tegra20_tear_down_cpu;
  47. break;
  48. case TEGRA30:
  49. case TEGRA114:
  50. case TEGRA124:
  51. if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
  52. IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
  53. IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
  54. tegra_tear_down_cpu = tegra30_tear_down_cpu;
  55. break;
  56. }
  57. }
  58. /*
  59. * restore_cpu_complex
  60. *
  61. * restores cpu clock setting, clears flow controller
  62. *
  63. * Always called on CPU 0.
  64. */
  65. static void restore_cpu_complex(void)
  66. {
  67. int cpu = smp_processor_id();
  68. BUG_ON(cpu != 0);
  69. #ifdef CONFIG_SMP
  70. cpu = cpu_logical_map(cpu);
  71. #endif
  72. /* Restore the CPU clock settings */
  73. tegra_cpu_clock_resume();
  74. flowctrl_cpu_suspend_exit(cpu);
  75. }
  76. /*
  77. * suspend_cpu_complex
  78. *
  79. * saves pll state for use by restart_plls, prepares flow controller for
  80. * transition to suspend state
  81. *
  82. * Must always be called on cpu 0.
  83. */
  84. static void suspend_cpu_complex(void)
  85. {
  86. int cpu = smp_processor_id();
  87. BUG_ON(cpu != 0);
  88. #ifdef CONFIG_SMP
  89. cpu = cpu_logical_map(cpu);
  90. #endif
  91. /* Save the CPU clock settings */
  92. tegra_cpu_clock_suspend();
  93. flowctrl_cpu_suspend_enter(cpu);
  94. }
  95. void tegra_pm_clear_cpu_in_lp2(void)
  96. {
  97. int phy_cpu_id = cpu_logical_map(smp_processor_id());
  98. u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
  99. spin_lock(&tegra_lp2_lock);
  100. BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
  101. *cpu_in_lp2 &= ~BIT(phy_cpu_id);
  102. spin_unlock(&tegra_lp2_lock);
  103. }
  104. void tegra_pm_set_cpu_in_lp2(void)
  105. {
  106. int phy_cpu_id = cpu_logical_map(smp_processor_id());
  107. u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
  108. spin_lock(&tegra_lp2_lock);
  109. BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
  110. *cpu_in_lp2 |= BIT(phy_cpu_id);
  111. spin_unlock(&tegra_lp2_lock);
  112. }
  113. static int tegra_sleep_cpu(unsigned long v2p)
  114. {
  115. if (tegra_cpu_car_ops->rail_off_ready &&
  116. WARN_ON(!tegra_cpu_rail_off_ready()))
  117. return -EBUSY;
  118. /*
  119. * L2 cache disabling using kernel API only allowed when all
  120. * secondary CPU's are offline. Cache have to be disabled with
  121. * MMU-on if cache maintenance is done via Trusted Foundations
  122. * firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
  123. * if any of secondary CPU's is online and this is the LP2-idle
  124. * code-path only for Tegra20/30.
  125. */
  126. #ifdef CONFIG_OUTER_CACHE
  127. if (trusted_foundations_registered() && outer_cache.disable)
  128. outer_cache.disable();
  129. #endif
  130. /*
  131. * Note that besides of setting up CPU reset vector this firmware
  132. * call may also do the following, depending on the FW version:
  133. * 1) Disable L2. But this doesn't matter since we already
  134. * disabled the L2.
  135. * 2) Disable D-cache. This need to be taken into account in
  136. * particular by the tegra_disable_clean_inv_dcache() which
  137. * shall avoid the re-disable.
  138. */
  139. call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
  140. setup_mm_for_reboot();
  141. tegra_sleep_cpu_finish(v2p);
  142. /* should never here */
  143. BUG();
  144. return 0;
  145. }
  146. static void tegra_pm_set(enum tegra_suspend_mode mode)
  147. {
  148. u32 value;
  149. switch (tegra_get_chip_id()) {
  150. case TEGRA20:
  151. case TEGRA30:
  152. break;
  153. default:
  154. /* Turn off CRAIL */
  155. value = flowctrl_read_cpu_csr(0);
  156. value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
  157. value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
  158. flowctrl_write_cpu_csr(0, value);
  159. break;
  160. }
  161. tegra_pmc_enter_suspend_mode(mode);
  162. }
  163. int tegra_pm_enter_lp2(void)
  164. {
  165. int err;
  166. tegra_pm_set(TEGRA_SUSPEND_LP2);
  167. cpu_cluster_pm_enter();
  168. suspend_cpu_complex();
  169. err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
  170. /*
  171. * Resume L2 cache if it wasn't re-enabled early during resume,
  172. * which is the case for Tegra30 that has to re-enable the cache
  173. * via firmware call. In other cases cache is already enabled and
  174. * hence re-enabling is a no-op. This is always a no-op on Tegra114+.
  175. */
  176. outer_resume();
  177. restore_cpu_complex();
  178. cpu_cluster_pm_exit();
  179. call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
  180. return err;
  181. }
  182. enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
  183. enum tegra_suspend_mode mode)
  184. {
  185. /*
  186. * The Tegra devices support suspending to LP1 or lower currently.
  187. */
  188. if (mode > TEGRA_SUSPEND_LP1)
  189. return TEGRA_SUSPEND_LP1;
  190. return mode;
  191. }
  192. static int tegra_sleep_core(unsigned long v2p)
  193. {
  194. /*
  195. * Cache have to be disabled with MMU-on if cache maintenance is done
  196. * via Trusted Foundations firmware. This is a no-op on Tegra114+.
  197. */
  198. if (trusted_foundations_registered())
  199. outer_disable();
  200. call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
  201. setup_mm_for_reboot();
  202. tegra_sleep_core_finish(v2p);
  203. /* should never here */
  204. BUG();
  205. return 0;
  206. }
  207. /*
  208. * tegra_lp1_iram_hook
  209. *
  210. * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
  211. * SDRAM. These codes not be copied to IRAM in this fuction. We need to
  212. * copy these code to IRAM before LP0/LP1 suspend and restore the content
  213. * of IRAM after resume.
  214. */
  215. static bool tegra_lp1_iram_hook(void)
  216. {
  217. switch (tegra_get_chip_id()) {
  218. case TEGRA20:
  219. if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
  220. tegra20_lp1_iram_hook();
  221. break;
  222. case TEGRA30:
  223. case TEGRA114:
  224. case TEGRA124:
  225. if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
  226. IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
  227. IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
  228. tegra30_lp1_iram_hook();
  229. break;
  230. default:
  231. break;
  232. }
  233. if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
  234. return false;
  235. iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
  236. iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
  237. if (!iram_save_addr)
  238. return false;
  239. return true;
  240. }
  241. static bool tegra_sleep_core_init(void)
  242. {
  243. switch (tegra_get_chip_id()) {
  244. case TEGRA20:
  245. if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
  246. tegra20_sleep_core_init();
  247. break;
  248. case TEGRA30:
  249. case TEGRA114:
  250. case TEGRA124:
  251. if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
  252. IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
  253. IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
  254. tegra30_sleep_core_init();
  255. break;
  256. default:
  257. break;
  258. }
  259. if (!tegra_sleep_core_finish)
  260. return false;
  261. return true;
  262. }
  263. static void tegra_suspend_enter_lp1(void)
  264. {
  265. /* copy the reset vector & SDRAM shutdown code into IRAM */
  266. memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
  267. iram_save_size);
  268. memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
  269. tegra_lp1_iram.start_addr, iram_save_size);
  270. *((u32 *)tegra_cpu_lp1_mask) = 1;
  271. }
  272. static void tegra_suspend_exit_lp1(void)
  273. {
  274. /* restore IRAM */
  275. memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
  276. iram_save_size);
  277. *(u32 *)tegra_cpu_lp1_mask = 0;
  278. }
  279. static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
  280. [TEGRA_SUSPEND_NONE] = "none",
  281. [TEGRA_SUSPEND_LP2] = "LP2",
  282. [TEGRA_SUSPEND_LP1] = "LP1",
  283. [TEGRA_SUSPEND_LP0] = "LP0",
  284. };
  285. static int tegra_suspend_enter(suspend_state_t state)
  286. {
  287. enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
  288. if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
  289. mode >= TEGRA_MAX_SUSPEND_MODE))
  290. return -EINVAL;
  291. pr_info("Entering suspend state %s\n", lp_state[mode]);
  292. tegra_pm_set(mode);
  293. local_fiq_disable();
  294. suspend_cpu_complex();
  295. switch (mode) {
  296. case TEGRA_SUSPEND_LP1:
  297. tegra_suspend_enter_lp1();
  298. break;
  299. case TEGRA_SUSPEND_LP2:
  300. tegra_pm_set_cpu_in_lp2();
  301. break;
  302. default:
  303. break;
  304. }
  305. cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
  306. /*
  307. * Resume L2 cache if it wasn't re-enabled early during resume,
  308. * which is the case for Tegra30 that has to re-enable the cache
  309. * via firmware call. In other cases cache is already enabled and
  310. * hence re-enabling is a no-op.
  311. */
  312. outer_resume();
  313. switch (mode) {
  314. case TEGRA_SUSPEND_LP1:
  315. tegra_suspend_exit_lp1();
  316. break;
  317. case TEGRA_SUSPEND_LP2:
  318. tegra_pm_clear_cpu_in_lp2();
  319. break;
  320. default:
  321. break;
  322. }
  323. restore_cpu_complex();
  324. local_fiq_enable();
  325. call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
  326. return 0;
  327. }
  328. static const struct platform_suspend_ops tegra_suspend_ops = {
  329. .valid = suspend_valid_only_mem,
  330. .enter = tegra_suspend_enter,
  331. };
  332. void tegra_pm_init_suspend(void)
  333. {
  334. enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
  335. if (mode == TEGRA_SUSPEND_NONE)
  336. return;
  337. tegra_tear_down_cpu_init();
  338. if (mode >= TEGRA_SUSPEND_LP1) {
  339. if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
  340. pr_err("%s: unable to allocate memory for SDRAM"
  341. "self-refresh -- LP0/LP1 unavailable\n",
  342. __func__);
  343. tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
  344. mode = TEGRA_SUSPEND_LP2;
  345. }
  346. }
  347. /* set up sleep function for cpu_suspend */
  348. switch (mode) {
  349. case TEGRA_SUSPEND_LP1:
  350. tegra_sleep_func = tegra_sleep_core;
  351. break;
  352. case TEGRA_SUSPEND_LP2:
  353. tegra_sleep_func = tegra_sleep_cpu;
  354. break;
  355. default:
  356. break;
  357. }
  358. suspend_set_ops(&tegra_suspend_ops);
  359. }
  360. int tegra_pm_park_secondary_cpu(unsigned long cpu)
  361. {
  362. if (cpu > 0) {
  363. tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
  364. if (tegra_get_chip_id() == TEGRA20)
  365. tegra20_hotplug_shutdown();
  366. else
  367. tegra30_hotplug_shutdown();
  368. }
  369. return -EINVAL;
  370. }
  371. #endif