time.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * arch/arm/plat-spear/time.c
  4. *
  5. * Copyright (C) 2010 ST Microelectronics
  6. * Shiraz Hashim<[email protected]>
  7. */
  8. #include <linux/clk.h>
  9. #include <linux/clockchips.h>
  10. #include <linux/clocksource.h>
  11. #include <linux/err.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ioport.h>
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_address.h>
  19. #include <linux/time.h>
  20. #include <linux/irq.h>
  21. #include <asm/mach/time.h>
  22. #include "generic.h"
  23. /*
  24. * We would use TIMER0 and TIMER1 as clockevent and clocksource.
  25. * Timer0 and Timer1 both belong to same gpt block in cpu subbsystem. Further
  26. * they share same functional clock. Any change in one's functional clock will
  27. * also affect other timer.
  28. */
  29. #define CLKEVT 0 /* gpt0, channel0 as clockevent */
  30. #define CLKSRC 1 /* gpt0, channel1 as clocksource */
  31. /* Register offsets, x is channel number */
  32. #define CR(x) ((x) * 0x80 + 0x80)
  33. #define IR(x) ((x) * 0x80 + 0x84)
  34. #define LOAD(x) ((x) * 0x80 + 0x88)
  35. #define COUNT(x) ((x) * 0x80 + 0x8C)
  36. /* Reg bit definitions */
  37. #define CTRL_INT_ENABLE 0x0100
  38. #define CTRL_ENABLE 0x0020
  39. #define CTRL_ONE_SHOT 0x0010
  40. #define CTRL_PRESCALER1 0x0
  41. #define CTRL_PRESCALER2 0x1
  42. #define CTRL_PRESCALER4 0x2
  43. #define CTRL_PRESCALER8 0x3
  44. #define CTRL_PRESCALER16 0x4
  45. #define CTRL_PRESCALER32 0x5
  46. #define CTRL_PRESCALER64 0x6
  47. #define CTRL_PRESCALER128 0x7
  48. #define CTRL_PRESCALER256 0x8
  49. #define INT_STATUS 0x1
  50. /*
  51. * Minimum clocksource/clockevent timer range in seconds
  52. */
  53. #define SPEAR_MIN_RANGE 4
  54. static __iomem void *gpt_base;
  55. static struct clk *gpt_clk;
  56. static int clockevent_next_event(unsigned long evt,
  57. struct clock_event_device *clk_event_dev);
  58. static void __init spear_clocksource_init(void)
  59. {
  60. u32 tick_rate;
  61. u16 val;
  62. /* program the prescaler (/256)*/
  63. writew(CTRL_PRESCALER256, gpt_base + CR(CLKSRC));
  64. /* find out actual clock driving Timer */
  65. tick_rate = clk_get_rate(gpt_clk);
  66. tick_rate >>= CTRL_PRESCALER256;
  67. writew(0xFFFF, gpt_base + LOAD(CLKSRC));
  68. val = readw(gpt_base + CR(CLKSRC));
  69. val &= ~CTRL_ONE_SHOT; /* autoreload mode */
  70. val |= CTRL_ENABLE ;
  71. writew(val, gpt_base + CR(CLKSRC));
  72. /* register the clocksource */
  73. clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
  74. 200, 16, clocksource_mmio_readw_up);
  75. }
  76. static inline void timer_shutdown(struct clock_event_device *evt)
  77. {
  78. u16 val = readw(gpt_base + CR(CLKEVT));
  79. /* stop the timer */
  80. val &= ~CTRL_ENABLE;
  81. writew(val, gpt_base + CR(CLKEVT));
  82. }
  83. static int spear_shutdown(struct clock_event_device *evt)
  84. {
  85. timer_shutdown(evt);
  86. return 0;
  87. }
  88. static int spear_set_oneshot(struct clock_event_device *evt)
  89. {
  90. u16 val;
  91. /* stop the timer */
  92. timer_shutdown(evt);
  93. val = readw(gpt_base + CR(CLKEVT));
  94. val |= CTRL_ONE_SHOT;
  95. writew(val, gpt_base + CR(CLKEVT));
  96. return 0;
  97. }
  98. static int spear_set_periodic(struct clock_event_device *evt)
  99. {
  100. u32 period;
  101. u16 val;
  102. /* stop the timer */
  103. timer_shutdown(evt);
  104. period = clk_get_rate(gpt_clk) / HZ;
  105. period >>= CTRL_PRESCALER16;
  106. writew(period, gpt_base + LOAD(CLKEVT));
  107. val = readw(gpt_base + CR(CLKEVT));
  108. val &= ~CTRL_ONE_SHOT;
  109. val |= CTRL_ENABLE | CTRL_INT_ENABLE;
  110. writew(val, gpt_base + CR(CLKEVT));
  111. return 0;
  112. }
  113. static struct clock_event_device clkevt = {
  114. .name = "tmr0",
  115. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  116. .set_state_shutdown = spear_shutdown,
  117. .set_state_periodic = spear_set_periodic,
  118. .set_state_oneshot = spear_set_oneshot,
  119. .tick_resume = spear_shutdown,
  120. .set_next_event = clockevent_next_event,
  121. .shift = 0, /* to be computed */
  122. };
  123. static int clockevent_next_event(unsigned long cycles,
  124. struct clock_event_device *clk_event_dev)
  125. {
  126. u16 val = readw(gpt_base + CR(CLKEVT));
  127. if (val & CTRL_ENABLE)
  128. writew(val & ~CTRL_ENABLE, gpt_base + CR(CLKEVT));
  129. writew(cycles, gpt_base + LOAD(CLKEVT));
  130. val |= CTRL_ENABLE | CTRL_INT_ENABLE;
  131. writew(val, gpt_base + CR(CLKEVT));
  132. return 0;
  133. }
  134. static irqreturn_t spear_timer_interrupt(int irq, void *dev_id)
  135. {
  136. struct clock_event_device *evt = &clkevt;
  137. writew(INT_STATUS, gpt_base + IR(CLKEVT));
  138. evt->event_handler(evt);
  139. return IRQ_HANDLED;
  140. }
  141. static void __init spear_clockevent_init(int irq)
  142. {
  143. u32 tick_rate;
  144. /* program the prescaler */
  145. writew(CTRL_PRESCALER16, gpt_base + CR(CLKEVT));
  146. tick_rate = clk_get_rate(gpt_clk);
  147. tick_rate >>= CTRL_PRESCALER16;
  148. clkevt.cpumask = cpumask_of(0);
  149. clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
  150. if (request_irq(irq, spear_timer_interrupt, IRQF_TIMER, "timer", NULL))
  151. pr_err("Failed to request irq %d (timer)\n", irq);
  152. }
  153. static const struct of_device_id timer_of_match[] __initconst = {
  154. { .compatible = "st,spear-timer", },
  155. { },
  156. };
  157. void __init spear_setup_of_timer(void)
  158. {
  159. struct device_node *np;
  160. int irq, ret;
  161. np = of_find_matching_node(NULL, timer_of_match);
  162. if (!np) {
  163. pr_err("%s: No timer passed via DT\n", __func__);
  164. return;
  165. }
  166. irq = irq_of_parse_and_map(np, 0);
  167. if (!irq) {
  168. pr_err("%s: No irq passed for timer via DT\n", __func__);
  169. goto err_put_np;
  170. }
  171. gpt_base = of_iomap(np, 0);
  172. if (!gpt_base) {
  173. pr_err("%s: of iomap failed\n", __func__);
  174. goto err_put_np;
  175. }
  176. gpt_clk = clk_get_sys("gpt0", NULL);
  177. if (IS_ERR(gpt_clk)) {
  178. pr_err("%s:couldn't get clk for gpt\n", __func__);
  179. goto err_iomap;
  180. }
  181. ret = clk_prepare_enable(gpt_clk);
  182. if (ret < 0) {
  183. pr_err("%s:couldn't prepare-enable gpt clock\n", __func__);
  184. goto err_prepare_enable_clk;
  185. }
  186. of_node_put(np);
  187. spear_clockevent_init(irq);
  188. spear_clocksource_init();
  189. return;
  190. err_prepare_enable_clk:
  191. clk_put(gpt_clk);
  192. err_iomap:
  193. iounmap(gpt_base);
  194. err_put_np:
  195. of_node_put(np);
  196. }