l2_cache.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright Altera Corporation (C) 2016. All rights reserved.
  4. */
  5. #include <linux/io.h>
  6. #include <linux/of_platform.h>
  7. #include <linux/of_address.h>
  8. #include "core.h"
  9. /* A10 System Manager L2 ECC Control register */
  10. #define A10_MPU_CTRL_L2_ECC_OFST 0x0
  11. #define A10_MPU_CTRL_L2_ECC_EN BIT(0)
  12. /* A10 System Manager Global IRQ Mask register */
  13. #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
  14. #define A10_SYSMGR_ECC_INTMASK_CLR_L2 BIT(0)
  15. /* A10 System Manager L2 ECC IRQ Clear register */
  16. #define A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST 0xA8
  17. #define A10_SYSMGR_MPU_CLEAR_L2_ECC (BIT(31) | BIT(15))
  18. void socfpga_init_l2_ecc(void)
  19. {
  20. struct device_node *np;
  21. void __iomem *mapped_l2_edac_addr;
  22. np = of_find_compatible_node(NULL, NULL, "altr,socfpga-l2-ecc");
  23. if (!np) {
  24. pr_err("Unable to find socfpga-l2-ecc in dtb\n");
  25. return;
  26. }
  27. mapped_l2_edac_addr = of_iomap(np, 0);
  28. of_node_put(np);
  29. if (!mapped_l2_edac_addr) {
  30. pr_err("Unable to find L2 ECC mapping in dtb\n");
  31. return;
  32. }
  33. /* Enable ECC */
  34. writel(0x01, mapped_l2_edac_addr);
  35. iounmap(mapped_l2_edac_addr);
  36. }
  37. void socfpga_init_arria10_l2_ecc(void)
  38. {
  39. struct device_node *np;
  40. void __iomem *mapped_l2_edac_addr;
  41. /* Find the L2 EDAC device tree node */
  42. np = of_find_compatible_node(NULL, NULL, "altr,socfpga-a10-l2-ecc");
  43. if (!np) {
  44. pr_err("Unable to find socfpga-a10-l2-ecc in dtb\n");
  45. return;
  46. }
  47. mapped_l2_edac_addr = of_iomap(np, 0);
  48. of_node_put(np);
  49. if (!mapped_l2_edac_addr) {
  50. pr_err("Unable to find L2 ECC mapping in dtb\n");
  51. return;
  52. }
  53. if (!sys_manager_base_addr) {
  54. pr_err("System Manager not mapped for L2 ECC\n");
  55. goto exit;
  56. }
  57. /* Clear any pending IRQs */
  58. writel(A10_SYSMGR_MPU_CLEAR_L2_ECC, (sys_manager_base_addr +
  59. A10_SYSMGR_MPU_CLEAR_L2_ECC_OFST));
  60. /* Enable ECC */
  61. writel(A10_SYSMGR_ECC_INTMASK_CLR_L2, sys_manager_base_addr +
  62. A10_SYSMGR_ECC_INTMASK_CLR_OFST);
  63. writel(A10_MPU_CTRL_L2_ECC_EN, mapped_l2_edac_addr +
  64. A10_MPU_CTRL_L2_ECC_OFST);
  65. exit:
  66. iounmap(mapped_l2_edac_addr);
  67. }