headsmp.S 3.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * SMP support for R-Mobile / SH-Mobile
  4. *
  5. * Copyright (C) 2010 Magnus Damm
  6. * Copyright (C) 2010 Takashi Yoshii
  7. *
  8. * Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved
  9. */
  10. #include <linux/init.h>
  11. #include <linux/linkage.h>
  12. #include <linux/threads.h>
  13. #include <asm/assembler.h>
  14. #include <asm/memory.h>
  15. #define SCTLR_MMU 0x01
  16. #define BOOTROM_ADDRESS 0xE6340000
  17. #define RWTCSRA_ADDRESS 0xE6020004
  18. #define RWTCSRA_WOVF 0x10
  19. /*
  20. * Reset vector for secondary CPUs.
  21. * This will be mapped at address 0 by SBAR register.
  22. * We need _long_ jump to the physical address.
  23. */
  24. .arm
  25. .align 12
  26. ENTRY(shmobile_boot_vector)
  27. ldr r1, 1f
  28. bx r1
  29. ENDPROC(shmobile_boot_vector)
  30. .align 2
  31. .globl shmobile_boot_fn
  32. shmobile_boot_fn:
  33. 1: .space 4
  34. .globl shmobile_boot_size
  35. shmobile_boot_size:
  36. .long . - shmobile_boot_vector
  37. #ifdef CONFIG_ARCH_RCAR_GEN2
  38. /*
  39. * Reset vector for R-Car Gen2 and RZ/G1 secondary CPUs.
  40. * This will be mapped at address 0 by SBAR register.
  41. */
  42. ENTRY(shmobile_boot_vector_gen2)
  43. mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR
  44. ldr r1, shmobile_boot_cpu_gen2
  45. cmp r0, r1
  46. bne shmobile_smp_continue_gen2
  47. mrc p15, 0, r1, c1, c0, 0 @ r1 = SCTLR
  48. and r0, r1, #SCTLR_MMU
  49. cmp r0, #SCTLR_MMU
  50. beq shmobile_smp_continue_gen2
  51. ldr r0, rwtcsra
  52. mov r1, #0
  53. ldrb r1, [r0]
  54. and r0, r1, #RWTCSRA_WOVF
  55. cmp r0, #RWTCSRA_WOVF
  56. bne shmobile_smp_continue_gen2
  57. ldr r0, bootrom
  58. bx r0
  59. shmobile_smp_continue_gen2:
  60. ldr r1, shmobile_boot_fn_gen2
  61. bx r1
  62. ENDPROC(shmobile_boot_vector_gen2)
  63. .align 4
  64. rwtcsra:
  65. .word RWTCSRA_ADDRESS
  66. bootrom:
  67. .word BOOTROM_ADDRESS
  68. .globl shmobile_boot_cpu_gen2
  69. shmobile_boot_cpu_gen2:
  70. .word 0x00000000
  71. .align 2
  72. .globl shmobile_boot_fn_gen2
  73. shmobile_boot_fn_gen2:
  74. .space 4
  75. .globl shmobile_boot_size_gen2
  76. shmobile_boot_size_gen2:
  77. .long . - shmobile_boot_vector_gen2
  78. #endif /* CONFIG_ARCH_RCAR_GEN2 */
  79. /*
  80. * Per-CPU SMP boot function/argument selection code based on MPIDR
  81. */
  82. ENTRY(shmobile_smp_boot)
  83. mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
  84. and r0, r1, #0xffffff @ MPIDR_HWID_BITMASK
  85. @ r0 = cpu_logical_map() value
  86. mov r1, #0 @ r1 = CPU index
  87. adr r2, 1f
  88. ldmia r2, {r5, r6, r7}
  89. add r5, r5, r2 @ array of per-cpu mpidr values
  90. add r6, r6, r2 @ array of per-cpu functions
  91. add r7, r7, r2 @ array of per-cpu arguments
  92. shmobile_smp_boot_find_mpidr:
  93. ldr r8, [r5, r1, lsl #2]
  94. cmp r8, r0
  95. bne shmobile_smp_boot_next
  96. ldr r9, [r6, r1, lsl #2]
  97. cmp r9, #0
  98. bne shmobile_smp_boot_found
  99. shmobile_smp_boot_next:
  100. add r1, r1, #1
  101. cmp r1, #NR_CPUS
  102. blo shmobile_smp_boot_find_mpidr
  103. b shmobile_smp_sleep
  104. shmobile_smp_boot_found:
  105. ldr r0, [r7, r1, lsl #2]
  106. ret r9
  107. ENDPROC(shmobile_smp_boot)
  108. ENTRY(shmobile_smp_sleep)
  109. wfi
  110. b shmobile_smp_boot
  111. ENDPROC(shmobile_smp_sleep)
  112. .align 2
  113. 1: .long shmobile_smp_mpidr - .
  114. .long shmobile_smp_fn - 1b
  115. .long shmobile_smp_arg - 1b
  116. .bss
  117. .globl shmobile_smp_mpidr
  118. shmobile_smp_mpidr:
  119. .space NR_CPUS * 4
  120. .globl shmobile_smp_fn
  121. shmobile_smp_fn:
  122. .space NR_CPUS * 4
  123. .globl shmobile_smp_arg
  124. shmobile_smp_arg:
  125. .space NR_CPUS * 4