neponset.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * linux/arch/arm/mach-sa1100/neponset.c
  4. */
  5. #include <linux/err.h>
  6. #include <linux/gpio/driver.h>
  7. #include <linux/gpio/gpio-reg.h>
  8. #include <linux/gpio/machine.h>
  9. #include <linux/init.h>
  10. #include <linux/ioport.h>
  11. #include <linux/irq.h>
  12. #include <linux/kernel.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/pm.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/slab.h>
  18. #include <linux/smc91x.h>
  19. #include <asm/mach-types.h>
  20. #include <asm/mach/map.h>
  21. #include <asm/hardware/sa1111.h>
  22. #include <linux/sizes.h>
  23. #include <mach/hardware.h>
  24. #include <mach/assabet.h>
  25. #include <mach/neponset.h>
  26. #include <mach/irqs.h>
  27. #define NEP_IRQ_SMC91X 0
  28. #define NEP_IRQ_USAR 1
  29. #define NEP_IRQ_SA1111 2
  30. #define NEP_IRQ_NR 3
  31. #define WHOAMI 0x00
  32. #define LEDS 0x10
  33. #define SWPK 0x20
  34. #define IRR 0x24
  35. #define KP_Y_IN 0x80
  36. #define KP_X_OUT 0x90
  37. #define NCR_0 0xa0
  38. #define MDM_CTL_0 0xb0
  39. #define MDM_CTL_1 0xb4
  40. #define AUD_CTL 0xc0
  41. #define IRR_ETHERNET (1 << 0)
  42. #define IRR_USAR (1 << 1)
  43. #define IRR_SA1111 (1 << 2)
  44. #define NCR_NGPIO 7
  45. #define MDM_CTL0_NGPIO 4
  46. #define MDM_CTL1_NGPIO 6
  47. #define AUD_NGPIO 2
  48. extern void sa1110_mb_disable(void);
  49. #define to_neponset_gpio_chip(x) container_of(x, struct neponset_gpio_chip, gc)
  50. static const char *neponset_ncr_names[] = {
  51. "gp01_off", "tp_power", "ms_power", "enet_osc",
  52. "spi_kb_wk_up", "a0vpp", "a1vpp"
  53. };
  54. static const char *neponset_mdmctl0_names[] = {
  55. "rts3", "dtr3", "rts1", "dtr1",
  56. };
  57. static const char *neponset_mdmctl1_names[] = {
  58. "cts3", "dsr3", "dcd3", "cts1", "dsr1", "dcd1"
  59. };
  60. static const char *neponset_aud_names[] = {
  61. "sel_1341", "mute_1341",
  62. };
  63. struct neponset_drvdata {
  64. void __iomem *base;
  65. struct platform_device *sa1111;
  66. struct platform_device *smc91x;
  67. unsigned irq_base;
  68. struct gpio_chip *gpio[4];
  69. };
  70. static struct gpiod_lookup_table neponset_uart1_gpio_table = {
  71. .dev_id = "sa11x0-uart.1",
  72. .table = {
  73. GPIO_LOOKUP("neponset-mdm-ctl0", 2, "rts", GPIO_ACTIVE_LOW),
  74. GPIO_LOOKUP("neponset-mdm-ctl0", 3, "dtr", GPIO_ACTIVE_LOW),
  75. GPIO_LOOKUP("neponset-mdm-ctl1", 3, "cts", GPIO_ACTIVE_LOW),
  76. GPIO_LOOKUP("neponset-mdm-ctl1", 4, "dsr", GPIO_ACTIVE_LOW),
  77. GPIO_LOOKUP("neponset-mdm-ctl1", 5, "dcd", GPIO_ACTIVE_LOW),
  78. { },
  79. },
  80. };
  81. static struct gpiod_lookup_table neponset_uart3_gpio_table = {
  82. .dev_id = "sa11x0-uart.3",
  83. .table = {
  84. GPIO_LOOKUP("neponset-mdm-ctl0", 0, "rts", GPIO_ACTIVE_LOW),
  85. GPIO_LOOKUP("neponset-mdm-ctl0", 1, "dtr", GPIO_ACTIVE_LOW),
  86. GPIO_LOOKUP("neponset-mdm-ctl1", 0, "cts", GPIO_ACTIVE_LOW),
  87. GPIO_LOOKUP("neponset-mdm-ctl1", 1, "dsr", GPIO_ACTIVE_LOW),
  88. GPIO_LOOKUP("neponset-mdm-ctl1", 2, "dcd", GPIO_ACTIVE_LOW),
  89. { },
  90. },
  91. };
  92. static struct gpiod_lookup_table neponset_pcmcia_table = {
  93. .dev_id = "1800",
  94. .table = {
  95. GPIO_LOOKUP("sa1111", 1, "a0vcc", GPIO_ACTIVE_HIGH),
  96. GPIO_LOOKUP("sa1111", 0, "a1vcc", GPIO_ACTIVE_HIGH),
  97. GPIO_LOOKUP("neponset-ncr", 5, "a0vpp", GPIO_ACTIVE_HIGH),
  98. GPIO_LOOKUP("neponset-ncr", 6, "a1vpp", GPIO_ACTIVE_HIGH),
  99. GPIO_LOOKUP("sa1111", 2, "b0vcc", GPIO_ACTIVE_HIGH),
  100. GPIO_LOOKUP("sa1111", 3, "b1vcc", GPIO_ACTIVE_HIGH),
  101. { },
  102. },
  103. };
  104. static struct neponset_drvdata *nep;
  105. void neponset_ncr_frob(unsigned int mask, unsigned int val)
  106. {
  107. struct neponset_drvdata *n = nep;
  108. unsigned long m = mask, v = val;
  109. if (nep)
  110. n->gpio[0]->set_multiple(n->gpio[0], &m, &v);
  111. else
  112. WARN(1, "nep unset\n");
  113. }
  114. EXPORT_SYMBOL(neponset_ncr_frob);
  115. /*
  116. * Install handler for Neponset IRQ. Note that we have to loop here
  117. * since the ETHERNET and USAR IRQs are level based, and we need to
  118. * ensure that the IRQ signal is deasserted before returning. This
  119. * is rather unfortunate.
  120. */
  121. static void neponset_irq_handler(struct irq_desc *desc)
  122. {
  123. struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
  124. unsigned int irr;
  125. while (1) {
  126. /*
  127. * Acknowledge the parent IRQ.
  128. */
  129. desc->irq_data.chip->irq_ack(&desc->irq_data);
  130. /*
  131. * Read the interrupt reason register. Let's have all
  132. * active IRQ bits high. Note: there is a typo in the
  133. * Neponset user's guide for the SA1111 IRR level.
  134. */
  135. irr = readb_relaxed(d->base + IRR);
  136. irr ^= IRR_ETHERNET | IRR_USAR;
  137. if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
  138. break;
  139. /*
  140. * Since there is no individual mask, we have to
  141. * mask the parent IRQ. This is safe, since we'll
  142. * recheck the register for any pending IRQs.
  143. */
  144. if (irr & (IRR_ETHERNET | IRR_USAR)) {
  145. desc->irq_data.chip->irq_mask(&desc->irq_data);
  146. /*
  147. * Ack the interrupt now to prevent re-entering
  148. * this neponset handler. Again, this is safe
  149. * since we'll check the IRR register prior to
  150. * leaving.
  151. */
  152. desc->irq_data.chip->irq_ack(&desc->irq_data);
  153. if (irr & IRR_ETHERNET)
  154. generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
  155. if (irr & IRR_USAR)
  156. generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
  157. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  158. }
  159. if (irr & IRR_SA1111)
  160. generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
  161. }
  162. }
  163. /* Yes, we really do not have any kind of masking or unmasking */
  164. static void nochip_noop(struct irq_data *irq)
  165. {
  166. }
  167. static struct irq_chip nochip = {
  168. .name = "neponset",
  169. .irq_ack = nochip_noop,
  170. .irq_mask = nochip_noop,
  171. .irq_unmask = nochip_noop,
  172. };
  173. static int neponset_init_gpio(struct gpio_chip **gcp,
  174. struct device *dev, const char *label, void __iomem *reg,
  175. unsigned num, bool in, const char *const * names)
  176. {
  177. struct gpio_chip *gc;
  178. gc = gpio_reg_init(dev, reg, -1, num, label, in ? 0xffffffff : 0,
  179. readl_relaxed(reg), names, NULL, NULL);
  180. if (IS_ERR(gc))
  181. return PTR_ERR(gc);
  182. *gcp = gc;
  183. return 0;
  184. }
  185. static struct sa1111_platform_data sa1111_info = {
  186. .disable_devs = SA1111_DEVID_PS2_MSE,
  187. };
  188. static int neponset_probe(struct platform_device *dev)
  189. {
  190. struct neponset_drvdata *d;
  191. struct resource *nep_res, *sa1111_res, *smc91x_res;
  192. struct resource sa1111_resources[] = {
  193. DEFINE_RES_MEM(0x40000000, SZ_8K),
  194. { .flags = IORESOURCE_IRQ },
  195. };
  196. struct platform_device_info sa1111_devinfo = {
  197. .parent = &dev->dev,
  198. .name = "sa1111",
  199. .id = 0,
  200. .res = sa1111_resources,
  201. .num_res = ARRAY_SIZE(sa1111_resources),
  202. .data = &sa1111_info,
  203. .size_data = sizeof(sa1111_info),
  204. .dma_mask = 0xffffffffUL,
  205. };
  206. struct resource smc91x_resources[] = {
  207. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
  208. 0x02000000, "smc91x-regs"),
  209. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
  210. 0x02000000, "smc91x-attrib"),
  211. { .flags = IORESOURCE_IRQ },
  212. };
  213. struct smc91x_platdata smc91x_platdata = {
  214. .flags = SMC91X_USE_8BIT | SMC91X_IO_SHIFT_2 | SMC91X_NOWAIT,
  215. };
  216. struct platform_device_info smc91x_devinfo = {
  217. .parent = &dev->dev,
  218. .name = "smc91x",
  219. .id = 0,
  220. .res = smc91x_resources,
  221. .num_res = ARRAY_SIZE(smc91x_resources),
  222. .data = &smc91x_platdata,
  223. .size_data = sizeof(smc91x_platdata),
  224. };
  225. int ret, irq;
  226. if (nep)
  227. return -EBUSY;
  228. irq = ret = platform_get_irq(dev, 0);
  229. if (ret < 0)
  230. goto err_alloc;
  231. nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  232. smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
  233. sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
  234. if (!nep_res || !smc91x_res || !sa1111_res) {
  235. ret = -ENXIO;
  236. goto err_alloc;
  237. }
  238. d = kzalloc(sizeof(*d), GFP_KERNEL);
  239. if (!d) {
  240. ret = -ENOMEM;
  241. goto err_alloc;
  242. }
  243. d->base = ioremap(nep_res->start, SZ_4K);
  244. if (!d->base) {
  245. ret = -ENOMEM;
  246. goto err_ioremap;
  247. }
  248. if (readb_relaxed(d->base + WHOAMI) != 0x11) {
  249. dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
  250. readb_relaxed(d->base + WHOAMI));
  251. ret = -ENODEV;
  252. goto err_id;
  253. }
  254. ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
  255. if (ret <= 0) {
  256. dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
  257. NEP_IRQ_NR, ret);
  258. if (ret == 0)
  259. ret = -ENOMEM;
  260. goto err_irq_alloc;
  261. }
  262. d->irq_base = ret;
  263. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
  264. handle_simple_irq);
  265. irq_clear_status_flags(d->irq_base + NEP_IRQ_SMC91X, IRQ_NOREQUEST | IRQ_NOPROBE);
  266. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
  267. handle_simple_irq);
  268. irq_clear_status_flags(d->irq_base + NEP_IRQ_USAR, IRQ_NOREQUEST | IRQ_NOPROBE);
  269. irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
  270. irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
  271. irq_set_chained_handler_and_data(irq, neponset_irq_handler, d);
  272. /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
  273. writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
  274. neponset_init_gpio(&d->gpio[0], &dev->dev, "neponset-ncr",
  275. d->base + NCR_0, NCR_NGPIO, false,
  276. neponset_ncr_names);
  277. neponset_init_gpio(&d->gpio[1], &dev->dev, "neponset-mdm-ctl0",
  278. d->base + MDM_CTL_0, MDM_CTL0_NGPIO, false,
  279. neponset_mdmctl0_names);
  280. neponset_init_gpio(&d->gpio[2], &dev->dev, "neponset-mdm-ctl1",
  281. d->base + MDM_CTL_1, MDM_CTL1_NGPIO, true,
  282. neponset_mdmctl1_names);
  283. neponset_init_gpio(&d->gpio[3], &dev->dev, "neponset-aud-ctl",
  284. d->base + AUD_CTL, AUD_NGPIO, false,
  285. neponset_aud_names);
  286. gpiod_add_lookup_table(&neponset_uart1_gpio_table);
  287. gpiod_add_lookup_table(&neponset_uart3_gpio_table);
  288. gpiod_add_lookup_table(&neponset_pcmcia_table);
  289. /*
  290. * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
  291. * something on the Neponset activates this IRQ on sleep (eth?)
  292. */
  293. #if 0
  294. enable_irq_wake(irq);
  295. #endif
  296. dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
  297. d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
  298. nep = d;
  299. /* Ensure that the memory bus request/grant signals are setup */
  300. sa1110_mb_disable();
  301. sa1111_resources[0].parent = sa1111_res;
  302. sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
  303. sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
  304. d->sa1111 = platform_device_register_full(&sa1111_devinfo);
  305. smc91x_resources[0].parent = smc91x_res;
  306. smc91x_resources[1].parent = smc91x_res;
  307. smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
  308. smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
  309. d->smc91x = platform_device_register_full(&smc91x_devinfo);
  310. platform_set_drvdata(dev, d);
  311. return 0;
  312. err_irq_alloc:
  313. err_id:
  314. iounmap(d->base);
  315. err_ioremap:
  316. kfree(d);
  317. err_alloc:
  318. return ret;
  319. }
  320. static int neponset_remove(struct platform_device *dev)
  321. {
  322. struct neponset_drvdata *d = platform_get_drvdata(dev);
  323. int irq = platform_get_irq(dev, 0);
  324. if (!IS_ERR(d->sa1111))
  325. platform_device_unregister(d->sa1111);
  326. if (!IS_ERR(d->smc91x))
  327. platform_device_unregister(d->smc91x);
  328. gpiod_remove_lookup_table(&neponset_pcmcia_table);
  329. gpiod_remove_lookup_table(&neponset_uart3_gpio_table);
  330. gpiod_remove_lookup_table(&neponset_uart1_gpio_table);
  331. irq_set_chained_handler(irq, NULL);
  332. irq_free_descs(d->irq_base, NEP_IRQ_NR);
  333. nep = NULL;
  334. iounmap(d->base);
  335. kfree(d);
  336. return 0;
  337. }
  338. #ifdef CONFIG_PM_SLEEP
  339. static int neponset_resume(struct device *dev)
  340. {
  341. struct neponset_drvdata *d = dev_get_drvdata(dev);
  342. int i, ret = 0;
  343. for (i = 0; i < ARRAY_SIZE(d->gpio); i++) {
  344. ret = gpio_reg_resume(d->gpio[i]);
  345. if (ret)
  346. break;
  347. }
  348. return ret;
  349. }
  350. static const struct dev_pm_ops neponset_pm_ops = {
  351. .resume_noirq = neponset_resume,
  352. .restore_noirq = neponset_resume,
  353. };
  354. #define PM_OPS &neponset_pm_ops
  355. #else
  356. #define PM_OPS NULL
  357. #endif
  358. static struct platform_driver neponset_device_driver = {
  359. .probe = neponset_probe,
  360. .remove = neponset_remove,
  361. .driver = {
  362. .name = "neponset",
  363. .pm = PM_OPS,
  364. },
  365. };
  366. static int __init neponset_init(void)
  367. {
  368. return platform_driver_register(&neponset_device_driver);
  369. }
  370. subsys_initcall(neponset_init);