vr1000.h 3.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2003 Simtec Electronics
  4. * Ben Dooks <[email protected]>
  5. *
  6. * VR1000 - CPLD control constants
  7. * Machine VR1000 - IRQ Number definitions
  8. * Machine VR1000 - Memory map definitions
  9. */
  10. #ifndef __MACH_S3C24XX_VR1000_H
  11. #define __MACH_S3C24XX_VR1000_H __FILE__
  12. #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
  13. /* irq numbers to onboard peripherals */
  14. #define VR1000_IRQ_USBOC IRQ_EINT19
  15. #define VR1000_IRQ_IDE0 IRQ_EINT16
  16. #define VR1000_IRQ_IDE1 IRQ_EINT17
  17. #define VR1000_IRQ_SERIAL IRQ_EINT12
  18. #define VR1000_IRQ_DM9000A IRQ_EINT10
  19. #define VR1000_IRQ_DM9000N IRQ_EINT9
  20. #define VR1000_IRQ_SMALERT IRQ_EINT8
  21. /* map */
  22. #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
  23. /* we put the CPLD registers next, to get them out of the way */
  24. #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
  25. #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
  26. #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
  27. #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
  28. #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
  29. #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
  30. #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
  31. #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
  32. /* next, we have the PC104 ISA interrupt registers */
  33. #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
  34. #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
  35. #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
  36. #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
  37. #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
  38. #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
  39. /*
  40. * 0xE0000000 contains the IO space that is split by speed and
  41. * whether the access is for 8 or 16bit IO... this ensures that
  42. * the correct access is made
  43. *
  44. * 0x10000000 of space, partitioned as so:
  45. *
  46. * 0x00000000 to 0x04000000 8bit, slow
  47. * 0x04000000 to 0x08000000 16bit, slow
  48. * 0x08000000 to 0x0C000000 16bit, net
  49. * 0x0C000000 to 0x10000000 16bit, fast
  50. *
  51. * each of these spaces has the following in:
  52. *
  53. * 0x02000000 to 0x02100000 1MB IDE primary channel
  54. * 0x02100000 to 0x02200000 1MB IDE primary channel aux
  55. * 0x02200000 to 0x02400000 1MB IDE secondary channel
  56. * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
  57. * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
  58. * 0x02600000 to 0x02700000 1MB
  59. *
  60. * the phyiscal layout of the zones are:
  61. * nGCS2 - 8bit, slow
  62. * nGCS3 - 16bit, slow
  63. * nGCS4 - 16bit, net
  64. * nGCS5 - 16bit, fast
  65. */
  66. #define VR1000_VA_MULTISPACE (0xE0000000)
  67. #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
  68. #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
  69. #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
  70. #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
  71. #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
  72. #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
  73. #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
  74. #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
  75. #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
  76. /* physical offset addresses for the peripherals */
  77. #define VR1000_PA_IDEPRI (0x02000000)
  78. #define VR1000_PA_IDEPRIAUX (0x02800000)
  79. #define VR1000_PA_IDESEC (0x03000000)
  80. #define VR1000_PA_IDESECAUX (0x03800000)
  81. #define VR1000_PA_DM9000 (0x05000000)
  82. #define VR1000_PA_SERIAL (0x11800000)
  83. #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
  84. /* VR1000 ram is in CS1, with A26..A24 = 2_101 */
  85. #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
  86. /* some configurations for the peripherals */
  87. #define VR1000_DM9000_CS VR1000_VAM_CS4
  88. #endif /* __MACH_S3C24XX_VR1000_H */