sleep-s3c64xx.S 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /* linux/arch/arm/plat-s3c64xx/sleep.S
  3. *
  4. * Copyright 2008 Openmoko, Inc.
  5. * Copyright 2008 Simtec Electronics
  6. * Ben Dooks <[email protected]>
  7. * http://armlinux.simtec.co.uk/
  8. *
  9. * S3C64XX CPU sleep code
  10. */
  11. #include <linux/linkage.h>
  12. #include <asm/assembler.h>
  13. #include "map.h"
  14. #undef S3C64XX_VA_GPIO
  15. #define S3C64XX_VA_GPIO (0x0)
  16. #include "regs-gpio.h"
  17. #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
  18. .text
  19. /* Sleep magic, the word before the resume entry point so that the
  20. * bootloader can check for a resumeable image. */
  21. .word 0x2bedf00d
  22. /* s3c_cpu_reusme
  23. *
  24. * This is the entry point, stored by whatever method the bootloader
  25. * requires to get the kernel runnign again. This code expects to be
  26. * entered with no caches live and the MMU disabled. It will then
  27. * restore the MMU and other basic CP registers saved and restart
  28. * the kernel C code to finish the resume code.
  29. */
  30. ENTRY(s3c_cpu_resume)
  31. msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
  32. ldr r2, =LL_UART /* for debug */
  33. #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
  34. #define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00)
  35. #define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04)
  36. #define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
  37. #define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
  38. /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
  39. * as the uboot version supplied resets these to inputs during the
  40. * resume checks.
  41. */
  42. ldr r3, =S3C64XX_PA_GPIO
  43. ldr r0, [ r3, #S3C64XX_GPNCON ]
  44. bic r0, r0, #(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) | \
  45. S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15))
  46. orr r0, r0, #(S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) | \
  47. S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15))
  48. str r0, [ r3, #S3C64XX_GPNCON ]
  49. ldr r0, [ r3, #S3C64XX_GPNDAT ]
  50. bic r0, r0, #0xf << 12 @ GPN12..15
  51. orr r0, r0, #1 << 15 @ GPN15
  52. str r0, [ r3, #S3C64XX_GPNDAT ]
  53. #endif
  54. b cpu_resume