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irqs-s3c24xx.h

irqs-s3c24xx.h 7.3 KB
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  1. /* SPDX-License-Identifier: GPL-2.0 */
    2. 

  2. /*
    3. 

  3.  * Copyright (c) 2003-2005 Simtec Electronics
    4. 

  4.  *   Ben Dooks <[email protected]>
    5. 

  5.  */
    6. 

  6. 

  7. 

  8. #ifndef __ASM_ARCH_IRQS_H
    9. 

  9. #define __ASM_ARCH_IRQS_H __FILE__
    10. 

  10. 

  11. /* we keep the first set of CPU IRQs out of the range of
    12. 

  12.  * the ISA space, so that the PC104 has them to itself
    13. 

  13.  * and we don't end up having to do horrible things to the
    14. 

  14.  * standard ISA drivers....
    15. 

  15.  */
    16. 

  16. 

  17. #define S3C2410_CPUIRQ_OFFSET	 (16)
    18. 

  18. 

  19. #define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
    20. 

  20. 

  21. /* main cpu interrupts */
    22. 

  22. #define IRQ_EINT0      S3C2410_IRQ(0)	    /* 16 */
    23. 

  23. #define IRQ_EINT1      S3C2410_IRQ(1)
    24. 

  24. #define IRQ_EINT2      S3C2410_IRQ(2)
    25. 

  25. #define IRQ_EINT3      S3C2410_IRQ(3)
    26. 

  26. #define IRQ_EINT4t7    S3C2410_IRQ(4)	    /* 20 */
    27. 

  27. #define IRQ_EINT8t23   S3C2410_IRQ(5)
    28. 

  28. #define IRQ_RESERVED6  S3C2410_IRQ(6)	    /* for s3c2410 */
    29. 

  29. #define IRQ_CAM        S3C2410_IRQ(6)	    /* for s3c2440,s3c2443 */
    30. 

  30. #define IRQ_BATT_FLT   S3C2410_IRQ(7)
    31. 

  31. #define IRQ_TICK       S3C2410_IRQ(8)	    /* 24 */
    32. 

  32. #define IRQ_WDT	       S3C2410_IRQ(9)	    /* WDT/AC97 for s3c2443 */
    33. 

  33. #define IRQ_TIMER0     S3C2410_IRQ(10)
    34. 

  34. #define IRQ_TIMER1     S3C2410_IRQ(11)
    35. 

  35. #define IRQ_TIMER2     S3C2410_IRQ(12)
    36. 

  36. #define IRQ_TIMER3     S3C2410_IRQ(13)
    37. 

  37. #define IRQ_TIMER4     S3C2410_IRQ(14)
    38. 

  38. #define IRQ_UART2      S3C2410_IRQ(15)
    39. 

  39. #define IRQ_LCD	       S3C2410_IRQ(16)	    /* 32 */
    40. 

  40. #define IRQ_DMA0       S3C2410_IRQ(17)	    /* IRQ_DMA for s3c2443 */
    41. 

  41. #define IRQ_DMA1       S3C2410_IRQ(18)
    42. 

  42. #define IRQ_DMA2       S3C2410_IRQ(19)
    43. 

  43. #define IRQ_DMA3       S3C2410_IRQ(20)
    44. 

  44. #define IRQ_SDI	       S3C2410_IRQ(21)
    45. 

  45. #define IRQ_SPI0       S3C2410_IRQ(22)
    46. 

  46. #define IRQ_UART1      S3C2410_IRQ(23)
    47. 

  47. #define IRQ_RESERVED24 S3C2410_IRQ(24)	    /* 40 */
    48. 

  48. #define IRQ_NFCON      S3C2410_IRQ(24)	    /* for s3c2440 */
    49. 

  49. #define IRQ_USBD       S3C2410_IRQ(25)
    50. 

  50. #define IRQ_USBH       S3C2410_IRQ(26)
    51. 

  51. #define IRQ_IIC	       S3C2410_IRQ(27)
    52. 

  52. #define IRQ_UART0      S3C2410_IRQ(28)	    /* 44 */
    53. 

  53. #define IRQ_SPI1       S3C2410_IRQ(29)
    54. 

  54. #define IRQ_RTC	       S3C2410_IRQ(30)
    55. 

  55. #define IRQ_ADCPARENT  S3C2410_IRQ(31)
    56. 

  56. 

  57. /* interrupts generated from the external interrupts sources */
    58. 

  58. #define IRQ_EINT0_2412 S3C2410_IRQ(32)
    59. 

  59. #define IRQ_EINT1_2412 S3C2410_IRQ(33)
    60. 

  60. #define IRQ_EINT2_2412 S3C2410_IRQ(34)
    61. 

  61. #define IRQ_EINT3_2412 S3C2410_IRQ(35)
    62. 

  62. #define IRQ_EINT4      S3C2410_IRQ(36)	   /* 52 */
    63. 

  63. #define IRQ_EINT5      S3C2410_IRQ(37)
    64. 

  64. #define IRQ_EINT6      S3C2410_IRQ(38)
    65. 

  65. #define IRQ_EINT7      S3C2410_IRQ(39)
    66. 

  66. #define IRQ_EINT8      S3C2410_IRQ(40)
    67. 

  67. #define IRQ_EINT9      S3C2410_IRQ(41)
    68. 

  68. #define IRQ_EINT10     S3C2410_IRQ(42)
    69. 

  69. #define IRQ_EINT11     S3C2410_IRQ(43)
    70. 

  70. #define IRQ_EINT12     S3C2410_IRQ(44)
    71. 

  71. #define IRQ_EINT13     S3C2410_IRQ(45)
    72. 

  72. #define IRQ_EINT14     S3C2410_IRQ(46)
    73. 

  73. #define IRQ_EINT15     S3C2410_IRQ(47)
    74. 

  74. #define IRQ_EINT16     S3C2410_IRQ(48)
    75. 

  75. #define IRQ_EINT17     S3C2410_IRQ(49)
    76. 

  76. #define IRQ_EINT18     S3C2410_IRQ(50)
    77. 

  77. #define IRQ_EINT19     S3C2410_IRQ(51)
    78. 

  78. #define IRQ_EINT20     S3C2410_IRQ(52)	   /* 68 */
    79. 

  79. #define IRQ_EINT21     S3C2410_IRQ(53)
    80. 

  80. #define IRQ_EINT22     S3C2410_IRQ(54)
    81. 

  81. #define IRQ_EINT23     S3C2410_IRQ(55)
    82. 

  82. 

  83. #define IRQ_EINT_BIT(x)	((x) - IRQ_EINT4 + 4)
    84. 

  84. #define IRQ_EINT(x)    (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
    85. 

  85. 

  86. #define IRQ_LCD_FIFO   S3C2410_IRQ(56)
    87. 

  87. #define IRQ_LCD_FRAME  S3C2410_IRQ(57)
    88. 

  88. 

  89. /* IRQs for the interal UARTs, and ADC
    90. 

  90.  * these need to be ordered in number of appearance in the
    91. 

  91.  * SUBSRC mask register
    92. 

  92. */
    93. 

  93. 

  94. #define S3C2410_IRQSUB(x)	S3C2410_IRQ((x)+58)
    95. 

  95. 

  96. #define IRQ_S3CUART_RX0		S3C2410_IRQSUB(0)	/* 74 */
    97. 

  97. #define IRQ_S3CUART_TX0		S3C2410_IRQSUB(1)
    98. 

  98. #define IRQ_S3CUART_ERR0	S3C2410_IRQSUB(2)
    99. 

  99. 

  100. #define IRQ_S3CUART_RX1		S3C2410_IRQSUB(3)	/* 77 */
    101. 

  101. #define IRQ_S3CUART_TX1		S3C2410_IRQSUB(4)
    102. 

  102. #define IRQ_S3CUART_ERR1	S3C2410_IRQSUB(5)
    103. 

  103. 

  104. #define IRQ_S3CUART_RX2		S3C2410_IRQSUB(6)	/* 80 */
    105. 

  105. #define IRQ_S3CUART_TX2		S3C2410_IRQSUB(7)
    106. 

  106. #define IRQ_S3CUART_ERR2	S3C2410_IRQSUB(8)
    107. 

  107. 

  108. #define IRQ_TC			S3C2410_IRQSUB(9)
    109. 

  109. #define IRQ_ADC			S3C2410_IRQSUB(10)
    110. 

  110. 

  111. #define NR_IRQS_S3C2410		(S3C2410_IRQSUB(10) + 1)
    112. 

  112. 

  113. /* extra irqs for s3c2412 */
    114. 

  114. 

  115. #define IRQ_S3C2412_CFSDI	S3C2410_IRQ(21)
    116. 

  116. 

  117. #define IRQ_S3C2412_SDI		S3C2410_IRQSUB(13)
    118. 

  118. #define IRQ_S3C2412_CF		S3C2410_IRQSUB(14)
    119. 

  119. 

  120. #define NR_IRQS_S3C2412		(S3C2410_IRQSUB(14) + 1)
    121. 

  121. 

  122. #define IRQ_S3C2416_EINT8t15	S3C2410_IRQ(5)
    123. 

  123. #define IRQ_S3C2416_DMA		S3C2410_IRQ(17)
    124. 

  124. #define IRQ_S3C2416_UART3	S3C2410_IRQ(18)
    125. 

  125. #define IRQ_S3C2416_SDI1	S3C2410_IRQ(20)
    126. 

  126. #define IRQ_S3C2416_SDI0	S3C2410_IRQ(21)
    127. 

  127. 

  128. #define IRQ_S3C2416_LCD2	S3C2410_IRQSUB(15)
    129. 

  129. #define IRQ_S3C2416_LCD3	S3C2410_IRQSUB(16)
    130. 

  130. #define IRQ_S3C2416_LCD4	S3C2410_IRQSUB(17)
    131. 

  131. #define IRQ_S3C2416_DMA0	S3C2410_IRQSUB(18)
    132. 

  132. #define IRQ_S3C2416_DMA1	S3C2410_IRQSUB(19)
    133. 

  133. #define IRQ_S3C2416_DMA2	S3C2410_IRQSUB(20)
    134. 

  134. #define IRQ_S3C2416_DMA3	S3C2410_IRQSUB(21)
    135. 

  135. #define IRQ_S3C2416_DMA4	S3C2410_IRQSUB(22)
    136. 

  136. #define IRQ_S3C2416_DMA5	S3C2410_IRQSUB(23)
    137. 

  137. #define IRQ_S32416_WDT		S3C2410_IRQSUB(27)
    138. 

  138. #define IRQ_S32416_AC97		S3C2410_IRQSUB(28)
    139. 

  139. 

  140. /* second interrupt-register of s3c2416/s3c2450 */
    141. 

  141. 

  142. #define S3C2416_IRQ(x)		S3C2410_IRQ((x) + 58 + 29)
    143. 

  143. #define IRQ_S3C2416_2D		S3C2416_IRQ(0)
    144. 

  144. #define IRQ_S3C2416_IIC1	S3C2416_IRQ(1)
    145. 

  145. #define IRQ_S3C2416_RESERVED2	S3C2416_IRQ(2)
    146. 

  146. #define IRQ_S3C2416_RESERVED3	S3C2416_IRQ(3)
    147. 

  147. #define IRQ_S3C2416_PCM0	S3C2416_IRQ(4)
    148. 

  148. #define IRQ_S3C2416_PCM1	S3C2416_IRQ(5)
    149. 

  149. #define IRQ_S3C2416_I2S0	S3C2416_IRQ(6)
    150. 

  150. #define IRQ_S3C2416_I2S1	S3C2416_IRQ(7)
    151. 

  151. 

  152. #define NR_IRQS_S3C2416		(S3C2416_IRQ(7) + 1)
    153. 

  153. 

  154. /* extra irqs for s3c2440/s3c2442 */
    155. 

  155. 

  156. #define IRQ_S3C2440_CAM_C	S3C2410_IRQSUB(11)	/* S3C2443 too */
    157. 

  157. #define IRQ_S3C2440_CAM_P	S3C2410_IRQSUB(12)	/* S3C2443 too */
    158. 

  158. 

  159. #define NR_IRQS_S3C2442		(S3C2410_IRQSUB(12) + 1)
    160. 

  160. 

  161. #define IRQ_S3C2440_WDT		S3C2410_IRQSUB(13)
    162. 

  162. #define IRQ_S3C2440_AC97	S3C2410_IRQSUB(14)
    163. 

  163. 

  164. #define NR_IRQS_S3C2440		(S3C2410_IRQSUB(14) + 1)
    165. 

  165. 

  166. /* irqs for s3c2443 */
    167. 

  167. 

  168. #define IRQ_S3C2443_DMA		S3C2410_IRQ(17)		/* IRQ_DMA1 */
    169. 

  169. #define IRQ_S3C2443_UART3	S3C2410_IRQ(18)		/* IRQ_DMA2 */
    170. 

  170. #define IRQ_S3C2443_CFCON	S3C2410_IRQ(19)		/* IRQ_DMA3 */
    171. 

  171. #define IRQ_S3C2443_HSMMC	S3C2410_IRQ(20)		/* IRQ_SDI */
    172. 

  172. #define IRQ_S3C2443_NAND	S3C2410_IRQ(24)		/* reserved */
    173. 

  173. 

  174. #define IRQ_S3C2416_HSMMC0	S3C2410_IRQ(21)		/* S3C2416/S3C2450 */
    175. 

  175. 

  176. #define IRQ_HSMMC0		IRQ_S3C2416_HSMMC0
    177. 

  177. #define IRQ_HSMMC1		IRQ_S3C2443_HSMMC
    178. 

  178. 

  179. #define IRQ_S3C2443_LCD1	S3C2410_IRQSUB(14)
    180. 

  180. #define IRQ_S3C2443_LCD2	S3C2410_IRQSUB(15)
    181. 

  181. #define IRQ_S3C2443_LCD3	S3C2410_IRQSUB(16)
    182. 

  182. #define IRQ_S3C2443_LCD4	S3C2410_IRQSUB(17)
    183. 

  183. 

  184. #define IRQ_S3C2443_DMA0	S3C2410_IRQSUB(18)
    185. 

  185. #define IRQ_S3C2443_DMA1	S3C2410_IRQSUB(19)
    186. 

  186. #define IRQ_S3C2443_DMA2	S3C2410_IRQSUB(20)
    187. 

  187. #define IRQ_S3C2443_DMA3	S3C2410_IRQSUB(21)
    188. 

  188. #define IRQ_S3C2443_DMA4	S3C2410_IRQSUB(22)
    189. 

  189. #define IRQ_S3C2443_DMA5	S3C2410_IRQSUB(23)
    190. 

  190. 

  191. /* UART3 */
    192. 

  192. #define IRQ_S3C2443_RX3		S3C2410_IRQSUB(24)
    193. 

  193. #define IRQ_S3C2443_TX3		S3C2410_IRQSUB(25)
    194. 

  194. #define IRQ_S3C2443_ERR3	S3C2410_IRQSUB(26)
    195. 

  195. 

  196. #define IRQ_S3C2443_WDT		S3C2410_IRQSUB(27)
    197. 

  197. #define IRQ_S3C2443_AC97	S3C2410_IRQSUB(28)
    198. 

  198. 

  199. #define NR_IRQS_S3C2443		(S3C2410_IRQSUB(28) + 1)
    200. 

  200. 

  201. /* compatibility define. */
    202. 

  202. #define IRQ_UART3		IRQ_S3C2443_UART3
    203. 

  203. #define IRQ_S3CUART_RX3		IRQ_S3C2443_RX3
    204. 

  204. #define IRQ_S3CUART_TX3		IRQ_S3C2443_TX3
    205. 

  205. #define IRQ_S3CUART_ERR3	IRQ_S3C2443_ERR3
    206. 

  206. 

  207. #define IRQ_LCD_VSYNC		IRQ_S3C2443_LCD3
    208. 

  208. #define IRQ_LCD_SYSTEM		IRQ_S3C2443_LCD2
    209. 

  209. 

  210. #ifdef CONFIG_CPU_S3C2440
    211. 

  211. #define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
    212. 

  212. #else
    213. 

  213. #define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
    214. 

  214. #endif
    215. 

  215. 

  216. /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
    217. 

  217. #define FIQ_START		IRQ_EINT0
    218. 

  218. 

  219. #endif /* __ASM_ARCH_IRQ_H */
    220.