bast.h 5.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (c) 2003-2004 Simtec Electronics
  4. * Ben Dooks <[email protected]>
  5. *
  6. * BAST - CPLD control constants
  7. * BAST - IRQ Number definitions
  8. * BAST - Memory map definitions
  9. */
  10. #ifndef __MACH_S3C24XX_BAST_H
  11. #define __MACH_S3C24XX_BAST_H __FILE__
  12. /* CTRL1 - Audio LR routing */
  13. #define BAST_CPLD_CTRL1_LRCOFF (0x00)
  14. #define BAST_CPLD_CTRL1_LRCADC (0x01)
  15. #define BAST_CPLD_CTRL1_LRCDAC (0x02)
  16. #define BAST_CPLD_CTRL1_LRCARM (0x03)
  17. #define BAST_CPLD_CTRL1_LRMASK (0x03)
  18. /* CTRL2 - NAND WP control, IDE Reset assert/check */
  19. #define BAST_CPLD_CTRL2_WNAND (0x04)
  20. #define BAST_CPLD_CTLR2_IDERST (0x08)
  21. /* CTRL3 - rom write control, CPLD identity */
  22. #define BAST_CPLD_CTRL3_IDMASK (0x0e)
  23. #define BAST_CPLD_CTRL3_ROMWEN (0x01)
  24. /* CTRL4 - 8bit LCD interface control/status */
  25. #define BAST_CPLD_CTRL4_LLAT (0x01)
  26. #define BAST_CPLD_CTRL4_LCDRW (0x02)
  27. #define BAST_CPLD_CTRL4_LCDCMD (0x04)
  28. #define BAST_CPLD_CTRL4_LCDE2 (0x01)
  29. /* CTRL5 - DMA routing */
  30. #define BAST_CPLD_DMA0_PRIIDE (0)
  31. #define BAST_CPLD_DMA0_SECIDE (1)
  32. #define BAST_CPLD_DMA0_ISA15 (2)
  33. #define BAST_CPLD_DMA0_ISA36 (3)
  34. #define BAST_CPLD_DMA1_PRIIDE (0 << 2)
  35. #define BAST_CPLD_DMA1_SECIDE (1 << 2)
  36. #define BAST_CPLD_DMA1_ISA15 (2 << 2)
  37. #define BAST_CPLD_DMA1_ISA36 (3 << 2)
  38. /* irq numbers to onboard peripherals */
  39. #define BAST_IRQ_USBOC IRQ_EINT18
  40. #define BAST_IRQ_IDE0 IRQ_EINT16
  41. #define BAST_IRQ_IDE1 IRQ_EINT17
  42. #define BAST_IRQ_PCSERIAL1 IRQ_EINT15
  43. #define BAST_IRQ_PCSERIAL2 IRQ_EINT14
  44. #define BAST_IRQ_PCPARALLEL IRQ_EINT13
  45. #define BAST_IRQ_ASIX IRQ_EINT11
  46. #define BAST_IRQ_DM9000 IRQ_EINT10
  47. #define BAST_IRQ_ISA IRQ_EINT9
  48. #define BAST_IRQ_SMALERT IRQ_EINT8
  49. /* map */
  50. /*
  51. * ok, we've used up to 0x13000000, now we need to find space for the
  52. * peripherals that live in the nGCS[x] areas, which are quite numerous
  53. * in their space. We also have the board's CPLD to find register space
  54. * for.
  55. */
  56. #define BAST_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
  57. /* we put the CPLD registers next, to get them out of the way */
  58. #define BAST_VA_CTRL1 BAST_IOADDR(0x00000000)
  59. #define BAST_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
  60. #define BAST_VA_CTRL2 BAST_IOADDR(0x00100000)
  61. #define BAST_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
  62. #define BAST_VA_CTRL3 BAST_IOADDR(0x00200000)
  63. #define BAST_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
  64. #define BAST_VA_CTRL4 BAST_IOADDR(0x00300000)
  65. #define BAST_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
  66. /* next, we have the PC104 ISA interrupt registers */
  67. #define BAST_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000)
  68. #define BAST_VA_PC104_IRQREQ BAST_IOADDR(0x00400000)
  69. #define BAST_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000)
  70. #define BAST_VA_PC104_IRQRAW BAST_IOADDR(0x00500000)
  71. #define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000)
  72. #define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
  73. #define BAST_PA_LCD_RCMD1 (0x8800000)
  74. #define BAST_VA_LCD_RCMD1 BAST_IOADDR(0x00700000)
  75. #define BAST_PA_LCD_WCMD1 (0x8000000)
  76. #define BAST_VA_LCD_WCMD1 BAST_IOADDR(0x00800000)
  77. #define BAST_PA_LCD_RDATA1 (0x9800000)
  78. #define BAST_VA_LCD_RDATA1 BAST_IOADDR(0x00900000)
  79. #define BAST_PA_LCD_WDATA1 (0x9000000)
  80. #define BAST_VA_LCD_WDATA1 BAST_IOADDR(0x00A00000)
  81. #define BAST_PA_LCD_RCMD2 (0xA800000)
  82. #define BAST_VA_LCD_RCMD2 BAST_IOADDR(0x00B00000)
  83. #define BAST_PA_LCD_WCMD2 (0xA000000)
  84. #define BAST_VA_LCD_WCMD2 BAST_IOADDR(0x00C00000)
  85. #define BAST_PA_LCD_RDATA2 (0xB800000)
  86. #define BAST_VA_LCD_RDATA2 BAST_IOADDR(0x00D00000)
  87. #define BAST_PA_LCD_WDATA2 (0xB000000)
  88. #define BAST_VA_LCD_WDATA2 BAST_IOADDR(0x00E00000)
  89. /*
  90. * 0xE0000000 contains the IO space that is split by speed and
  91. * whether the access is for 8 or 16bit IO... this ensures that
  92. * the correct access is made
  93. *
  94. * 0x10000000 of space, partitioned as so:
  95. *
  96. * 0x00000000 to 0x04000000 8bit, slow
  97. * 0x04000000 to 0x08000000 16bit, slow
  98. * 0x08000000 to 0x0C000000 16bit, net
  99. * 0x0C000000 to 0x10000000 16bit, fast
  100. *
  101. * each of these spaces has the following in:
  102. *
  103. * 0x00000000 to 0x01000000 16MB ISA IO space
  104. * 0x01000000 to 0x02000000 16MB ISA memory space
  105. * 0x02000000 to 0x02100000 1MB IDE primary channel
  106. * 0x02100000 to 0x02200000 1MB IDE primary channel aux
  107. * 0x02200000 to 0x02400000 1MB IDE secondary channel
  108. * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
  109. * 0x02400000 to 0x02500000 1MB ASIX ethernet controller
  110. * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controller
  111. * 0x02600000 to 0x02700000 1MB PC SuperIO controller
  112. *
  113. * the phyiscal layout of the zones are:
  114. * nGCS2 - 8bit, slow
  115. * nGCS3 - 16bit, slow
  116. * nGCS4 - 16bit, net
  117. * nGCS5 - 16bit, fast
  118. */
  119. #define BAST_VA_MULTISPACE (0xE0000000)
  120. #define BAST_VA_ISAIO (BAST_VA_MULTISPACE + 0x00000000)
  121. #define BAST_VA_ISAMEM (BAST_VA_MULTISPACE + 0x01000000)
  122. #define BAST_VA_IDEPRI (BAST_VA_MULTISPACE + 0x02000000)
  123. #define BAST_VA_IDEPRIAUX (BAST_VA_MULTISPACE + 0x02100000)
  124. #define BAST_VA_IDESEC (BAST_VA_MULTISPACE + 0x02200000)
  125. #define BAST_VA_IDESECAUX (BAST_VA_MULTISPACE + 0x02300000)
  126. #define BAST_VA_ASIXNET (BAST_VA_MULTISPACE + 0x02400000)
  127. #define BAST_VA_DM9000 (BAST_VA_MULTISPACE + 0x02500000)
  128. #define BAST_VA_SUPERIO (BAST_VA_MULTISPACE + 0x02600000)
  129. #define BAST_VAM_CS2 (0x00000000)
  130. #define BAST_VAM_CS3 (0x04000000)
  131. #define BAST_VAM_CS4 (0x08000000)
  132. #define BAST_VAM_CS5 (0x0C000000)
  133. /* physical offset addresses for the peripherals */
  134. #define BAST_PA_ISAIO (0x00000000)
  135. #define BAST_PA_ASIXNET (0x01000000)
  136. #define BAST_PA_SUPERIO (0x01800000)
  137. #define BAST_PA_IDEPRI (0x02000000)
  138. #define BAST_PA_IDEPRIAUX (0x02800000)
  139. #define BAST_PA_IDESEC (0x03000000)
  140. #define BAST_PA_IDESECAUX (0x03800000)
  141. #define BAST_PA_ISAMEM (0x04000000)
  142. #define BAST_PA_DM9000 (0x05000000)
  143. /* some configurations for the peripherals */
  144. #define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
  145. #define BAST_ASIXNET_CS BAST_VAM_CS5
  146. #define BAST_DM9000_CS BAST_VAM_CS4
  147. #define BAST_IDE_CS S3C2410_CS5
  148. #endif /* __MACH_S3C24XX_BAST_H */