zeus.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Support for the Arcom ZEUS.
  4. *
  5. * Copyright (C) 2006 Arcom Control Systems Ltd.
  6. *
  7. * Loosely based on Arcom's 2.6.16.28.
  8. * Maintained by Marc Zyngier <[email protected]>
  9. */
  10. #include <linux/cpufreq.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/leds.h>
  13. #include <linux/irq.h>
  14. #include <linux/pm.h>
  15. #include <linux/property.h>
  16. #include <linux/gpio.h>
  17. #include <linux/gpio/machine.h>
  18. #include <linux/serial_8250.h>
  19. #include <linux/dm9000.h>
  20. #include <linux/mmc/host.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/pxa2xx_spi.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <linux/mtd/physmap.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_data/i2c-pxa.h>
  28. #include <linux/platform_data/pca953x.h>
  29. #include <linux/apm-emulation.h>
  30. #include <linux/regulator/fixed.h>
  31. #include <linux/regulator/machine.h>
  32. #include <asm/mach-types.h>
  33. #include <asm/suspend.h>
  34. #include <asm/system_info.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include "pxa27x.h"
  38. #include "devices.h"
  39. #include "regs-uart.h"
  40. #include <linux/platform_data/usb-ohci-pxa27x.h>
  41. #include <linux/platform_data/mmc-pxamci.h>
  42. #include "pxa27x-udc.h"
  43. #include "udc.h"
  44. #include <linux/platform_data/video-pxafb.h>
  45. #include "pm.h"
  46. #include <linux/platform_data/asoc-pxa.h>
  47. #include "viper-pcmcia.h"
  48. #include "zeus.h"
  49. #include "smemc.h"
  50. #include "generic.h"
  51. /*
  52. * Interrupt handling
  53. */
  54. static unsigned long zeus_irq_enabled_mask;
  55. static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
  56. static const int zeus_isa_irq_map[] = {
  57. 0, /* ISA irq #0, invalid */
  58. 0, /* ISA irq #1, invalid */
  59. 0, /* ISA irq #2, invalid */
  60. 1 << 0, /* ISA irq #3 */
  61. 1 << 1, /* ISA irq #4 */
  62. 1 << 2, /* ISA irq #5 */
  63. 1 << 3, /* ISA irq #6 */
  64. 1 << 4, /* ISA irq #7 */
  65. 0, /* ISA irq #8, invalid */
  66. 0, /* ISA irq #9, invalid */
  67. 1 << 5, /* ISA irq #10 */
  68. 1 << 6, /* ISA irq #11 */
  69. 1 << 7, /* ISA irq #12 */
  70. };
  71. static inline int zeus_irq_to_bitmask(unsigned int irq)
  72. {
  73. return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
  74. }
  75. static inline int zeus_bit_to_irq(int bit)
  76. {
  77. return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
  78. }
  79. static void zeus_ack_irq(struct irq_data *d)
  80. {
  81. __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
  82. }
  83. static void zeus_mask_irq(struct irq_data *d)
  84. {
  85. zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
  86. }
  87. static void zeus_unmask_irq(struct irq_data *d)
  88. {
  89. zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
  90. }
  91. static inline unsigned long zeus_irq_pending(void)
  92. {
  93. return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
  94. }
  95. static void zeus_irq_handler(struct irq_desc *desc)
  96. {
  97. unsigned int irq;
  98. unsigned long pending;
  99. pending = zeus_irq_pending();
  100. do {
  101. /* we're in a chained irq handler,
  102. * so ack the interrupt by hand */
  103. desc->irq_data.chip->irq_ack(&desc->irq_data);
  104. if (likely(pending)) {
  105. irq = zeus_bit_to_irq(__ffs(pending));
  106. generic_handle_irq(irq);
  107. }
  108. pending = zeus_irq_pending();
  109. } while (pending);
  110. }
  111. static struct irq_chip zeus_irq_chip = {
  112. .name = "ISA",
  113. .irq_ack = zeus_ack_irq,
  114. .irq_mask = zeus_mask_irq,
  115. .irq_unmask = zeus_unmask_irq,
  116. };
  117. static void __init zeus_init_irq(void)
  118. {
  119. int level;
  120. int isa_irq;
  121. pxa27x_init_irq();
  122. /* Peripheral IRQs. It would be nice to move those inside driver
  123. configuration, but it is not supported at the moment. */
  124. irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
  125. irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
  126. irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
  127. irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
  128. IRQ_TYPE_EDGE_FALLING);
  129. irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
  130. /* Setup ISA IRQs */
  131. for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
  132. isa_irq = zeus_bit_to_irq(level);
  133. irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
  134. handle_edge_irq);
  135. irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  136. }
  137. irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
  138. irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
  139. }
  140. /*
  141. * Platform devices
  142. */
  143. /* Flash */
  144. static struct resource zeus_mtd_resources[] = {
  145. [0] = { /* NOR Flash (up to 64MB) */
  146. .start = ZEUS_FLASH_PHYS,
  147. .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
  148. .flags = IORESOURCE_MEM,
  149. },
  150. [1] = { /* SRAM */
  151. .start = ZEUS_SRAM_PHYS,
  152. .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
  153. .flags = IORESOURCE_MEM,
  154. },
  155. };
  156. static struct physmap_flash_data zeus_flash_data[] = {
  157. [0] = {
  158. .width = 2,
  159. .parts = NULL,
  160. .nr_parts = 0,
  161. },
  162. };
  163. static struct platform_device zeus_mtd_devices[] = {
  164. [0] = {
  165. .name = "physmap-flash",
  166. .id = 0,
  167. .dev = {
  168. .platform_data = &zeus_flash_data[0],
  169. },
  170. .resource = &zeus_mtd_resources[0],
  171. .num_resources = 1,
  172. },
  173. };
  174. /* Serial */
  175. static struct resource zeus_serial_resources[] = {
  176. {
  177. .start = 0x10000000,
  178. .end = 0x1000000f,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. {
  182. .start = 0x10800000,
  183. .end = 0x1080000f,
  184. .flags = IORESOURCE_MEM,
  185. },
  186. {
  187. .start = 0x11000000,
  188. .end = 0x1100000f,
  189. .flags = IORESOURCE_MEM,
  190. },
  191. {
  192. .start = 0x40100000,
  193. .end = 0x4010001f,
  194. .flags = IORESOURCE_MEM,
  195. },
  196. {
  197. .start = 0x40200000,
  198. .end = 0x4020001f,
  199. .flags = IORESOURCE_MEM,
  200. },
  201. {
  202. .start = 0x40700000,
  203. .end = 0x4070001f,
  204. .flags = IORESOURCE_MEM,
  205. },
  206. };
  207. static struct plat_serial8250_port serial_platform_data[] = {
  208. /* External UARTs */
  209. /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
  210. { /* COM1 */
  211. .mapbase = 0x10000000,
  212. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
  213. .irqflags = IRQF_TRIGGER_RISING,
  214. .uartclk = 14745600,
  215. .regshift = 1,
  216. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  217. .iotype = UPIO_MEM,
  218. },
  219. { /* COM2 */
  220. .mapbase = 0x10800000,
  221. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
  222. .irqflags = IRQF_TRIGGER_RISING,
  223. .uartclk = 14745600,
  224. .regshift = 1,
  225. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  226. .iotype = UPIO_MEM,
  227. },
  228. { /* COM3 */
  229. .mapbase = 0x11000000,
  230. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
  231. .irqflags = IRQF_TRIGGER_RISING,
  232. .uartclk = 14745600,
  233. .regshift = 1,
  234. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  235. .iotype = UPIO_MEM,
  236. },
  237. { /* COM4 */
  238. .mapbase = 0x11800000,
  239. .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
  240. .irqflags = IRQF_TRIGGER_RISING,
  241. .uartclk = 14745600,
  242. .regshift = 1,
  243. .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  244. .iotype = UPIO_MEM,
  245. },
  246. /* Internal UARTs */
  247. { /* FFUART */
  248. .membase = (void *)&FFUART,
  249. .mapbase = __PREG(FFUART),
  250. .irq = IRQ_FFUART,
  251. .uartclk = 921600 * 16,
  252. .regshift = 2,
  253. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  254. .iotype = UPIO_MEM,
  255. },
  256. { /* BTUART */
  257. .membase = (void *)&BTUART,
  258. .mapbase = __PREG(BTUART),
  259. .irq = IRQ_BTUART,
  260. .uartclk = 921600 * 16,
  261. .regshift = 2,
  262. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  263. .iotype = UPIO_MEM,
  264. },
  265. { /* STUART */
  266. .membase = (void *)&STUART,
  267. .mapbase = __PREG(STUART),
  268. .irq = IRQ_STUART,
  269. .uartclk = 921600 * 16,
  270. .regshift = 2,
  271. .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
  272. .iotype = UPIO_MEM,
  273. },
  274. { },
  275. };
  276. static struct platform_device zeus_serial_device = {
  277. .name = "serial8250",
  278. .id = PLAT8250_DEV_PLATFORM,
  279. .dev = {
  280. .platform_data = serial_platform_data,
  281. },
  282. .num_resources = ARRAY_SIZE(zeus_serial_resources),
  283. .resource = zeus_serial_resources,
  284. };
  285. /* Ethernet */
  286. static struct resource zeus_dm9k0_resource[] = {
  287. [0] = {
  288. .start = ZEUS_ETH0_PHYS,
  289. .end = ZEUS_ETH0_PHYS + 1,
  290. .flags = IORESOURCE_MEM
  291. },
  292. [1] = {
  293. .start = ZEUS_ETH0_PHYS + 2,
  294. .end = ZEUS_ETH0_PHYS + 3,
  295. .flags = IORESOURCE_MEM
  296. },
  297. [2] = {
  298. .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
  299. .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
  300. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  301. },
  302. };
  303. static struct resource zeus_dm9k1_resource[] = {
  304. [0] = {
  305. .start = ZEUS_ETH1_PHYS,
  306. .end = ZEUS_ETH1_PHYS + 1,
  307. .flags = IORESOURCE_MEM
  308. },
  309. [1] = {
  310. .start = ZEUS_ETH1_PHYS + 2,
  311. .end = ZEUS_ETH1_PHYS + 3,
  312. .flags = IORESOURCE_MEM,
  313. },
  314. [2] = {
  315. .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
  316. .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
  317. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
  318. },
  319. };
  320. static struct dm9000_plat_data zeus_dm9k_platdata = {
  321. .flags = DM9000_PLATF_16BITONLY,
  322. };
  323. static struct platform_device zeus_dm9k0_device = {
  324. .name = "dm9000",
  325. .id = 0,
  326. .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
  327. .resource = zeus_dm9k0_resource,
  328. .dev = {
  329. .platform_data = &zeus_dm9k_platdata,
  330. }
  331. };
  332. static struct platform_device zeus_dm9k1_device = {
  333. .name = "dm9000",
  334. .id = 1,
  335. .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
  336. .resource = zeus_dm9k1_resource,
  337. .dev = {
  338. .platform_data = &zeus_dm9k_platdata,
  339. }
  340. };
  341. /* External SRAM */
  342. static struct resource zeus_sram_resource = {
  343. .start = ZEUS_SRAM_PHYS,
  344. .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
  345. .flags = IORESOURCE_MEM,
  346. };
  347. static struct platform_device zeus_sram_device = {
  348. .name = "pxa2xx-8bit-sram",
  349. .id = 0,
  350. .num_resources = 1,
  351. .resource = &zeus_sram_resource,
  352. };
  353. /* SPI interface on SSP3 */
  354. static struct pxa2xx_spi_controller pxa2xx_spi_ssp3_master_info = {
  355. .num_chipselect = 1,
  356. .enable_dma = 1,
  357. };
  358. /* CAN bus on SPI */
  359. static struct regulator_consumer_supply can_regulator_consumer =
  360. REGULATOR_SUPPLY("vdd", "spi3.0");
  361. static struct regulator_init_data can_regulator_init_data = {
  362. .constraints = {
  363. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  364. },
  365. .consumer_supplies = &can_regulator_consumer,
  366. .num_consumer_supplies = 1,
  367. };
  368. static struct fixed_voltage_config can_regulator_pdata = {
  369. .supply_name = "CAN_SHDN",
  370. .microvolts = 3300000,
  371. .init_data = &can_regulator_init_data,
  372. };
  373. static struct platform_device can_regulator_device = {
  374. .name = "reg-fixed-voltage",
  375. .id = 0,
  376. .dev = {
  377. .platform_data = &can_regulator_pdata,
  378. },
  379. };
  380. static struct gpiod_lookup_table can_regulator_gpiod_table = {
  381. .dev_id = "reg-fixed-voltage.0",
  382. .table = {
  383. GPIO_LOOKUP("gpio-pxa", ZEUS_CAN_SHDN_GPIO,
  384. NULL, GPIO_ACTIVE_LOW),
  385. { },
  386. },
  387. };
  388. static const struct property_entry mcp251x_properties[] = {
  389. PROPERTY_ENTRY_U32("clock-frequency", 16000000),
  390. {}
  391. };
  392. static const struct software_node mcp251x_node = {
  393. .properties = mcp251x_properties,
  394. };
  395. static struct spi_board_info zeus_spi_board_info[] = {
  396. [0] = {
  397. .modalias = "mcp2515",
  398. .swnode = &mcp251x_node,
  399. .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
  400. .max_speed_hz = 1*1000*1000,
  401. .bus_num = 3,
  402. .mode = SPI_MODE_0,
  403. .chip_select = 0,
  404. },
  405. };
  406. /* Leds */
  407. static struct gpio_led zeus_leds[] = {
  408. [0] = {
  409. .name = "zeus:yellow:1",
  410. .default_trigger = "heartbeat",
  411. .gpio = ZEUS_EXT0_GPIO(3),
  412. .active_low = 1,
  413. },
  414. [1] = {
  415. .name = "zeus:yellow:2",
  416. .default_trigger = "default-on",
  417. .gpio = ZEUS_EXT0_GPIO(4),
  418. .active_low = 1,
  419. },
  420. [2] = {
  421. .name = "zeus:yellow:3",
  422. .default_trigger = "default-on",
  423. .gpio = ZEUS_EXT0_GPIO(5),
  424. .active_low = 1,
  425. },
  426. };
  427. static struct gpio_led_platform_data zeus_leds_info = {
  428. .leds = zeus_leds,
  429. .num_leds = ARRAY_SIZE(zeus_leds),
  430. };
  431. static struct platform_device zeus_leds_device = {
  432. .name = "leds-gpio",
  433. .id = -1,
  434. .dev = {
  435. .platform_data = &zeus_leds_info,
  436. },
  437. };
  438. static void zeus_cf_reset(int state)
  439. {
  440. u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
  441. if (state)
  442. cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
  443. else
  444. cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
  445. __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
  446. }
  447. static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
  448. .cd_gpio = ZEUS_CF_CD_GPIO,
  449. .rdy_gpio = ZEUS_CF_RDY_GPIO,
  450. .pwr_gpio = ZEUS_CF_PWEN_GPIO,
  451. .reset = zeus_cf_reset,
  452. };
  453. static struct platform_device zeus_pcmcia_device = {
  454. .name = "zeus-pcmcia",
  455. .id = -1,
  456. .dev = {
  457. .platform_data = &zeus_pcmcia_info,
  458. },
  459. };
  460. static struct resource zeus_max6369_resource = {
  461. .start = ZEUS_CPLD_EXTWDOG_PHYS,
  462. .end = ZEUS_CPLD_EXTWDOG_PHYS,
  463. .flags = IORESOURCE_MEM,
  464. };
  465. struct platform_device zeus_max6369_device = {
  466. .name = "max6369_wdt",
  467. .id = -1,
  468. .resource = &zeus_max6369_resource,
  469. .num_resources = 1,
  470. };
  471. /* AC'97 */
  472. static pxa2xx_audio_ops_t zeus_ac97_info = {
  473. .reset_gpio = 95,
  474. };
  475. /*
  476. * USB host
  477. */
  478. static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
  479. REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
  480. };
  481. static struct regulator_init_data zeus_ohci_regulator_data = {
  482. .constraints = {
  483. .valid_ops_mask = REGULATOR_CHANGE_STATUS,
  484. },
  485. .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies),
  486. .consumer_supplies = zeus_ohci_regulator_supplies,
  487. };
  488. static struct fixed_voltage_config zeus_ohci_regulator_config = {
  489. .supply_name = "vbus2",
  490. .microvolts = 5000000, /* 5.0V */
  491. .startup_delay = 0,
  492. .init_data = &zeus_ohci_regulator_data,
  493. };
  494. static struct platform_device zeus_ohci_regulator_device = {
  495. .name = "reg-fixed-voltage",
  496. .id = 1,
  497. .dev = {
  498. .platform_data = &zeus_ohci_regulator_config,
  499. },
  500. };
  501. static struct gpiod_lookup_table zeus_ohci_regulator_gpiod_table = {
  502. .dev_id = "reg-fixed-voltage.0",
  503. .table = {
  504. GPIO_LOOKUP("gpio-pxa", ZEUS_USB2_PWREN_GPIO,
  505. NULL, GPIO_ACTIVE_HIGH),
  506. { },
  507. },
  508. };
  509. static struct pxaohci_platform_data zeus_ohci_platform_data = {
  510. .port_mode = PMM_NPS_MODE,
  511. /* Clear Power Control Polarity Low and set Power Sense
  512. * Polarity Low. Supply power to USB ports. */
  513. .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
  514. };
  515. static void __init zeus_register_ohci(void)
  516. {
  517. /* Port 2 is shared between host and client interface. */
  518. UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
  519. pxa_set_ohci_info(&zeus_ohci_platform_data);
  520. }
  521. /*
  522. * Flat Panel
  523. */
  524. static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
  525. {
  526. gpio_set_value(ZEUS_LCD_EN_GPIO, on);
  527. }
  528. static void zeus_backlight_power(int on)
  529. {
  530. gpio_set_value(ZEUS_BKLEN_GPIO, on);
  531. }
  532. static int zeus_setup_fb_gpios(void)
  533. {
  534. int err;
  535. if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
  536. goto out_err;
  537. if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
  538. goto out_err_lcd;
  539. if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
  540. goto out_err_lcd;
  541. if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
  542. goto out_err_bkl;
  543. return 0;
  544. out_err_bkl:
  545. gpio_free(ZEUS_BKLEN_GPIO);
  546. out_err_lcd:
  547. gpio_free(ZEUS_LCD_EN_GPIO);
  548. out_err:
  549. return err;
  550. }
  551. static struct pxafb_mode_info zeus_fb_mode_info[] = {
  552. {
  553. .pixclock = 39722,
  554. .xres = 640,
  555. .yres = 480,
  556. .bpp = 16,
  557. .hsync_len = 63,
  558. .left_margin = 16,
  559. .right_margin = 81,
  560. .vsync_len = 2,
  561. .upper_margin = 12,
  562. .lower_margin = 31,
  563. .sync = 0,
  564. },
  565. };
  566. static struct pxafb_mach_info zeus_fb_info = {
  567. .modes = zeus_fb_mode_info,
  568. .num_modes = 1,
  569. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
  570. .pxafb_lcd_power = zeus_lcd_power,
  571. .pxafb_backlight_power = zeus_backlight_power,
  572. };
  573. /*
  574. * MMC/SD Device
  575. *
  576. * The card detect interrupt isn't debounced so we delay it by 250ms
  577. * to give the card a chance to fully insert/eject.
  578. */
  579. static struct pxamci_platform_data zeus_mci_platform_data = {
  580. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  581. .detect_delay_ms = 250,
  582. .gpio_card_ro_invert = 1,
  583. };
  584. static struct gpiod_lookup_table zeus_mci_gpio_table = {
  585. .dev_id = "pxa2xx-mci.0",
  586. .table = {
  587. GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_CD_GPIO,
  588. "cd", GPIO_ACTIVE_LOW),
  589. GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_WP_GPIO,
  590. "wp", GPIO_ACTIVE_HIGH),
  591. { },
  592. },
  593. };
  594. /*
  595. * USB Device Controller
  596. */
  597. static void zeus_udc_command(int cmd)
  598. {
  599. switch (cmd) {
  600. case PXA2XX_UDC_CMD_DISCONNECT:
  601. pr_info("zeus: disconnecting USB client\n");
  602. UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
  603. break;
  604. case PXA2XX_UDC_CMD_CONNECT:
  605. pr_info("zeus: connecting USB client\n");
  606. UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
  607. break;
  608. }
  609. }
  610. static struct pxa2xx_udc_mach_info zeus_udc_info = {
  611. .udc_command = zeus_udc_command,
  612. };
  613. static struct platform_device *zeus_devices[] __initdata = {
  614. &zeus_serial_device,
  615. &zeus_mtd_devices[0],
  616. &zeus_dm9k0_device,
  617. &zeus_dm9k1_device,
  618. &zeus_sram_device,
  619. &zeus_leds_device,
  620. &zeus_pcmcia_device,
  621. &zeus_max6369_device,
  622. &can_regulator_device,
  623. &zeus_ohci_regulator_device,
  624. };
  625. #ifdef CONFIG_PM
  626. static void zeus_power_off(void)
  627. {
  628. local_irq_disable();
  629. cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
  630. }
  631. #else
  632. #define zeus_power_off NULL
  633. #endif
  634. #ifdef CONFIG_APM_EMULATION
  635. static void zeus_get_power_status(struct apm_power_info *info)
  636. {
  637. /* Power supply is always present */
  638. info->ac_line_status = APM_AC_ONLINE;
  639. info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
  640. info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
  641. }
  642. static inline void zeus_setup_apm(void)
  643. {
  644. apm_get_power_status = zeus_get_power_status;
  645. }
  646. #else
  647. static inline void zeus_setup_apm(void)
  648. {
  649. }
  650. #endif
  651. static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
  652. unsigned ngpio, void *context)
  653. {
  654. int i;
  655. u8 pcb_info = 0;
  656. for (i = 0; i < 8; i++) {
  657. int pcb_bit = gpio + i + 8;
  658. if (gpio_request(pcb_bit, "pcb info")) {
  659. dev_err(&client->dev, "Can't request pcb info %d\n", i);
  660. continue;
  661. }
  662. if (gpio_direction_input(pcb_bit)) {
  663. dev_err(&client->dev, "Can't read pcb info %d\n", i);
  664. gpio_free(pcb_bit);
  665. continue;
  666. }
  667. pcb_info |= !!gpio_get_value(pcb_bit) << i;
  668. gpio_free(pcb_bit);
  669. }
  670. dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
  671. pcb_info >> 4, pcb_info & 0xf);
  672. return 0;
  673. }
  674. static struct pca953x_platform_data zeus_pca953x_pdata[] = {
  675. [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
  676. [1] = {
  677. .gpio_base = ZEUS_EXT1_GPIO_BASE,
  678. .setup = zeus_get_pcb_info,
  679. },
  680. [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
  681. };
  682. static struct i2c_board_info __initdata zeus_i2c_devices[] = {
  683. {
  684. I2C_BOARD_INFO("pca9535", 0x21),
  685. .platform_data = &zeus_pca953x_pdata[0],
  686. },
  687. {
  688. I2C_BOARD_INFO("pca9535", 0x22),
  689. .platform_data = &zeus_pca953x_pdata[1],
  690. },
  691. {
  692. I2C_BOARD_INFO("pca9535", 0x20),
  693. .platform_data = &zeus_pca953x_pdata[2],
  694. .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
  695. },
  696. { I2C_BOARD_INFO("lm75a", 0x48) },
  697. { I2C_BOARD_INFO("24c01", 0x50) },
  698. { I2C_BOARD_INFO("isl1208", 0x6f) },
  699. };
  700. static mfp_cfg_t zeus_pin_config[] __initdata = {
  701. /* AC97 */
  702. GPIO28_AC97_BITCLK,
  703. GPIO29_AC97_SDATA_IN_0,
  704. GPIO30_AC97_SDATA_OUT,
  705. GPIO31_AC97_SYNC,
  706. GPIO15_nCS_1,
  707. GPIO78_nCS_2,
  708. GPIO80_nCS_4,
  709. GPIO33_nCS_5,
  710. GPIO22_GPIO,
  711. GPIO32_MMC_CLK,
  712. GPIO92_MMC_DAT_0,
  713. GPIO109_MMC_DAT_1,
  714. GPIO110_MMC_DAT_2,
  715. GPIO111_MMC_DAT_3,
  716. GPIO112_MMC_CMD,
  717. GPIO88_USBH1_PWR,
  718. GPIO89_USBH1_PEN,
  719. GPIO119_USBH2_PWR,
  720. GPIO120_USBH2_PEN,
  721. GPIO86_LCD_LDD_16,
  722. GPIO87_LCD_LDD_17,
  723. GPIO102_GPIO,
  724. GPIO104_CIF_DD_2,
  725. GPIO105_CIF_DD_1,
  726. GPIO81_SSP3_TXD,
  727. GPIO82_SSP3_RXD,
  728. GPIO83_SSP3_SFRM,
  729. GPIO84_SSP3_SCLK,
  730. GPIO48_nPOE,
  731. GPIO49_nPWE,
  732. GPIO50_nPIOR,
  733. GPIO51_nPIOW,
  734. GPIO85_nPCE_1,
  735. GPIO54_nPCE_2,
  736. GPIO79_PSKTSEL,
  737. GPIO55_nPREG,
  738. GPIO56_nPWAIT,
  739. GPIO57_nIOIS16,
  740. GPIO36_GPIO, /* CF CD */
  741. GPIO97_GPIO, /* CF PWREN */
  742. GPIO99_GPIO, /* CF RDY */
  743. };
  744. /*
  745. * DM9k MSCx settings: SRAM, 16 bits
  746. * 17 cycles delay first access
  747. * 5 cycles delay next access
  748. * 13 cycles recovery time
  749. * faster device
  750. */
  751. #define DM9K_MSC_VALUE 0xe4c9
  752. static void __init zeus_init(void)
  753. {
  754. u16 dm9000_msc = DM9K_MSC_VALUE;
  755. u32 msc0, msc1;
  756. system_rev = __raw_readw(ZEUS_CPLD_VERSION);
  757. pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
  758. /* Fix timings for dm9000s (CS1/CS2)*/
  759. msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
  760. msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
  761. __raw_writel(msc0, MSC0);
  762. __raw_writel(msc1, MSC1);
  763. pm_power_off = zeus_power_off;
  764. zeus_setup_apm();
  765. pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
  766. gpiod_add_lookup_table(&can_regulator_gpiod_table);
  767. gpiod_add_lookup_table(&zeus_ohci_regulator_gpiod_table);
  768. platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
  769. zeus_register_ohci();
  770. if (zeus_setup_fb_gpios())
  771. pr_err("Failed to setup fb gpios\n");
  772. else
  773. pxa_set_fb_info(NULL, &zeus_fb_info);
  774. gpiod_add_lookup_table(&zeus_mci_gpio_table);
  775. pxa_set_mci_info(&zeus_mci_platform_data);
  776. pxa_set_udc_info(&zeus_udc_info);
  777. pxa_set_ac97_info(&zeus_ac97_info);
  778. pxa_set_i2c_info(NULL);
  779. i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
  780. pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
  781. spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
  782. regulator_has_full_constraints();
  783. }
  784. static struct map_desc zeus_io_desc[] __initdata = {
  785. {
  786. .virtual = (unsigned long)ZEUS_CPLD_VERSION,
  787. .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
  788. .length = 0x1000,
  789. .type = MT_DEVICE,
  790. },
  791. {
  792. .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
  793. .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
  794. .length = 0x1000,
  795. .type = MT_DEVICE,
  796. },
  797. {
  798. .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
  799. .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
  800. .length = 0x1000,
  801. .type = MT_DEVICE,
  802. },
  803. {
  804. .virtual = (unsigned long)ZEUS_PC104IO,
  805. .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
  806. .length = 0x00800000,
  807. .type = MT_DEVICE,
  808. },
  809. {
  810. /*
  811. * ISA I/O space mapping:
  812. * - ports 0x0000-0x0fff are PC/104
  813. * - ports 0x10000-0x10fff are PCMCIA slot 1
  814. * - ports 0x11000-0x11fff are PC/104
  815. */
  816. .virtual = PCI_IO_VIRT_BASE,
  817. .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
  818. .length = 0x1000,
  819. .type = MT_DEVICE,
  820. },
  821. };
  822. static void __init zeus_map_io(void)
  823. {
  824. pxa27x_map_io();
  825. iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
  826. /* Clear PSPR to ensure a full restart on wake-up. */
  827. PMCR = PSPR = 0;
  828. /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
  829. writel(readl(OSCC) | OSCC_OON, OSCC);
  830. /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
  831. * float chip selects and PCMCIA */
  832. PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
  833. }
  834. MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
  835. /* Maintainer: Marc Zyngier <[email protected]> */
  836. .atag_offset = 0x100,
  837. .map_io = zeus_map_io,
  838. .nr_irqs = ZEUS_NR_IRQS,
  839. .init_irq = zeus_init_irq,
  840. .handle_irq = pxa27x_handle_irq,
  841. .init_time = pxa_timer_init,
  842. .init_machine = zeus_init,
  843. .restart = pxa_restart,
  844. MACHINE_END