sleep.S 4.2 KB

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  1. /*
  2. * Low-level PXA250/210 sleep/wakeUp support
  3. *
  4. * Initial SA1110 code:
  5. * Copyright (c) 2001 Cliff Brake <[email protected]>
  6. *
  7. * Adapted for PXA by Nicolas Pitre:
  8. * Copyright (c) 2002 Monta Vista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License.
  12. */
  13. #include <linux/linkage.h>
  14. #include <asm/assembler.h>
  15. #include "smemc.h"
  16. #include "pxa2xx-regs.h"
  17. #define MDREFR_KDIV 0x200a4000 // all banks
  18. #define CCCR_SLEEP 0x00000107 // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
  19. #define CCCR_N_MASK 0x00000380
  20. #define CCCR_M_MASK 0x00000060
  21. #define CCCR_L_MASK 0x0000001f
  22. .text
  23. #ifdef CONFIG_PXA3xx
  24. /*
  25. * pxa3xx_finish_suspend() - forces CPU into sleep state (S2D3C4)
  26. */
  27. ENTRY(pxa3xx_finish_suspend)
  28. mov r0, #0x06 @ S2D3C4 mode
  29. mcr p14, 0, r0, c7, c0, 0 @ enter sleep
  30. 20: b 20b @ waiting for sleep
  31. #endif /* CONFIG_PXA3xx */
  32. #ifdef CONFIG_PXA27x
  33. /*
  34. * pxa27x_finish_suspend()
  35. *
  36. * Forces CPU into sleep state.
  37. *
  38. * r0 = value for PWRMODE M field for desired sleep state
  39. */
  40. ENTRY(pxa27x_finish_suspend)
  41. @ Put the processor to sleep
  42. @ (also workaround for sighting 28071)
  43. @ prepare value for sleep mode
  44. mov r1, r0 @ sleep mode
  45. @ prepare pointer to physical address 0 (virtual mapping in generic.c)
  46. mov r2, #UNCACHED_PHYS_0
  47. @ prepare SDRAM refresh settings
  48. ldr r4, =MDREFR
  49. ldr r5, [r4]
  50. @ enable SDRAM self-refresh mode
  51. orr r5, r5, #MDREFR_SLFRSH
  52. @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
  53. ldr r6, =MDREFR_KDIV
  54. orr r5, r5, r6
  55. @ Intel PXA270 Specification Update notes problems sleeping
  56. @ with core operating above 91 MHz
  57. @ (see Errata 50, ...processor does not exit from sleep...)
  58. ldr r6, =CCCR
  59. ldr r8, [r6] @ keep original value for resume
  60. ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
  61. mov r0, #0x2 @ prepare value for CLKCFG
  62. @ align execution to a cache line
  63. b pxa_cpu_do_suspend
  64. #endif
  65. #ifdef CONFIG_PXA25x
  66. /*
  67. * pxa25x_finish_suspend()
  68. *
  69. * Forces CPU into sleep state.
  70. *
  71. * r0 = value for PWRMODE M field for desired sleep state
  72. */
  73. ENTRY(pxa25x_finish_suspend)
  74. @ prepare value for sleep mode
  75. mov r1, r0 @ sleep mode
  76. @ prepare pointer to physical address 0 (virtual mapping in generic.c)
  77. mov r2, #UNCACHED_PHYS_0
  78. @ prepare SDRAM refresh settings
  79. ldr r4, =MDREFR
  80. ldr r5, [r4]
  81. @ enable SDRAM self-refresh mode
  82. orr r5, r5, #MDREFR_SLFRSH
  83. @ Intel PXA255 Specification Update notes problems
  84. @ about suspending with PXBus operating above 133MHz
  85. @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
  86. @
  87. @ We keep the change-down close to the actual suspend on SDRAM
  88. @ as possible to eliminate messing about with the refresh clock
  89. @ as the system will restore with the original speed settings
  90. @
  91. @ Ben Dooks, 13-Sep-2004
  92. ldr r6, =CCCR
  93. ldr r8, [r6] @ keep original value for resume
  94. @ ensure x1 for run and turbo mode with memory clock
  95. bic r7, r8, #CCCR_M_MASK | CCCR_N_MASK
  96. orr r7, r7, #(1<<5) | (2<<7)
  97. @ check that the memory frequency is within limits
  98. and r14, r7, #CCCR_L_MASK
  99. teq r14, #1
  100. bicne r7, r7, #CCCR_L_MASK
  101. orrne r7, r7, #1 @@ 99.53MHz
  102. @ get ready for the change
  103. @ note, turbo is not preserved over sleep so there is no
  104. @ point in preserving it here. we save it on the stack with the
  105. @ other CP registers instead.
  106. mov r0, #0
  107. mcr p14, 0, r0, c6, c0, 0
  108. orr r0, r0, #2 @ initiate change bit
  109. b pxa_cpu_do_suspend
  110. #endif
  111. .ltorg
  112. .align 5
  113. pxa_cpu_do_suspend:
  114. @ All needed values are now in registers.
  115. @ These last instructions should be in cache
  116. @ initiate the frequency change...
  117. str r7, [r6]
  118. mcr p14, 0, r0, c6, c0, 0
  119. @ restore the original cpu speed value for resume
  120. str r8, [r6]
  121. @ need 6 13-MHz cycles before changing PWRMODE
  122. @ just set frequency to 91-MHz... 6*91/13 = 42
  123. mov r0, #42
  124. 10: subs r0, r0, #1
  125. bne 10b
  126. @ Do not reorder...
  127. @ Intel PXA270 Specification Update notes problems performing
  128. @ external accesses after SDRAM is put in self-refresh mode
  129. @ (see Errata 38 ...hangs when entering self-refresh mode)
  130. @ force address lines low by reading at physical address 0
  131. ldr r3, [r2]
  132. @ put SDRAM into self-refresh
  133. str r5, [r4]
  134. @ enter sleep mode
  135. mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
  136. 20: b 20b @ loop waiting for sleep