saar.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-pxa/saar.c
  4. *
  5. * Support for the Marvell PXA930 Handheld Platform (aka SAAR)
  6. *
  7. * Copyright (C) 2007-2008 Marvell International Ltd.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/init.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/clk.h>
  15. #include <linux/gpio.h>
  16. #include <linux/delay.h>
  17. #include <linux/fb.h>
  18. #include <linux/i2c.h>
  19. #include <linux/platform_data/i2c-pxa.h>
  20. #include <linux/smc91x.h>
  21. #include <linux/mfd/da903x.h>
  22. #include <linux/mtd/mtd.h>
  23. #include <linux/mtd/partitions.h>
  24. #include <linux/mtd/onenand.h>
  25. #include <asm/mach-types.h>
  26. #include <asm/mach/arch.h>
  27. #include <asm/mach/flash.h>
  28. #include "pxa930.h"
  29. #include <linux/platform_data/video-pxafb.h>
  30. #include "devices.h"
  31. #include "generic.h"
  32. #define GPIO_LCD_RESET (16)
  33. /* SAAR MFP configurations */
  34. static mfp_cfg_t saar_mfp_cfg[] __initdata = {
  35. /* LCD */
  36. GPIO23_LCD_DD0,
  37. GPIO24_LCD_DD1,
  38. GPIO25_LCD_DD2,
  39. GPIO26_LCD_DD3,
  40. GPIO27_LCD_DD4,
  41. GPIO28_LCD_DD5,
  42. GPIO29_LCD_DD6,
  43. GPIO44_LCD_DD7,
  44. GPIO21_LCD_CS,
  45. GPIO22_LCD_VSYNC,
  46. GPIO17_LCD_FCLK_RD,
  47. GPIO18_LCD_LCLK_A0,
  48. GPIO19_LCD_PCLK_WR,
  49. GPIO16_GPIO, /* LCD reset */
  50. /* Ethernet */
  51. DF_nCS1_nCS3,
  52. GPIO97_GPIO,
  53. /* DFI */
  54. DF_INT_RnB_ND_INT_RnB,
  55. DF_nRE_nOE_ND_nRE,
  56. DF_nWE_ND_nWE,
  57. DF_CLE_nOE_ND_CLE,
  58. DF_nADV1_ALE_ND_ALE,
  59. DF_nADV2_ALE_nCS3,
  60. DF_nCS0_ND_nCS0,
  61. DF_IO0_ND_IO0,
  62. DF_IO1_ND_IO1,
  63. DF_IO2_ND_IO2,
  64. DF_IO3_ND_IO3,
  65. DF_IO4_ND_IO4,
  66. DF_IO5_ND_IO5,
  67. DF_IO6_ND_IO6,
  68. DF_IO7_ND_IO7,
  69. DF_IO8_ND_IO8,
  70. DF_IO9_ND_IO9,
  71. DF_IO10_ND_IO10,
  72. DF_IO11_ND_IO11,
  73. DF_IO12_ND_IO12,
  74. DF_IO13_ND_IO13,
  75. DF_IO14_ND_IO14,
  76. DF_IO15_ND_IO15,
  77. };
  78. #define SAAR_ETH_PHYS (0x14000000)
  79. static struct resource smc91x_resources[] = {
  80. [0] = {
  81. .start = (SAAR_ETH_PHYS + 0x300),
  82. .end = (SAAR_ETH_PHYS + 0xfffff),
  83. .flags = IORESOURCE_MEM,
  84. },
  85. [1] = {
  86. .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
  87. .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
  88. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  89. }
  90. };
  91. static struct smc91x_platdata saar_smc91x_info = {
  92. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
  93. };
  94. static struct platform_device smc91x_device = {
  95. .name = "smc91x",
  96. .id = 0,
  97. .num_resources = ARRAY_SIZE(smc91x_resources),
  98. .resource = smc91x_resources,
  99. .dev = {
  100. .platform_data = &saar_smc91x_info,
  101. },
  102. };
  103. #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
  104. static uint16_t lcd_power_on[] = {
  105. /* single frame */
  106. SMART_CMD_NOOP,
  107. SMART_CMD(0x00),
  108. SMART_DELAY(0),
  109. SMART_CMD_NOOP,
  110. SMART_CMD(0x00),
  111. SMART_DELAY(0),
  112. SMART_CMD_NOOP,
  113. SMART_CMD(0x00),
  114. SMART_DELAY(0),
  115. SMART_CMD_NOOP,
  116. SMART_CMD(0x00),
  117. SMART_DELAY(10),
  118. /* calibration control */
  119. SMART_CMD(0x00),
  120. SMART_CMD(0xA4),
  121. SMART_DAT(0x80),
  122. SMART_DAT(0x01),
  123. SMART_DELAY(150),
  124. /*Power-On Init sequence*/
  125. SMART_CMD(0x00), /* output ctrl */
  126. SMART_CMD(0x01),
  127. SMART_DAT(0x01),
  128. SMART_DAT(0x00),
  129. SMART_CMD(0x00), /* wave ctrl */
  130. SMART_CMD(0x02),
  131. SMART_DAT(0x07),
  132. SMART_DAT(0x00),
  133. SMART_CMD(0x00),
  134. SMART_CMD(0x03), /* entry mode */
  135. SMART_DAT(0xD0),
  136. SMART_DAT(0x30),
  137. SMART_CMD(0x00),
  138. SMART_CMD(0x08), /* display ctrl 2 */
  139. SMART_DAT(0x08),
  140. SMART_DAT(0x08),
  141. SMART_CMD(0x00),
  142. SMART_CMD(0x09), /* display ctrl 3 */
  143. SMART_DAT(0x04),
  144. SMART_DAT(0x2F),
  145. SMART_CMD(0x00),
  146. SMART_CMD(0x0A), /* display ctrl 4 */
  147. SMART_DAT(0x00),
  148. SMART_DAT(0x08),
  149. SMART_CMD(0x00),
  150. SMART_CMD(0x0D), /* Frame Marker position */
  151. SMART_DAT(0x00),
  152. SMART_DAT(0x08),
  153. SMART_CMD(0x00),
  154. SMART_CMD(0x60), /* Driver output control */
  155. SMART_DAT(0x27),
  156. SMART_DAT(0x00),
  157. SMART_CMD(0x00),
  158. SMART_CMD(0x61), /* Base image display control */
  159. SMART_DAT(0x00),
  160. SMART_DAT(0x01),
  161. SMART_CMD(0x00),
  162. SMART_CMD(0x30), /* Y settings 30h-3Dh */
  163. SMART_DAT(0x07),
  164. SMART_DAT(0x07),
  165. SMART_CMD(0x00),
  166. SMART_CMD(0x31),
  167. SMART_DAT(0x00),
  168. SMART_DAT(0x07),
  169. SMART_CMD(0x00),
  170. SMART_CMD(0x32), /* Timing(3), ASW HOLD=0.5CLK */
  171. SMART_DAT(0x04),
  172. SMART_DAT(0x00),
  173. SMART_CMD(0x00),
  174. SMART_CMD(0x33), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
  175. SMART_DAT(0x03),
  176. SMART_DAT(0x03),
  177. SMART_CMD(0x00),
  178. SMART_CMD(0x34),
  179. SMART_DAT(0x00),
  180. SMART_DAT(0x00),
  181. SMART_CMD(0x00),
  182. SMART_CMD(0x35),
  183. SMART_DAT(0x02),
  184. SMART_DAT(0x05),
  185. SMART_CMD(0x00),
  186. SMART_CMD(0x36),
  187. SMART_DAT(0x1F),
  188. SMART_DAT(0x1F),
  189. SMART_CMD(0x00),
  190. SMART_CMD(0x37),
  191. SMART_DAT(0x07),
  192. SMART_DAT(0x07),
  193. SMART_CMD(0x00),
  194. SMART_CMD(0x38),
  195. SMART_DAT(0x00),
  196. SMART_DAT(0x07),
  197. SMART_CMD(0x00),
  198. SMART_CMD(0x39),
  199. SMART_DAT(0x04),
  200. SMART_DAT(0x00),
  201. SMART_CMD(0x00),
  202. SMART_CMD(0x3A),
  203. SMART_DAT(0x03),
  204. SMART_DAT(0x03),
  205. SMART_CMD(0x00),
  206. SMART_CMD(0x3B),
  207. SMART_DAT(0x00),
  208. SMART_DAT(0x00),
  209. SMART_CMD(0x00),
  210. SMART_CMD(0x3C),
  211. SMART_DAT(0x02),
  212. SMART_DAT(0x05),
  213. SMART_CMD(0x00),
  214. SMART_CMD(0x3D),
  215. SMART_DAT(0x1F),
  216. SMART_DAT(0x1F),
  217. SMART_CMD(0x00), /* Display control 1 */
  218. SMART_CMD(0x07),
  219. SMART_DAT(0x00),
  220. SMART_DAT(0x01),
  221. SMART_CMD(0x00), /* Power control 5 */
  222. SMART_CMD(0x17),
  223. SMART_DAT(0x00),
  224. SMART_DAT(0x01),
  225. SMART_CMD(0x00), /* Power control 1 */
  226. SMART_CMD(0x10),
  227. SMART_DAT(0x10),
  228. SMART_DAT(0xB0),
  229. SMART_CMD(0x00), /* Power control 2 */
  230. SMART_CMD(0x11),
  231. SMART_DAT(0x01),
  232. SMART_DAT(0x30),
  233. SMART_CMD(0x00), /* Power control 3 */
  234. SMART_CMD(0x12),
  235. SMART_DAT(0x01),
  236. SMART_DAT(0x9E),
  237. SMART_CMD(0x00), /* Power control 4 */
  238. SMART_CMD(0x13),
  239. SMART_DAT(0x17),
  240. SMART_DAT(0x00),
  241. SMART_CMD(0x00), /* Power control 3 */
  242. SMART_CMD(0x12),
  243. SMART_DAT(0x01),
  244. SMART_DAT(0xBE),
  245. SMART_DELAY(100),
  246. /* display mode : 240*320 */
  247. SMART_CMD(0x00), /* RAM address set(H) 0*/
  248. SMART_CMD(0x20),
  249. SMART_DAT(0x00),
  250. SMART_DAT(0x00),
  251. SMART_CMD(0x00), /* RAM address set(V) 4*/
  252. SMART_CMD(0x21),
  253. SMART_DAT(0x00),
  254. SMART_DAT(0x00),
  255. SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/
  256. SMART_CMD(0x50),
  257. SMART_DAT(0x00),
  258. SMART_DAT(0x00),
  259. SMART_CMD(0x00), /* End of Window RAM address set(H) 12*/
  260. SMART_CMD(0x51),
  261. SMART_DAT(0x00),
  262. SMART_DAT(0xEF),
  263. SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/
  264. SMART_CMD(0x52),
  265. SMART_DAT(0x00),
  266. SMART_DAT(0x00),
  267. SMART_CMD(0x00), /* End of Window RAM address set(V) 20*/
  268. SMART_CMD(0x53),
  269. SMART_DAT(0x01),
  270. SMART_DAT(0x3F),
  271. SMART_CMD(0x00), /* Panel interface control 1 */
  272. SMART_CMD(0x90),
  273. SMART_DAT(0x00),
  274. SMART_DAT(0x1A),
  275. SMART_CMD(0x00), /* Panel interface control 2 */
  276. SMART_CMD(0x92),
  277. SMART_DAT(0x04),
  278. SMART_DAT(0x00),
  279. SMART_CMD(0x00), /* Panel interface control 3 */
  280. SMART_CMD(0x93),
  281. SMART_DAT(0x00),
  282. SMART_DAT(0x05),
  283. SMART_DELAY(20),
  284. };
  285. static uint16_t lcd_panel_on[] = {
  286. SMART_CMD(0x00),
  287. SMART_CMD(0x07),
  288. SMART_DAT(0x00),
  289. SMART_DAT(0x21),
  290. SMART_DELAY(1),
  291. SMART_CMD(0x00),
  292. SMART_CMD(0x07),
  293. SMART_DAT(0x00),
  294. SMART_DAT(0x61),
  295. SMART_DELAY(100),
  296. SMART_CMD(0x00),
  297. SMART_CMD(0x07),
  298. SMART_DAT(0x01),
  299. SMART_DAT(0x73),
  300. SMART_DELAY(1),
  301. };
  302. static uint16_t lcd_panel_off[] = {
  303. SMART_CMD(0x00),
  304. SMART_CMD(0x07),
  305. SMART_DAT(0x00),
  306. SMART_DAT(0x72),
  307. SMART_DELAY(40),
  308. SMART_CMD(0x00),
  309. SMART_CMD(0x07),
  310. SMART_DAT(0x00),
  311. SMART_DAT(0x01),
  312. SMART_DELAY(1),
  313. SMART_CMD(0x00),
  314. SMART_CMD(0x07),
  315. SMART_DAT(0x00),
  316. SMART_DAT(0x00),
  317. SMART_DELAY(1),
  318. };
  319. static uint16_t lcd_power_off[] = {
  320. SMART_CMD(0x00),
  321. SMART_CMD(0x10),
  322. SMART_DAT(0x00),
  323. SMART_DAT(0x80),
  324. SMART_CMD(0x00),
  325. SMART_CMD(0x11),
  326. SMART_DAT(0x01),
  327. SMART_DAT(0x60),
  328. SMART_CMD(0x00),
  329. SMART_CMD(0x12),
  330. SMART_DAT(0x01),
  331. SMART_DAT(0xAE),
  332. SMART_DELAY(40),
  333. SMART_CMD(0x00),
  334. SMART_CMD(0x10),
  335. SMART_DAT(0x00),
  336. SMART_DAT(0x00),
  337. };
  338. static uint16_t update_framedata[] = {
  339. /* set display ram: 240*320 */
  340. SMART_CMD(0x00), /* RAM address set(H) 0*/
  341. SMART_CMD(0x20),
  342. SMART_DAT(0x00),
  343. SMART_DAT(0x00),
  344. SMART_CMD(0x00), /* RAM address set(V) 4*/
  345. SMART_CMD(0x21),
  346. SMART_DAT(0x00),
  347. SMART_DAT(0x00),
  348. SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
  349. SMART_CMD(0x50),
  350. SMART_DAT(0x00),
  351. SMART_DAT(0x00),
  352. SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */
  353. SMART_CMD(0x51),
  354. SMART_DAT(0x00),
  355. SMART_DAT(0xEF),
  356. SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
  357. SMART_CMD(0x52),
  358. SMART_DAT(0x00),
  359. SMART_DAT(0x00),
  360. SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */
  361. SMART_CMD(0x53),
  362. SMART_DAT(0x01),
  363. SMART_DAT(0x3F),
  364. /* wait for vsync cmd before transferring frame data */
  365. SMART_CMD_WAIT_FOR_VSYNC,
  366. /* write ram */
  367. SMART_CMD(0x00),
  368. SMART_CMD(0x22),
  369. /* write frame data */
  370. SMART_CMD_WRITE_FRAME,
  371. };
  372. static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var)
  373. {
  374. static int pin_requested = 0;
  375. struct fb_info *info = container_of(var, struct fb_info, var);
  376. int err;
  377. if (!pin_requested) {
  378. err = gpio_request(GPIO_LCD_RESET, "lcd reset");
  379. if (err) {
  380. pr_err("failed to request gpio for LCD reset\n");
  381. return;
  382. }
  383. gpio_direction_output(GPIO_LCD_RESET, 0);
  384. pin_requested = 1;
  385. }
  386. if (on) {
  387. gpio_set_value(GPIO_LCD_RESET, 0); msleep(100);
  388. gpio_set_value(GPIO_LCD_RESET, 1); msleep(10);
  389. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on));
  390. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on));
  391. } else {
  392. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off));
  393. pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off));
  394. }
  395. err = pxafb_smart_flush(info);
  396. if (err)
  397. pr_err("%s: timed out\n", __func__);
  398. }
  399. static void ltm022a97a_update(struct fb_info *info)
  400. {
  401. pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
  402. pxafb_smart_flush(info);
  403. }
  404. static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = {
  405. [0] = {
  406. .xres = 240,
  407. .yres = 320,
  408. .bpp = 16,
  409. .a0csrd_set_hld = 30,
  410. .a0cswr_set_hld = 30,
  411. .wr_pulse_width = 30,
  412. .rd_pulse_width = 30,
  413. .op_hold_time = 30,
  414. .cmd_inh_time = 60,
  415. /* L_LCLK_A0 and L_LCLK_RD active low */
  416. .sync = FB_SYNC_HOR_HIGH_ACT |
  417. FB_SYNC_VERT_HIGH_ACT,
  418. },
  419. };
  420. static struct pxafb_mach_info saar_lcd_info = {
  421. .modes = toshiba_ltm022a97a_modes,
  422. .num_modes = 1,
  423. .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
  424. .pxafb_lcd_power = ltm022a97a_lcd_power,
  425. .smart_update = ltm022a97a_update,
  426. };
  427. static void __init saar_init_lcd(void)
  428. {
  429. pxa_set_fb_info(NULL, &saar_lcd_info);
  430. }
  431. #else
  432. static inline void saar_init_lcd(void) {}
  433. #endif
  434. #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
  435. static struct da9034_backlight_pdata saar_da9034_backlight = {
  436. .output_current = 4, /* 4mA */
  437. };
  438. static struct da903x_subdev_info saar_da9034_subdevs[] = {
  439. [0] = {
  440. .name = "da903x-backlight",
  441. .id = DA9034_ID_WLED,
  442. .platform_data = &saar_da9034_backlight,
  443. },
  444. };
  445. static struct da903x_platform_data saar_da9034_info = {
  446. .num_subdevs = ARRAY_SIZE(saar_da9034_subdevs),
  447. .subdevs = saar_da9034_subdevs,
  448. };
  449. static struct i2c_board_info saar_i2c_info[] = {
  450. [0] = {
  451. .type = "da9034",
  452. .addr = 0x34,
  453. .platform_data = &saar_da9034_info,
  454. .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
  455. },
  456. };
  457. static void __init saar_init_i2c(void)
  458. {
  459. pxa_set_i2c_info(NULL);
  460. i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info));
  461. }
  462. #else
  463. static inline void saar_init_i2c(void) {}
  464. #endif
  465. #if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
  466. static struct mtd_partition saar_onenand_partitions[] = {
  467. {
  468. .name = "bootloader",
  469. .offset = 0,
  470. .size = SZ_1M,
  471. .mask_flags = MTD_WRITEABLE,
  472. }, {
  473. .name = "reserved",
  474. .offset = MTDPART_OFS_APPEND,
  475. .size = SZ_128K,
  476. .mask_flags = MTD_WRITEABLE,
  477. }, {
  478. .name = "reserved",
  479. .offset = MTDPART_OFS_APPEND,
  480. .size = SZ_8M,
  481. .mask_flags = MTD_WRITEABLE,
  482. }, {
  483. .name = "kernel",
  484. .offset = MTDPART_OFS_APPEND,
  485. .size = (SZ_2M + SZ_1M),
  486. .mask_flags = 0,
  487. }, {
  488. .name = "filesystem",
  489. .offset = MTDPART_OFS_APPEND,
  490. .size = SZ_32M + SZ_16M,
  491. .mask_flags = 0,
  492. }
  493. };
  494. static struct onenand_platform_data saar_onenand_info = {
  495. .parts = saar_onenand_partitions,
  496. .nr_parts = ARRAY_SIZE(saar_onenand_partitions),
  497. };
  498. #define SMC_CS0_PHYS_BASE (0x10000000)
  499. static struct resource saar_resource_onenand[] = {
  500. [0] = {
  501. .start = SMC_CS0_PHYS_BASE,
  502. .end = SMC_CS0_PHYS_BASE + SZ_1M,
  503. .flags = IORESOURCE_MEM,
  504. },
  505. };
  506. static struct platform_device saar_device_onenand = {
  507. .name = "onenand-flash",
  508. .id = -1,
  509. .dev = {
  510. .platform_data = &saar_onenand_info,
  511. },
  512. .resource = saar_resource_onenand,
  513. .num_resources = ARRAY_SIZE(saar_resource_onenand),
  514. };
  515. static void __init saar_init_onenand(void)
  516. {
  517. platform_device_register(&saar_device_onenand);
  518. }
  519. #else
  520. static void __init saar_init_onenand(void) {}
  521. #endif
  522. static void __init saar_init(void)
  523. {
  524. /* initialize MFP configurations */
  525. pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
  526. pxa_set_ffuart_info(NULL);
  527. pxa_set_btuart_info(NULL);
  528. pxa_set_stuart_info(NULL);
  529. platform_device_register(&smc91x_device);
  530. saar_init_onenand();
  531. saar_init_i2c();
  532. saar_init_lcd();
  533. }
  534. MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
  535. /* Maintainer: Eric Miao <[email protected]> */
  536. .atag_offset = 0x100,
  537. .map_io = pxa3xx_map_io,
  538. .nr_irqs = PXA_NR_IRQS,
  539. .init_irq = pxa3xx_init_irq,
  540. .handle_irq = pxa3xx_handle_irq,
  541. .init_time = pxa_timer_init,
  542. .init_machine = saar_init,
  543. .restart = pxa_restart,
  544. MACHINE_END