pxa3xx.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-pxa/pxa3xx.c
  4. *
  5. * code specific to pxa3xx aka Monahans
  6. *
  7. * Copyright (C) 2006 Marvell International Ltd.
  8. *
  9. * 2007-09-02: eric miao <[email protected]>
  10. * initial version
  11. */
  12. #include <linux/dmaengine.h>
  13. #include <linux/dma/pxa-dma.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/gpio-pxa.h>
  18. #include <linux/pm.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/irq.h>
  21. #include <linux/irqchip.h>
  22. #include <linux/io.h>
  23. #include <linux/of.h>
  24. #include <linux/syscore_ops.h>
  25. #include <linux/platform_data/i2c-pxa.h>
  26. #include <linux/platform_data/mmp_dma.h>
  27. #include <linux/soc/pxa/cpu.h>
  28. #include <linux/clk/pxa.h>
  29. #include <asm/mach/map.h>
  30. #include <asm/suspend.h>
  31. #include "pxa3xx-regs.h"
  32. #include "reset.h"
  33. #include <linux/platform_data/usb-ohci-pxa27x.h>
  34. #include "pm.h"
  35. #include "addr-map.h"
  36. #include "smemc.h"
  37. #include "irqs.h"
  38. #include "generic.h"
  39. #include "devices.h"
  40. #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
  41. #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
  42. extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
  43. /*
  44. * NAND NFC: DFI bus arbitration subset
  45. */
  46. #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
  47. #define NDCR_ND_ARB_EN (1 << 12)
  48. #define NDCR_ND_ARB_CNTL (1 << 19)
  49. #define CKEN_BOOT 11 /* < Boot rom clock enable */
  50. #define CKEN_TPM 19 /* < TPM clock enable */
  51. #define CKEN_HSIO2 41 /* < HSIO2 clock enable */
  52. #ifdef CONFIG_PM
  53. #define ISRAM_START 0x5c000000
  54. #define ISRAM_SIZE SZ_256K
  55. static void __iomem *sram;
  56. static unsigned long wakeup_src;
  57. /*
  58. * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
  59. * memory controller has to be reinitialised, so we place some code
  60. * in the SRAM to perform this function.
  61. *
  62. * We disable FIQs across the standby - otherwise, we might receive a
  63. * FIQ while the SDRAM is unavailable.
  64. */
  65. static void pxa3xx_cpu_standby(unsigned int pwrmode)
  66. {
  67. void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
  68. memcpy_toio(sram + 0x8000, pm_enter_standby_start,
  69. pm_enter_standby_end - pm_enter_standby_start);
  70. AD2D0SR = ~0;
  71. AD2D1SR = ~0;
  72. AD2D0ER = wakeup_src;
  73. AD2D1ER = 0;
  74. ASCR = ASCR;
  75. ARSR = ARSR;
  76. local_fiq_disable();
  77. fn(pwrmode);
  78. local_fiq_enable();
  79. AD2D0ER = 0;
  80. AD2D1ER = 0;
  81. }
  82. /*
  83. * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
  84. * PXA3xx development kits assumes that the resuming process continues
  85. * with the address stored within the first 4 bytes of SDRAM. The PSPR
  86. * register is used privately by BootROM and OBM, and _must_ be set to
  87. * 0x5c014000 for the moment.
  88. */
  89. static void pxa3xx_cpu_pm_suspend(void)
  90. {
  91. volatile unsigned long *p = (volatile void *)0xc0000000;
  92. unsigned long saved_data = *p;
  93. #ifndef CONFIG_IWMMXT
  94. u64 acc0;
  95. asm volatile(".arch_extension xscale\n\t"
  96. "mra %Q0, %R0, acc0" : "=r" (acc0));
  97. #endif
  98. /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
  99. CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
  100. CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
  101. /* clear and setup wakeup source */
  102. AD3SR = ~0;
  103. AD3ER = wakeup_src;
  104. ASCR = ASCR;
  105. ARSR = ARSR;
  106. PCFR |= (1u << 13); /* L1_DIS */
  107. PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
  108. PSPR = 0x5c014000;
  109. /* overwrite with the resume address */
  110. *p = __pa_symbol(cpu_resume);
  111. cpu_suspend(0, pxa3xx_finish_suspend);
  112. *p = saved_data;
  113. AD3ER = 0;
  114. #ifndef CONFIG_IWMMXT
  115. asm volatile(".arch_extension xscale\n\t"
  116. "mar acc0, %Q0, %R0" : "=r" (acc0));
  117. #endif
  118. }
  119. static void pxa3xx_cpu_pm_enter(suspend_state_t state)
  120. {
  121. /*
  122. * Don't sleep if no wakeup sources are defined
  123. */
  124. if (wakeup_src == 0) {
  125. printk(KERN_ERR "Not suspending: no wakeup sources\n");
  126. return;
  127. }
  128. switch (state) {
  129. case PM_SUSPEND_STANDBY:
  130. pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
  131. break;
  132. case PM_SUSPEND_MEM:
  133. pxa3xx_cpu_pm_suspend();
  134. break;
  135. }
  136. }
  137. static int pxa3xx_cpu_pm_valid(suspend_state_t state)
  138. {
  139. return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
  140. }
  141. static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
  142. .valid = pxa3xx_cpu_pm_valid,
  143. .enter = pxa3xx_cpu_pm_enter,
  144. };
  145. static void __init pxa3xx_init_pm(void)
  146. {
  147. sram = ioremap(ISRAM_START, ISRAM_SIZE);
  148. if (!sram) {
  149. printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
  150. return;
  151. }
  152. /*
  153. * Since we copy wakeup code into the SRAM, we need to ensure
  154. * that it is preserved over the low power modes. Note: bit 8
  155. * is undocumented in the developer manual, but must be set.
  156. */
  157. AD1R |= ADXR_L2 | ADXR_R0;
  158. AD2R |= ADXR_L2 | ADXR_R0;
  159. AD3R |= ADXR_L2 | ADXR_R0;
  160. /*
  161. * Clear the resume enable registers.
  162. */
  163. AD1D0ER = 0;
  164. AD2D0ER = 0;
  165. AD2D1ER = 0;
  166. AD3ER = 0;
  167. pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
  168. }
  169. static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
  170. {
  171. unsigned long flags, mask = 0;
  172. switch (d->irq) {
  173. case IRQ_SSP3:
  174. mask = ADXER_MFP_WSSP3;
  175. break;
  176. case IRQ_MSL:
  177. mask = ADXER_WMSL0;
  178. break;
  179. case IRQ_USBH2:
  180. case IRQ_USBH1:
  181. mask = ADXER_WUSBH;
  182. break;
  183. case IRQ_KEYPAD:
  184. mask = ADXER_WKP;
  185. break;
  186. case IRQ_AC97:
  187. mask = ADXER_MFP_WAC97;
  188. break;
  189. case IRQ_USIM:
  190. mask = ADXER_WUSIM0;
  191. break;
  192. case IRQ_SSP2:
  193. mask = ADXER_MFP_WSSP2;
  194. break;
  195. case IRQ_I2C:
  196. mask = ADXER_MFP_WI2C;
  197. break;
  198. case IRQ_STUART:
  199. mask = ADXER_MFP_WUART3;
  200. break;
  201. case IRQ_BTUART:
  202. mask = ADXER_MFP_WUART2;
  203. break;
  204. case IRQ_FFUART:
  205. mask = ADXER_MFP_WUART1;
  206. break;
  207. case IRQ_MMC:
  208. mask = ADXER_MFP_WMMC1;
  209. break;
  210. case IRQ_SSP:
  211. mask = ADXER_MFP_WSSP1;
  212. break;
  213. case IRQ_RTCAlrm:
  214. mask = ADXER_WRTC;
  215. break;
  216. case IRQ_SSP4:
  217. mask = ADXER_MFP_WSSP4;
  218. break;
  219. case IRQ_TSI:
  220. mask = ADXER_WTSI;
  221. break;
  222. case IRQ_USIM2:
  223. mask = ADXER_WUSIM1;
  224. break;
  225. case IRQ_MMC2:
  226. mask = ADXER_MFP_WMMC2;
  227. break;
  228. case IRQ_NAND:
  229. mask = ADXER_MFP_WFLASH;
  230. break;
  231. case IRQ_USB2:
  232. mask = ADXER_WUSB2;
  233. break;
  234. case IRQ_WAKEUP0:
  235. mask = ADXER_WEXTWAKE0;
  236. break;
  237. case IRQ_WAKEUP1:
  238. mask = ADXER_WEXTWAKE1;
  239. break;
  240. case IRQ_MMC3:
  241. mask = ADXER_MFP_GEN12;
  242. break;
  243. default:
  244. return -EINVAL;
  245. }
  246. local_irq_save(flags);
  247. if (on)
  248. wakeup_src |= mask;
  249. else
  250. wakeup_src &= ~mask;
  251. local_irq_restore(flags);
  252. return 0;
  253. }
  254. #else
  255. static inline void pxa3xx_init_pm(void) {}
  256. #define pxa3xx_set_wake NULL
  257. #endif
  258. static void pxa_ack_ext_wakeup(struct irq_data *d)
  259. {
  260. PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
  261. }
  262. static void pxa_mask_ext_wakeup(struct irq_data *d)
  263. {
  264. pxa_mask_irq(d);
  265. PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
  266. }
  267. static void pxa_unmask_ext_wakeup(struct irq_data *d)
  268. {
  269. pxa_unmask_irq(d);
  270. PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
  271. }
  272. static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
  273. {
  274. if (flow_type & IRQ_TYPE_EDGE_RISING)
  275. PWER |= 1 << (d->irq - IRQ_WAKEUP0);
  276. if (flow_type & IRQ_TYPE_EDGE_FALLING)
  277. PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
  278. return 0;
  279. }
  280. static struct irq_chip pxa_ext_wakeup_chip = {
  281. .name = "WAKEUP",
  282. .irq_ack = pxa_ack_ext_wakeup,
  283. .irq_mask = pxa_mask_ext_wakeup,
  284. .irq_unmask = pxa_unmask_ext_wakeup,
  285. .irq_set_type = pxa_set_ext_wakeup_type,
  286. };
  287. static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
  288. unsigned int))
  289. {
  290. int irq;
  291. for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
  292. irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
  293. handle_edge_irq);
  294. irq_clear_status_flags(irq, IRQ_NOREQUEST);
  295. }
  296. pxa_ext_wakeup_chip.irq_set_wake = fn;
  297. }
  298. static void __init __pxa3xx_init_irq(void)
  299. {
  300. /* enable CP6 access */
  301. u32 value;
  302. __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
  303. value |= (1 << 6);
  304. __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
  305. pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
  306. }
  307. void __init pxa3xx_init_irq(void)
  308. {
  309. __pxa3xx_init_irq();
  310. pxa_init_irq(56, pxa3xx_set_wake);
  311. }
  312. #ifdef CONFIG_OF
  313. static int __init __init
  314. pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
  315. {
  316. __pxa3xx_init_irq();
  317. pxa_dt_irq_init(pxa3xx_set_wake);
  318. set_handle_irq(ichp_handle_irq);
  319. return 0;
  320. }
  321. IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
  322. #endif /* CONFIG_OF */
  323. static struct map_desc pxa3xx_io_desc[] __initdata = {
  324. { /* Mem Ctl */
  325. .virtual = (unsigned long)SMEMC_VIRT,
  326. .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
  327. .length = SMEMC_SIZE,
  328. .type = MT_DEVICE
  329. }, {
  330. .virtual = (unsigned long)NAND_VIRT,
  331. .pfn = __phys_to_pfn(NAND_PHYS),
  332. .length = NAND_SIZE,
  333. .type = MT_DEVICE
  334. },
  335. };
  336. void __init pxa3xx_map_io(void)
  337. {
  338. pxa_map_io();
  339. iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
  340. pxa3xx_get_clk_frequency_khz(1);
  341. }
  342. /*
  343. * device registration specific to PXA3xx.
  344. */
  345. void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
  346. {
  347. pxa_register_device(&pxa3xx_device_i2c_power, info);
  348. }
  349. static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
  350. .irq_base = PXA_GPIO_TO_IRQ(0),
  351. };
  352. static struct platform_device *devices[] __initdata = {
  353. &pxa27x_device_udc,
  354. &pxa_device_pmu,
  355. &pxa_device_i2s,
  356. &pxa_device_asoc_ssp1,
  357. &pxa_device_asoc_ssp2,
  358. &pxa_device_asoc_ssp3,
  359. &pxa_device_asoc_ssp4,
  360. &pxa_device_asoc_platform,
  361. &pxa_device_rtc,
  362. &pxa3xx_device_ssp1,
  363. &pxa3xx_device_ssp2,
  364. &pxa3xx_device_ssp3,
  365. &pxa3xx_device_ssp4,
  366. &pxa27x_device_pwm0,
  367. &pxa27x_device_pwm1,
  368. };
  369. static const struct dma_slave_map pxa3xx_slave_map[] = {
  370. /* PXA25x, PXA27x and PXA3xx common entries */
  371. { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
  372. { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
  373. { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
  374. PDMA_FILTER_PARAM(LOWEST, 10) },
  375. { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
  376. { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
  377. { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
  378. { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
  379. { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
  380. { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
  381. { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
  382. { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
  383. { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
  384. { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
  385. { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
  386. { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
  387. /* PXA3xx specific map */
  388. { "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
  389. { "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
  390. { "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
  391. { "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
  392. { "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
  393. { "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
  394. { "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
  395. };
  396. static struct mmp_dma_platdata pxa3xx_dma_pdata = {
  397. .dma_channels = 32,
  398. .nb_requestors = 100,
  399. .slave_map = pxa3xx_slave_map,
  400. .slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map),
  401. };
  402. static int __init pxa3xx_init(void)
  403. {
  404. int ret = 0;
  405. if (cpu_is_pxa3xx()) {
  406. pxa_register_wdt(ARSR);
  407. /*
  408. * clear RDH bit every time after reset
  409. *
  410. * Note: the last 3 bits DxS are write-1-to-clear so carefully
  411. * preserve them here in case they will be referenced later
  412. */
  413. ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
  414. /*
  415. * Disable DFI bus arbitration, to prevent a system bus lock if
  416. * somebody disables the NAND clock (unused clock) while this
  417. * bit remains set.
  418. */
  419. NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
  420. pxa3xx_init_pm();
  421. enable_irq_wake(IRQ_WAKEUP0);
  422. if (cpu_is_pxa320())
  423. enable_irq_wake(IRQ_WAKEUP1);
  424. register_syscore_ops(&pxa_irq_syscore_ops);
  425. register_syscore_ops(&pxa3xx_mfp_syscore_ops);
  426. if (of_have_populated_dt())
  427. return 0;
  428. pxa2xx_set_dmac_info(&pxa3xx_dma_pdata);
  429. ret = platform_add_devices(devices, ARRAY_SIZE(devices));
  430. if (ret)
  431. return ret;
  432. if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
  433. platform_device_add_data(&pxa3xx_device_gpio,
  434. &pxa3xx_gpio_pdata,
  435. sizeof(pxa3xx_gpio_pdata));
  436. ret = platform_device_register(&pxa3xx_device_gpio);
  437. }
  438. }
  439. return ret;
  440. }
  441. postcore_initcall(pxa3xx_init);