lpd270.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * linux/arch/arm/mach-pxa/lpd270.c
  4. *
  5. * Support for the LogicPD PXA270 Card Engine.
  6. * Derived from the mainstone code, which carries these notices:
  7. *
  8. * Author: Nicolas Pitre
  9. * Created: Nov 05, 2002
  10. * Copyright: MontaVista Software Inc.
  11. */
  12. #include <linux/gpio.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/syscore_ops.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/sched.h>
  18. #include <linux/bitops.h>
  19. #include <linux/fb.h>
  20. #include <linux/ioport.h>
  21. #include <linux/mtd/mtd.h>
  22. #include <linux/mtd/partitions.h>
  23. #include <linux/pwm.h>
  24. #include <linux/pwm_backlight.h>
  25. #include <linux/smc91x.h>
  26. #include <asm/types.h>
  27. #include <asm/setup.h>
  28. #include <asm/memory.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/irq.h>
  31. #include <linux/sizes.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/mach/irq.h>
  35. #include <asm/mach/flash.h>
  36. #include "pxa27x.h"
  37. #include "lpd270.h"
  38. #include "addr-map.h"
  39. #include <linux/platform_data/asoc-pxa.h>
  40. #include <linux/platform_data/video-pxafb.h>
  41. #include <linux/platform_data/mmc-pxamci.h>
  42. #include <linux/platform_data/irda-pxaficp.h>
  43. #include <linux/platform_data/usb-ohci-pxa27x.h>
  44. #include "smemc.h"
  45. #include "generic.h"
  46. #include "devices.h"
  47. static unsigned long lpd270_pin_config[] __initdata = {
  48. /* Chip Selects */
  49. GPIO15_nCS_1, /* Mainboard Flash */
  50. GPIO78_nCS_2, /* CPLD + Ethernet */
  51. /* LCD - 16bpp Active TFT */
  52. GPIO58_LCD_LDD_0,
  53. GPIO59_LCD_LDD_1,
  54. GPIO60_LCD_LDD_2,
  55. GPIO61_LCD_LDD_3,
  56. GPIO62_LCD_LDD_4,
  57. GPIO63_LCD_LDD_5,
  58. GPIO64_LCD_LDD_6,
  59. GPIO65_LCD_LDD_7,
  60. GPIO66_LCD_LDD_8,
  61. GPIO67_LCD_LDD_9,
  62. GPIO68_LCD_LDD_10,
  63. GPIO69_LCD_LDD_11,
  64. GPIO70_LCD_LDD_12,
  65. GPIO71_LCD_LDD_13,
  66. GPIO72_LCD_LDD_14,
  67. GPIO73_LCD_LDD_15,
  68. GPIO74_LCD_FCLK,
  69. GPIO75_LCD_LCLK,
  70. GPIO76_LCD_PCLK,
  71. GPIO77_LCD_BIAS,
  72. GPIO16_PWM0_OUT, /* Backlight */
  73. /* USB Host */
  74. GPIO88_USBH1_PWR,
  75. GPIO89_USBH1_PEN,
  76. /* AC97 */
  77. GPIO28_AC97_BITCLK,
  78. GPIO29_AC97_SDATA_IN_0,
  79. GPIO30_AC97_SDATA_OUT,
  80. GPIO31_AC97_SYNC,
  81. GPIO45_AC97_SYSCLK,
  82. GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
  83. };
  84. static unsigned int lpd270_irq_enabled;
  85. static void lpd270_mask_irq(struct irq_data *d)
  86. {
  87. int lpd270_irq = d->irq - LPD270_IRQ(0);
  88. __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
  89. lpd270_irq_enabled &= ~(1 << lpd270_irq);
  90. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  91. }
  92. static void lpd270_unmask_irq(struct irq_data *d)
  93. {
  94. int lpd270_irq = d->irq - LPD270_IRQ(0);
  95. lpd270_irq_enabled |= 1 << lpd270_irq;
  96. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  97. }
  98. static struct irq_chip lpd270_irq_chip = {
  99. .name = "CPLD",
  100. .irq_ack = lpd270_mask_irq,
  101. .irq_mask = lpd270_mask_irq,
  102. .irq_unmask = lpd270_unmask_irq,
  103. };
  104. static void lpd270_irq_handler(struct irq_desc *desc)
  105. {
  106. unsigned int irq;
  107. unsigned long pending;
  108. pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
  109. do {
  110. /* clear useless edge notification */
  111. desc->irq_data.chip->irq_ack(&desc->irq_data);
  112. if (likely(pending)) {
  113. irq = LPD270_IRQ(0) + __ffs(pending);
  114. generic_handle_irq(irq);
  115. pending = __raw_readw(LPD270_INT_STATUS) &
  116. lpd270_irq_enabled;
  117. }
  118. } while (pending);
  119. }
  120. static void __init lpd270_init_irq(void)
  121. {
  122. int irq;
  123. pxa27x_init_irq();
  124. __raw_writew(0, LPD270_INT_MASK);
  125. __raw_writew(0, LPD270_INT_STATUS);
  126. /* setup extra LogicPD PXA270 irqs */
  127. for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
  128. irq_set_chip_and_handler(irq, &lpd270_irq_chip,
  129. handle_level_irq);
  130. irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
  131. }
  132. irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
  133. irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
  134. }
  135. #ifdef CONFIG_PM
  136. static void lpd270_irq_resume(void)
  137. {
  138. __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
  139. }
  140. static struct syscore_ops lpd270_irq_syscore_ops = {
  141. .resume = lpd270_irq_resume,
  142. };
  143. static int __init lpd270_irq_device_init(void)
  144. {
  145. if (machine_is_logicpd_pxa270()) {
  146. register_syscore_ops(&lpd270_irq_syscore_ops);
  147. return 0;
  148. }
  149. return -ENODEV;
  150. }
  151. device_initcall(lpd270_irq_device_init);
  152. #endif
  153. static struct resource smc91x_resources[] = {
  154. [0] = {
  155. .start = LPD270_ETH_PHYS,
  156. .end = (LPD270_ETH_PHYS + 0xfffff),
  157. .flags = IORESOURCE_MEM,
  158. },
  159. [1] = {
  160. .start = LPD270_ETHERNET_IRQ,
  161. .end = LPD270_ETHERNET_IRQ,
  162. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
  163. },
  164. };
  165. struct smc91x_platdata smc91x_platdata = {
  166. .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
  167. };
  168. static struct platform_device smc91x_device = {
  169. .name = "smc91x",
  170. .id = 0,
  171. .num_resources = ARRAY_SIZE(smc91x_resources),
  172. .resource = smc91x_resources,
  173. .dev.platform_data = &smc91x_platdata,
  174. };
  175. static struct resource lpd270_flash_resources[] = {
  176. [0] = {
  177. .start = PXA_CS0_PHYS,
  178. .end = PXA_CS0_PHYS + SZ_64M - 1,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. [1] = {
  182. .start = PXA_CS1_PHYS,
  183. .end = PXA_CS1_PHYS + SZ_64M - 1,
  184. .flags = IORESOURCE_MEM,
  185. },
  186. };
  187. static struct mtd_partition lpd270_flash0_partitions[] = {
  188. {
  189. .name = "Bootloader",
  190. .size = 0x00040000,
  191. .offset = 0,
  192. .mask_flags = MTD_WRITEABLE /* force read-only */
  193. }, {
  194. .name = "Kernel",
  195. .size = 0x00400000,
  196. .offset = 0x00040000,
  197. }, {
  198. .name = "Filesystem",
  199. .size = MTDPART_SIZ_FULL,
  200. .offset = 0x00440000
  201. },
  202. };
  203. static struct flash_platform_data lpd270_flash_data[2] = {
  204. {
  205. .name = "processor-flash",
  206. .map_name = "cfi_probe",
  207. .parts = lpd270_flash0_partitions,
  208. .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
  209. }, {
  210. .name = "mainboard-flash",
  211. .map_name = "cfi_probe",
  212. .parts = NULL,
  213. .nr_parts = 0,
  214. }
  215. };
  216. static struct platform_device lpd270_flash_device[2] = {
  217. {
  218. .name = "pxa2xx-flash",
  219. .id = 0,
  220. .dev = {
  221. .platform_data = &lpd270_flash_data[0],
  222. },
  223. .resource = &lpd270_flash_resources[0],
  224. .num_resources = 1,
  225. }, {
  226. .name = "pxa2xx-flash",
  227. .id = 1,
  228. .dev = {
  229. .platform_data = &lpd270_flash_data[1],
  230. },
  231. .resource = &lpd270_flash_resources[1],
  232. .num_resources = 1,
  233. },
  234. };
  235. static struct pwm_lookup lpd270_pwm_lookup[] = {
  236. PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
  237. PWM_POLARITY_NORMAL),
  238. };
  239. static struct platform_pwm_backlight_data lpd270_backlight_data = {
  240. .max_brightness = 1,
  241. .dft_brightness = 1,
  242. };
  243. static struct platform_device lpd270_backlight_device = {
  244. .name = "pwm-backlight",
  245. .dev = {
  246. .parent = &pxa27x_device_pwm0.dev,
  247. .platform_data = &lpd270_backlight_data,
  248. },
  249. };
  250. /* 5.7" TFT QVGA (LoLo display number 1) */
  251. static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
  252. .pixclock = 150000,
  253. .xres = 320,
  254. .yres = 240,
  255. .bpp = 16,
  256. .hsync_len = 0x14,
  257. .left_margin = 0x28,
  258. .right_margin = 0x0a,
  259. .vsync_len = 0x02,
  260. .upper_margin = 0x08,
  261. .lower_margin = 0x14,
  262. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  263. };
  264. static struct pxafb_mach_info sharp_lq057q3dc02 = {
  265. .modes = &sharp_lq057q3dc02_mode,
  266. .num_modes = 1,
  267. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  268. LCD_ALTERNATE_MAPPING,
  269. };
  270. /* 12.1" TFT SVGA (LoLo display number 2) */
  271. static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
  272. .pixclock = 50000,
  273. .xres = 800,
  274. .yres = 600,
  275. .bpp = 16,
  276. .hsync_len = 0x05,
  277. .left_margin = 0x52,
  278. .right_margin = 0x05,
  279. .vsync_len = 0x04,
  280. .upper_margin = 0x14,
  281. .lower_margin = 0x0a,
  282. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  283. };
  284. static struct pxafb_mach_info sharp_lq121s1dg31 = {
  285. .modes = &sharp_lq121s1dg31_mode,
  286. .num_modes = 1,
  287. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  288. LCD_ALTERNATE_MAPPING,
  289. };
  290. /* 3.6" TFT QVGA (LoLo display number 3) */
  291. static struct pxafb_mode_info sharp_lq036q1da01_mode = {
  292. .pixclock = 150000,
  293. .xres = 320,
  294. .yres = 240,
  295. .bpp = 16,
  296. .hsync_len = 0x0e,
  297. .left_margin = 0x04,
  298. .right_margin = 0x0a,
  299. .vsync_len = 0x03,
  300. .upper_margin = 0x03,
  301. .lower_margin = 0x03,
  302. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  303. };
  304. static struct pxafb_mach_info sharp_lq036q1da01 = {
  305. .modes = &sharp_lq036q1da01_mode,
  306. .num_modes = 1,
  307. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  308. LCD_ALTERNATE_MAPPING,
  309. };
  310. /* 6.4" TFT VGA (LoLo display number 5) */
  311. static struct pxafb_mode_info sharp_lq64d343_mode = {
  312. .pixclock = 25000,
  313. .xres = 640,
  314. .yres = 480,
  315. .bpp = 16,
  316. .hsync_len = 0x31,
  317. .left_margin = 0x89,
  318. .right_margin = 0x19,
  319. .vsync_len = 0x12,
  320. .upper_margin = 0x22,
  321. .lower_margin = 0x00,
  322. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  323. };
  324. static struct pxafb_mach_info sharp_lq64d343 = {
  325. .modes = &sharp_lq64d343_mode,
  326. .num_modes = 1,
  327. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  328. LCD_ALTERNATE_MAPPING,
  329. };
  330. /* 10.4" TFT VGA (LoLo display number 7) */
  331. static struct pxafb_mode_info sharp_lq10d368_mode = {
  332. .pixclock = 25000,
  333. .xres = 640,
  334. .yres = 480,
  335. .bpp = 16,
  336. .hsync_len = 0x31,
  337. .left_margin = 0x89,
  338. .right_margin = 0x19,
  339. .vsync_len = 0x12,
  340. .upper_margin = 0x22,
  341. .lower_margin = 0x00,
  342. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  343. };
  344. static struct pxafb_mach_info sharp_lq10d368 = {
  345. .modes = &sharp_lq10d368_mode,
  346. .num_modes = 1,
  347. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  348. LCD_ALTERNATE_MAPPING,
  349. };
  350. /* 3.5" TFT QVGA (LoLo display number 8) */
  351. static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
  352. .pixclock = 150000,
  353. .xres = 240,
  354. .yres = 320,
  355. .bpp = 16,
  356. .hsync_len = 0x0e,
  357. .left_margin = 0x0a,
  358. .right_margin = 0x0a,
  359. .vsync_len = 0x03,
  360. .upper_margin = 0x05,
  361. .lower_margin = 0x14,
  362. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  363. };
  364. static struct pxafb_mach_info sharp_lq035q7db02_20 = {
  365. .modes = &sharp_lq035q7db02_20_mode,
  366. .num_modes = 1,
  367. .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
  368. LCD_ALTERNATE_MAPPING,
  369. };
  370. static struct pxafb_mach_info *lpd270_lcd_to_use;
  371. static int __init lpd270_set_lcd(char *str)
  372. {
  373. if (!strncasecmp(str, "lq057q3dc02", 11)) {
  374. lpd270_lcd_to_use = &sharp_lq057q3dc02;
  375. } else if (!strncasecmp(str, "lq121s1dg31", 11)) {
  376. lpd270_lcd_to_use = &sharp_lq121s1dg31;
  377. } else if (!strncasecmp(str, "lq036q1da01", 11)) {
  378. lpd270_lcd_to_use = &sharp_lq036q1da01;
  379. } else if (!strncasecmp(str, "lq64d343", 8)) {
  380. lpd270_lcd_to_use = &sharp_lq64d343;
  381. } else if (!strncasecmp(str, "lq10d368", 8)) {
  382. lpd270_lcd_to_use = &sharp_lq10d368;
  383. } else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
  384. lpd270_lcd_to_use = &sharp_lq035q7db02_20;
  385. } else {
  386. printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
  387. }
  388. return 1;
  389. }
  390. __setup("lcd=", lpd270_set_lcd);
  391. static struct platform_device *platform_devices[] __initdata = {
  392. &smc91x_device,
  393. &lpd270_backlight_device,
  394. &lpd270_flash_device[0],
  395. &lpd270_flash_device[1],
  396. };
  397. static struct pxaohci_platform_data lpd270_ohci_platform_data = {
  398. .port_mode = PMM_PERPORT_MODE,
  399. .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
  400. };
  401. static void __init lpd270_init(void)
  402. {
  403. pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
  404. pxa_set_ffuart_info(NULL);
  405. pxa_set_btuart_info(NULL);
  406. pxa_set_stuart_info(NULL);
  407. lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
  408. lpd270_flash_data[1].width = 4;
  409. /*
  410. * System bus arbiter setting:
  411. * - Core_Park
  412. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  413. */
  414. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  415. pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
  416. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  417. pxa_set_ac97_info(NULL);
  418. if (lpd270_lcd_to_use != NULL)
  419. pxa_set_fb_info(NULL, lpd270_lcd_to_use);
  420. pxa_set_ohci_info(&lpd270_ohci_platform_data);
  421. }
  422. static struct map_desc lpd270_io_desc[] __initdata = {
  423. {
  424. .virtual = (unsigned long)LPD270_CPLD_VIRT,
  425. .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
  426. .length = LPD270_CPLD_SIZE,
  427. .type = MT_DEVICE,
  428. },
  429. };
  430. static void __init lpd270_map_io(void)
  431. {
  432. pxa27x_map_io();
  433. iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
  434. /* for use I SRAM as framebuffer. */
  435. PSLR |= 0x00000F04;
  436. PCFR = 0x00000066;
  437. }
  438. MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
  439. /* Maintainer: Peter Barada */
  440. .atag_offset = 0x100,
  441. .map_io = lpd270_map_io,
  442. .nr_irqs = LPD270_NR_IRQS,
  443. .init_irq = lpd270_init_irq,
  444. .handle_irq = pxa27x_handle_irq,
  445. .init_time = pxa_timer_init,
  446. .init_machine = lpd270_init,
  447. .restart = pxa_restart,
  448. MACHINE_END