devices.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/module.h>
  3. #include <linux/kernel.h>
  4. #include <linux/init.h>
  5. #include <linux/platform_device.h>
  6. #include <linux/clkdev.h>
  7. #include <linux/clk-provider.h>
  8. #include <linux/dma-mapping.h>
  9. #include <linux/dmaengine.h>
  10. #include <linux/spi/pxa2xx_spi.h>
  11. #include <linux/platform_data/i2c-pxa.h>
  12. #include <linux/soc/pxa/cpu.h>
  13. #include "udc.h"
  14. #include <linux/platform_data/usb-pxa3xx-ulpi.h>
  15. #include <linux/platform_data/video-pxafb.h>
  16. #include <linux/platform_data/mmc-pxamci.h>
  17. #include <linux/platform_data/irda-pxaficp.h>
  18. #include "irqs.h"
  19. #include <linux/platform_data/usb-ohci-pxa27x.h>
  20. #include <linux/platform_data/keypad-pxa27x.h>
  21. #include <linux/platform_data/media/camera-pxa.h>
  22. #include <linux/platform_data/asoc-pxa.h>
  23. #include <linux/platform_data/mmp_dma.h>
  24. #include <linux/platform_data/mtd-nand-pxa3xx.h>
  25. #include "regs-ost.h"
  26. #include "reset.h"
  27. #include "devices.h"
  28. #include "generic.h"
  29. void __init pxa_register_device(struct platform_device *dev, void *data)
  30. {
  31. int ret;
  32. dev->dev.platform_data = data;
  33. ret = platform_device_register(dev);
  34. if (ret)
  35. dev_err(&dev->dev, "unable to register device: %d\n", ret);
  36. }
  37. static struct resource pxa_resource_pmu = {
  38. .start = IRQ_PMU,
  39. .end = IRQ_PMU,
  40. .flags = IORESOURCE_IRQ,
  41. };
  42. struct platform_device pxa_device_pmu = {
  43. .name = "xscale-pmu",
  44. .id = -1,
  45. .resource = &pxa_resource_pmu,
  46. .num_resources = 1,
  47. };
  48. static struct resource pxamci_resources[] = {
  49. [0] = {
  50. .start = 0x41100000,
  51. .end = 0x41100fff,
  52. .flags = IORESOURCE_MEM,
  53. },
  54. [1] = {
  55. .start = IRQ_MMC,
  56. .end = IRQ_MMC,
  57. .flags = IORESOURCE_IRQ,
  58. },
  59. };
  60. static u64 pxamci_dmamask = 0xffffffffUL;
  61. struct platform_device pxa_device_mci = {
  62. .name = "pxa2xx-mci",
  63. .id = 0,
  64. .dev = {
  65. .dma_mask = &pxamci_dmamask,
  66. .coherent_dma_mask = 0xffffffff,
  67. },
  68. .num_resources = ARRAY_SIZE(pxamci_resources),
  69. .resource = pxamci_resources,
  70. };
  71. void __init pxa_set_mci_info(struct pxamci_platform_data *info)
  72. {
  73. pxa_register_device(&pxa_device_mci, info);
  74. }
  75. static struct pxa2xx_udc_mach_info pxa_udc_info = {
  76. .gpio_pullup = -1,
  77. };
  78. void __init pxa_set_udc_info(struct pxa2xx_udc_mach_info *info)
  79. {
  80. memcpy(&pxa_udc_info, info, sizeof *info);
  81. }
  82. static struct resource pxa2xx_udc_resources[] = {
  83. [0] = {
  84. .start = 0x40600000,
  85. .end = 0x4060ffff,
  86. .flags = IORESOURCE_MEM,
  87. },
  88. [1] = {
  89. .start = IRQ_USB,
  90. .end = IRQ_USB,
  91. .flags = IORESOURCE_IRQ,
  92. },
  93. };
  94. static u64 udc_dma_mask = ~(u32)0;
  95. struct platform_device pxa25x_device_udc = {
  96. .name = "pxa25x-udc",
  97. .id = -1,
  98. .resource = pxa2xx_udc_resources,
  99. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  100. .dev = {
  101. .platform_data = &pxa_udc_info,
  102. .dma_mask = &udc_dma_mask,
  103. }
  104. };
  105. struct platform_device pxa27x_device_udc = {
  106. .name = "pxa27x-udc",
  107. .id = -1,
  108. .resource = pxa2xx_udc_resources,
  109. .num_resources = ARRAY_SIZE(pxa2xx_udc_resources),
  110. .dev = {
  111. .platform_data = &pxa_udc_info,
  112. .dma_mask = &udc_dma_mask,
  113. }
  114. };
  115. #ifdef CONFIG_PXA3xx
  116. static struct resource pxa3xx_u2d_resources[] = {
  117. [0] = {
  118. .start = 0x54100000,
  119. .end = 0x54100fff,
  120. .flags = IORESOURCE_MEM,
  121. },
  122. [1] = {
  123. .start = IRQ_USB2,
  124. .end = IRQ_USB2,
  125. .flags = IORESOURCE_IRQ,
  126. },
  127. };
  128. struct platform_device pxa3xx_device_u2d = {
  129. .name = "pxa3xx-u2d",
  130. .id = -1,
  131. .resource = pxa3xx_u2d_resources,
  132. .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
  133. };
  134. void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
  135. {
  136. pxa_register_device(&pxa3xx_device_u2d, info);
  137. }
  138. #endif /* CONFIG_PXA3xx */
  139. static struct resource pxafb_resources[] = {
  140. [0] = {
  141. .start = 0x44000000,
  142. .end = 0x4400ffff,
  143. .flags = IORESOURCE_MEM,
  144. },
  145. [1] = {
  146. .start = IRQ_LCD,
  147. .end = IRQ_LCD,
  148. .flags = IORESOURCE_IRQ,
  149. },
  150. };
  151. static u64 fb_dma_mask = ~(u64)0;
  152. struct platform_device pxa_device_fb = {
  153. .name = "pxa2xx-fb",
  154. .id = -1,
  155. .dev = {
  156. .dma_mask = &fb_dma_mask,
  157. .coherent_dma_mask = 0xffffffff,
  158. },
  159. .num_resources = ARRAY_SIZE(pxafb_resources),
  160. .resource = pxafb_resources,
  161. };
  162. void __init pxa_set_fb_info(struct device *parent, struct pxafb_mach_info *info)
  163. {
  164. pxa_device_fb.dev.parent = parent;
  165. pxa_register_device(&pxa_device_fb, info);
  166. }
  167. static struct resource pxa_resource_ffuart[] = {
  168. {
  169. .start = 0x40100000,
  170. .end = 0x40100023,
  171. .flags = IORESOURCE_MEM,
  172. }, {
  173. .start = IRQ_FFUART,
  174. .end = IRQ_FFUART,
  175. .flags = IORESOURCE_IRQ,
  176. }
  177. };
  178. struct platform_device pxa_device_ffuart = {
  179. .name = "pxa2xx-uart",
  180. .id = 0,
  181. .resource = pxa_resource_ffuart,
  182. .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
  183. };
  184. void __init pxa_set_ffuart_info(void *info)
  185. {
  186. pxa_register_device(&pxa_device_ffuart, info);
  187. }
  188. static struct resource pxa_resource_btuart[] = {
  189. {
  190. .start = 0x40200000,
  191. .end = 0x40200023,
  192. .flags = IORESOURCE_MEM,
  193. }, {
  194. .start = IRQ_BTUART,
  195. .end = IRQ_BTUART,
  196. .flags = IORESOURCE_IRQ,
  197. }
  198. };
  199. struct platform_device pxa_device_btuart = {
  200. .name = "pxa2xx-uart",
  201. .id = 1,
  202. .resource = pxa_resource_btuart,
  203. .num_resources = ARRAY_SIZE(pxa_resource_btuart),
  204. };
  205. void __init pxa_set_btuart_info(void *info)
  206. {
  207. pxa_register_device(&pxa_device_btuart, info);
  208. }
  209. static struct resource pxa_resource_stuart[] = {
  210. {
  211. .start = 0x40700000,
  212. .end = 0x40700023,
  213. .flags = IORESOURCE_MEM,
  214. }, {
  215. .start = IRQ_STUART,
  216. .end = IRQ_STUART,
  217. .flags = IORESOURCE_IRQ,
  218. }
  219. };
  220. struct platform_device pxa_device_stuart = {
  221. .name = "pxa2xx-uart",
  222. .id = 2,
  223. .resource = pxa_resource_stuart,
  224. .num_resources = ARRAY_SIZE(pxa_resource_stuart),
  225. };
  226. void __init pxa_set_stuart_info(void *info)
  227. {
  228. pxa_register_device(&pxa_device_stuart, info);
  229. }
  230. static struct resource pxa_resource_hwuart[] = {
  231. {
  232. .start = 0x41600000,
  233. .end = 0x4160002F,
  234. .flags = IORESOURCE_MEM,
  235. }, {
  236. .start = IRQ_HWUART,
  237. .end = IRQ_HWUART,
  238. .flags = IORESOURCE_IRQ,
  239. }
  240. };
  241. struct platform_device pxa_device_hwuart = {
  242. .name = "pxa2xx-uart",
  243. .id = 3,
  244. .resource = pxa_resource_hwuart,
  245. .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
  246. };
  247. void __init pxa_set_hwuart_info(void *info)
  248. {
  249. if (cpu_is_pxa255())
  250. pxa_register_device(&pxa_device_hwuart, info);
  251. else
  252. pr_info("UART: Ignoring attempt to register HWUART on non-PXA255 hardware");
  253. }
  254. static struct resource pxai2c_resources[] = {
  255. {
  256. .start = 0x40301680,
  257. .end = 0x403016a3,
  258. .flags = IORESOURCE_MEM,
  259. }, {
  260. .start = IRQ_I2C,
  261. .end = IRQ_I2C,
  262. .flags = IORESOURCE_IRQ,
  263. },
  264. };
  265. struct platform_device pxa_device_i2c = {
  266. .name = "pxa2xx-i2c",
  267. .id = 0,
  268. .resource = pxai2c_resources,
  269. .num_resources = ARRAY_SIZE(pxai2c_resources),
  270. };
  271. void __init pxa_set_i2c_info(struct i2c_pxa_platform_data *info)
  272. {
  273. pxa_register_device(&pxa_device_i2c, info);
  274. }
  275. #ifdef CONFIG_PXA27x
  276. static struct resource pxa27x_resources_i2c_power[] = {
  277. {
  278. .start = 0x40f00180,
  279. .end = 0x40f001a3,
  280. .flags = IORESOURCE_MEM,
  281. }, {
  282. .start = IRQ_PWRI2C,
  283. .end = IRQ_PWRI2C,
  284. .flags = IORESOURCE_IRQ,
  285. },
  286. };
  287. struct platform_device pxa27x_device_i2c_power = {
  288. .name = "pxa2xx-i2c",
  289. .id = 1,
  290. .resource = pxa27x_resources_i2c_power,
  291. .num_resources = ARRAY_SIZE(pxa27x_resources_i2c_power),
  292. };
  293. #endif
  294. static struct resource pxai2s_resources[] = {
  295. {
  296. .start = 0x40400000,
  297. .end = 0x40400083,
  298. .flags = IORESOURCE_MEM,
  299. }, {
  300. .start = IRQ_I2S,
  301. .end = IRQ_I2S,
  302. .flags = IORESOURCE_IRQ,
  303. },
  304. };
  305. struct platform_device pxa_device_i2s = {
  306. .name = "pxa2xx-i2s",
  307. .id = -1,
  308. .resource = pxai2s_resources,
  309. .num_resources = ARRAY_SIZE(pxai2s_resources),
  310. };
  311. struct platform_device pxa_device_asoc_ssp1 = {
  312. .name = "pxa-ssp-dai",
  313. .id = 0,
  314. };
  315. struct platform_device pxa_device_asoc_ssp2= {
  316. .name = "pxa-ssp-dai",
  317. .id = 1,
  318. };
  319. struct platform_device pxa_device_asoc_ssp3 = {
  320. .name = "pxa-ssp-dai",
  321. .id = 2,
  322. };
  323. struct platform_device pxa_device_asoc_ssp4 = {
  324. .name = "pxa-ssp-dai",
  325. .id = 3,
  326. };
  327. struct platform_device pxa_device_asoc_platform = {
  328. .name = "pxa-pcm-audio",
  329. .id = -1,
  330. };
  331. static u64 pxaficp_dmamask = ~(u32)0;
  332. static struct resource pxa_ir_resources[] = {
  333. [0] = {
  334. .start = IRQ_STUART,
  335. .end = IRQ_STUART,
  336. .flags = IORESOURCE_IRQ,
  337. },
  338. [1] = {
  339. .start = IRQ_ICP,
  340. .end = IRQ_ICP,
  341. .flags = IORESOURCE_IRQ,
  342. },
  343. [3] = {
  344. .start = 0x40800000,
  345. .end = 0x4080001b,
  346. .flags = IORESOURCE_MEM,
  347. },
  348. [4] = {
  349. .start = 0x40700000,
  350. .end = 0x40700023,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. };
  354. struct platform_device pxa_device_ficp = {
  355. .name = "pxa2xx-ir",
  356. .id = -1,
  357. .num_resources = ARRAY_SIZE(pxa_ir_resources),
  358. .resource = pxa_ir_resources,
  359. .dev = {
  360. .dma_mask = &pxaficp_dmamask,
  361. .coherent_dma_mask = 0xffffffff,
  362. },
  363. };
  364. void __init pxa_set_ficp_info(struct pxaficp_platform_data *info)
  365. {
  366. pxa_register_device(&pxa_device_ficp, info);
  367. }
  368. static struct resource pxa_rtc_resources[] = {
  369. [0] = {
  370. .start = 0x40900000,
  371. .end = 0x40900000 + 0x3b,
  372. .flags = IORESOURCE_MEM,
  373. },
  374. [1] = {
  375. .start = IRQ_RTC1Hz,
  376. .end = IRQ_RTC1Hz,
  377. .name = "rtc 1Hz",
  378. .flags = IORESOURCE_IRQ,
  379. },
  380. [2] = {
  381. .start = IRQ_RTCAlrm,
  382. .end = IRQ_RTCAlrm,
  383. .name = "rtc alarm",
  384. .flags = IORESOURCE_IRQ,
  385. },
  386. };
  387. struct platform_device pxa_device_rtc = {
  388. .name = "pxa-rtc",
  389. .id = -1,
  390. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  391. .resource = pxa_rtc_resources,
  392. };
  393. struct platform_device sa1100_device_rtc = {
  394. .name = "sa1100-rtc",
  395. .id = -1,
  396. .num_resources = ARRAY_SIZE(pxa_rtc_resources),
  397. .resource = pxa_rtc_resources,
  398. };
  399. static struct resource pxa_ac97_resources[] = {
  400. [0] = {
  401. .start = 0x40500000,
  402. .end = 0x40500000 + 0xfff,
  403. .flags = IORESOURCE_MEM,
  404. },
  405. [1] = {
  406. .start = IRQ_AC97,
  407. .end = IRQ_AC97,
  408. .flags = IORESOURCE_IRQ,
  409. },
  410. };
  411. static u64 pxa_ac97_dmamask = 0xffffffffUL;
  412. struct platform_device pxa_device_ac97 = {
  413. .name = "pxa2xx-ac97",
  414. .id = -1,
  415. .dev = {
  416. .dma_mask = &pxa_ac97_dmamask,
  417. .coherent_dma_mask = 0xffffffff,
  418. },
  419. .num_resources = ARRAY_SIZE(pxa_ac97_resources),
  420. .resource = pxa_ac97_resources,
  421. };
  422. void __init pxa_set_ac97_info(pxa2xx_audio_ops_t *ops)
  423. {
  424. int ret;
  425. ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:0", "AC97CLK",
  426. &pxa_device_ac97.dev);
  427. if (ret)
  428. pr_err("PXA AC97 clock1 alias error: %d\n", ret);
  429. ret = clk_add_alias("ac97_clk", "pxa2xx-ac97:1", "AC97CLK",
  430. &pxa_device_ac97.dev);
  431. if (ret)
  432. pr_err("PXA AC97 clock2 alias error: %d\n", ret);
  433. pxa_register_device(&pxa_device_ac97, ops);
  434. }
  435. #ifdef CONFIG_PXA25x
  436. static struct resource pxa25x_resource_pwm0[] = {
  437. [0] = {
  438. .start = 0x40b00000,
  439. .end = 0x40b0000f,
  440. .flags = IORESOURCE_MEM,
  441. },
  442. };
  443. struct platform_device pxa25x_device_pwm0 = {
  444. .name = "pxa25x-pwm",
  445. .id = 0,
  446. .resource = pxa25x_resource_pwm0,
  447. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm0),
  448. };
  449. static struct resource pxa25x_resource_pwm1[] = {
  450. [0] = {
  451. .start = 0x40c00000,
  452. .end = 0x40c0000f,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. };
  456. struct platform_device pxa25x_device_pwm1 = {
  457. .name = "pxa25x-pwm",
  458. .id = 1,
  459. .resource = pxa25x_resource_pwm1,
  460. .num_resources = ARRAY_SIZE(pxa25x_resource_pwm1),
  461. };
  462. static u64 pxa25x_ssp_dma_mask = DMA_BIT_MASK(32);
  463. static struct resource pxa25x_resource_ssp[] = {
  464. [0] = {
  465. .start = 0x41000000,
  466. .end = 0x4100001f,
  467. .flags = IORESOURCE_MEM,
  468. },
  469. [1] = {
  470. .start = IRQ_SSP,
  471. .end = IRQ_SSP,
  472. .flags = IORESOURCE_IRQ,
  473. },
  474. };
  475. struct platform_device pxa25x_device_ssp = {
  476. .name = "pxa25x-ssp",
  477. .id = 0,
  478. .dev = {
  479. .dma_mask = &pxa25x_ssp_dma_mask,
  480. .coherent_dma_mask = DMA_BIT_MASK(32),
  481. },
  482. .resource = pxa25x_resource_ssp,
  483. .num_resources = ARRAY_SIZE(pxa25x_resource_ssp),
  484. };
  485. static u64 pxa25x_nssp_dma_mask = DMA_BIT_MASK(32);
  486. static struct resource pxa25x_resource_nssp[] = {
  487. [0] = {
  488. .start = 0x41400000,
  489. .end = 0x4140002f,
  490. .flags = IORESOURCE_MEM,
  491. },
  492. [1] = {
  493. .start = IRQ_NSSP,
  494. .end = IRQ_NSSP,
  495. .flags = IORESOURCE_IRQ,
  496. },
  497. };
  498. struct platform_device pxa25x_device_nssp = {
  499. .name = "pxa25x-nssp",
  500. .id = 1,
  501. .dev = {
  502. .dma_mask = &pxa25x_nssp_dma_mask,
  503. .coherent_dma_mask = DMA_BIT_MASK(32),
  504. },
  505. .resource = pxa25x_resource_nssp,
  506. .num_resources = ARRAY_SIZE(pxa25x_resource_nssp),
  507. };
  508. static u64 pxa25x_assp_dma_mask = DMA_BIT_MASK(32);
  509. static struct resource pxa25x_resource_assp[] = {
  510. [0] = {
  511. .start = 0x41500000,
  512. .end = 0x4150002f,
  513. .flags = IORESOURCE_MEM,
  514. },
  515. [1] = {
  516. .start = IRQ_ASSP,
  517. .end = IRQ_ASSP,
  518. .flags = IORESOURCE_IRQ,
  519. },
  520. };
  521. struct platform_device pxa25x_device_assp = {
  522. /* ASSP is basically equivalent to NSSP */
  523. .name = "pxa25x-nssp",
  524. .id = 2,
  525. .dev = {
  526. .dma_mask = &pxa25x_assp_dma_mask,
  527. .coherent_dma_mask = DMA_BIT_MASK(32),
  528. },
  529. .resource = pxa25x_resource_assp,
  530. .num_resources = ARRAY_SIZE(pxa25x_resource_assp),
  531. };
  532. #endif /* CONFIG_PXA25x */
  533. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  534. static struct resource pxa27x_resource_camera[] = {
  535. [0] = {
  536. .start = 0x50000000,
  537. .end = 0x50000fff,
  538. .flags = IORESOURCE_MEM,
  539. },
  540. [1] = {
  541. .start = IRQ_CAMERA,
  542. .end = IRQ_CAMERA,
  543. .flags = IORESOURCE_IRQ,
  544. },
  545. };
  546. static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
  547. static struct platform_device pxa27x_device_camera = {
  548. .name = "pxa27x-camera",
  549. .id = 0, /* This is used to put cameras on this interface */
  550. .dev = {
  551. .dma_mask = &pxa27x_dma_mask_camera,
  552. .coherent_dma_mask = 0xffffffff,
  553. },
  554. .num_resources = ARRAY_SIZE(pxa27x_resource_camera),
  555. .resource = pxa27x_resource_camera,
  556. };
  557. void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
  558. {
  559. struct clk *mclk;
  560. /* Register a fixed-rate clock for camera sensors. */
  561. mclk = clk_register_fixed_rate(NULL, "pxa_camera_clk", NULL, 0,
  562. info->mclk_10khz * 10000);
  563. if (!IS_ERR(mclk))
  564. clkdev_create(mclk, "mclk", NULL);
  565. pxa_register_device(&pxa27x_device_camera, info);
  566. }
  567. static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
  568. static struct resource pxa27x_resource_ohci[] = {
  569. [0] = {
  570. .start = 0x4C000000,
  571. .end = 0x4C00ff6f,
  572. .flags = IORESOURCE_MEM,
  573. },
  574. [1] = {
  575. .start = IRQ_USBH1,
  576. .end = IRQ_USBH1,
  577. .flags = IORESOURCE_IRQ,
  578. },
  579. };
  580. struct platform_device pxa27x_device_ohci = {
  581. .name = "pxa27x-ohci",
  582. .id = -1,
  583. .dev = {
  584. .dma_mask = &pxa27x_ohci_dma_mask,
  585. .coherent_dma_mask = DMA_BIT_MASK(32),
  586. },
  587. .num_resources = ARRAY_SIZE(pxa27x_resource_ohci),
  588. .resource = pxa27x_resource_ohci,
  589. };
  590. void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
  591. {
  592. pxa_register_device(&pxa27x_device_ohci, info);
  593. }
  594. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  595. #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
  596. static struct resource pxa27x_resource_keypad[] = {
  597. [0] = {
  598. .start = 0x41500000,
  599. .end = 0x4150004c,
  600. .flags = IORESOURCE_MEM,
  601. },
  602. [1] = {
  603. .start = IRQ_KEYPAD,
  604. .end = IRQ_KEYPAD,
  605. .flags = IORESOURCE_IRQ,
  606. },
  607. };
  608. struct platform_device pxa27x_device_keypad = {
  609. .name = "pxa27x-keypad",
  610. .id = -1,
  611. .resource = pxa27x_resource_keypad,
  612. .num_resources = ARRAY_SIZE(pxa27x_resource_keypad),
  613. };
  614. void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
  615. {
  616. pxa_register_device(&pxa27x_device_keypad, info);
  617. }
  618. static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
  619. static struct resource pxa27x_resource_ssp1[] = {
  620. [0] = {
  621. .start = 0x41000000,
  622. .end = 0x4100003f,
  623. .flags = IORESOURCE_MEM,
  624. },
  625. [1] = {
  626. .start = IRQ_SSP,
  627. .end = IRQ_SSP,
  628. .flags = IORESOURCE_IRQ,
  629. },
  630. };
  631. struct platform_device pxa27x_device_ssp1 = {
  632. .name = "pxa27x-ssp",
  633. .id = 0,
  634. .dev = {
  635. .dma_mask = &pxa27x_ssp1_dma_mask,
  636. .coherent_dma_mask = DMA_BIT_MASK(32),
  637. },
  638. .resource = pxa27x_resource_ssp1,
  639. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  640. };
  641. static u64 pxa27x_ssp2_dma_mask = DMA_BIT_MASK(32);
  642. static struct resource pxa27x_resource_ssp2[] = {
  643. [0] = {
  644. .start = 0x41700000,
  645. .end = 0x4170003f,
  646. .flags = IORESOURCE_MEM,
  647. },
  648. [1] = {
  649. .start = IRQ_SSP2,
  650. .end = IRQ_SSP2,
  651. .flags = IORESOURCE_IRQ,
  652. },
  653. };
  654. struct platform_device pxa27x_device_ssp2 = {
  655. .name = "pxa27x-ssp",
  656. .id = 1,
  657. .dev = {
  658. .dma_mask = &pxa27x_ssp2_dma_mask,
  659. .coherent_dma_mask = DMA_BIT_MASK(32),
  660. },
  661. .resource = pxa27x_resource_ssp2,
  662. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  663. };
  664. static u64 pxa27x_ssp3_dma_mask = DMA_BIT_MASK(32);
  665. static struct resource pxa27x_resource_ssp3[] = {
  666. [0] = {
  667. .start = 0x41900000,
  668. .end = 0x4190003f,
  669. .flags = IORESOURCE_MEM,
  670. },
  671. [1] = {
  672. .start = IRQ_SSP3,
  673. .end = IRQ_SSP3,
  674. .flags = IORESOURCE_IRQ,
  675. },
  676. };
  677. struct platform_device pxa27x_device_ssp3 = {
  678. .name = "pxa27x-ssp",
  679. .id = 2,
  680. .dev = {
  681. .dma_mask = &pxa27x_ssp3_dma_mask,
  682. .coherent_dma_mask = DMA_BIT_MASK(32),
  683. },
  684. .resource = pxa27x_resource_ssp3,
  685. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  686. };
  687. static struct resource pxa27x_resource_pwm0[] = {
  688. [0] = {
  689. .start = 0x40b00000,
  690. .end = 0x40b0001f,
  691. .flags = IORESOURCE_MEM,
  692. },
  693. };
  694. struct platform_device pxa27x_device_pwm0 = {
  695. .name = "pxa27x-pwm",
  696. .id = 0,
  697. .resource = pxa27x_resource_pwm0,
  698. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm0),
  699. };
  700. static struct resource pxa27x_resource_pwm1[] = {
  701. [0] = {
  702. .start = 0x40c00000,
  703. .end = 0x40c0001f,
  704. .flags = IORESOURCE_MEM,
  705. },
  706. };
  707. struct platform_device pxa27x_device_pwm1 = {
  708. .name = "pxa27x-pwm",
  709. .id = 1,
  710. .resource = pxa27x_resource_pwm1,
  711. .num_resources = ARRAY_SIZE(pxa27x_resource_pwm1),
  712. };
  713. #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
  714. #ifdef CONFIG_PXA3xx
  715. static struct resource pxa3xx_resources_mci2[] = {
  716. [0] = {
  717. .start = 0x42000000,
  718. .end = 0x42000fff,
  719. .flags = IORESOURCE_MEM,
  720. },
  721. [1] = {
  722. .start = IRQ_MMC2,
  723. .end = IRQ_MMC2,
  724. .flags = IORESOURCE_IRQ,
  725. },
  726. };
  727. struct platform_device pxa3xx_device_mci2 = {
  728. .name = "pxa2xx-mci",
  729. .id = 1,
  730. .dev = {
  731. .dma_mask = &pxamci_dmamask,
  732. .coherent_dma_mask = 0xffffffff,
  733. },
  734. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci2),
  735. .resource = pxa3xx_resources_mci2,
  736. };
  737. void __init pxa3xx_set_mci2_info(struct pxamci_platform_data *info)
  738. {
  739. pxa_register_device(&pxa3xx_device_mci2, info);
  740. }
  741. static struct resource pxa3xx_resources_mci3[] = {
  742. [0] = {
  743. .start = 0x42500000,
  744. .end = 0x42500fff,
  745. .flags = IORESOURCE_MEM,
  746. },
  747. [1] = {
  748. .start = IRQ_MMC3,
  749. .end = IRQ_MMC3,
  750. .flags = IORESOURCE_IRQ,
  751. },
  752. };
  753. struct platform_device pxa3xx_device_mci3 = {
  754. .name = "pxa2xx-mci",
  755. .id = 2,
  756. .dev = {
  757. .dma_mask = &pxamci_dmamask,
  758. .coherent_dma_mask = 0xffffffff,
  759. },
  760. .num_resources = ARRAY_SIZE(pxa3xx_resources_mci3),
  761. .resource = pxa3xx_resources_mci3,
  762. };
  763. void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
  764. {
  765. pxa_register_device(&pxa3xx_device_mci3, info);
  766. }
  767. static struct resource pxa3xx_resources_gcu[] = {
  768. {
  769. .start = 0x54000000,
  770. .end = 0x54000fff,
  771. .flags = IORESOURCE_MEM,
  772. },
  773. {
  774. .start = IRQ_GCU,
  775. .end = IRQ_GCU,
  776. .flags = IORESOURCE_IRQ,
  777. },
  778. };
  779. static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
  780. struct platform_device pxa3xx_device_gcu = {
  781. .name = "pxa3xx-gcu",
  782. .id = -1,
  783. .num_resources = ARRAY_SIZE(pxa3xx_resources_gcu),
  784. .resource = pxa3xx_resources_gcu,
  785. .dev = {
  786. .dma_mask = &pxa3xx_gcu_dmamask,
  787. .coherent_dma_mask = 0xffffffff,
  788. },
  789. };
  790. #endif /* CONFIG_PXA3xx */
  791. #if defined(CONFIG_PXA3xx)
  792. static struct resource pxa3xx_resources_i2c_power[] = {
  793. {
  794. .start = 0x40f500c0,
  795. .end = 0x40f500d3,
  796. .flags = IORESOURCE_MEM,
  797. }, {
  798. .start = IRQ_PWRI2C,
  799. .end = IRQ_PWRI2C,
  800. .flags = IORESOURCE_IRQ,
  801. },
  802. };
  803. struct platform_device pxa3xx_device_i2c_power = {
  804. .name = "pxa3xx-pwri2c",
  805. .id = 1,
  806. .resource = pxa3xx_resources_i2c_power,
  807. .num_resources = ARRAY_SIZE(pxa3xx_resources_i2c_power),
  808. };
  809. static struct resource pxa3xx_resources_nand[] = {
  810. [0] = {
  811. .start = 0x43100000,
  812. .end = 0x43100053,
  813. .flags = IORESOURCE_MEM,
  814. },
  815. [1] = {
  816. .start = IRQ_NAND,
  817. .end = IRQ_NAND,
  818. .flags = IORESOURCE_IRQ,
  819. },
  820. };
  821. static u64 pxa3xx_nand_dma_mask = DMA_BIT_MASK(32);
  822. struct platform_device pxa3xx_device_nand = {
  823. .name = "pxa3xx-nand",
  824. .id = -1,
  825. .dev = {
  826. .dma_mask = &pxa3xx_nand_dma_mask,
  827. .coherent_dma_mask = DMA_BIT_MASK(32),
  828. },
  829. .num_resources = ARRAY_SIZE(pxa3xx_resources_nand),
  830. .resource = pxa3xx_resources_nand,
  831. };
  832. void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
  833. {
  834. pxa_register_device(&pxa3xx_device_nand, info);
  835. }
  836. static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
  837. static struct resource pxa3xx_resource_ssp4[] = {
  838. [0] = {
  839. .start = 0x41a00000,
  840. .end = 0x41a0003f,
  841. .flags = IORESOURCE_MEM,
  842. },
  843. [1] = {
  844. .start = IRQ_SSP4,
  845. .end = IRQ_SSP4,
  846. .flags = IORESOURCE_IRQ,
  847. },
  848. };
  849. /*
  850. * PXA3xx SSP is basically equivalent to PXA27x.
  851. * However, we need to register the device by the correct name in order to
  852. * make the driver set the correct internal type, hence we provide specific
  853. * platform_devices for each of them.
  854. */
  855. struct platform_device pxa3xx_device_ssp1 = {
  856. .name = "pxa3xx-ssp",
  857. .id = 0,
  858. .dev = {
  859. .dma_mask = &pxa27x_ssp1_dma_mask,
  860. .coherent_dma_mask = DMA_BIT_MASK(32),
  861. },
  862. .resource = pxa27x_resource_ssp1,
  863. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp1),
  864. };
  865. struct platform_device pxa3xx_device_ssp2 = {
  866. .name = "pxa3xx-ssp",
  867. .id = 1,
  868. .dev = {
  869. .dma_mask = &pxa27x_ssp2_dma_mask,
  870. .coherent_dma_mask = DMA_BIT_MASK(32),
  871. },
  872. .resource = pxa27x_resource_ssp2,
  873. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp2),
  874. };
  875. struct platform_device pxa3xx_device_ssp3 = {
  876. .name = "pxa3xx-ssp",
  877. .id = 2,
  878. .dev = {
  879. .dma_mask = &pxa27x_ssp3_dma_mask,
  880. .coherent_dma_mask = DMA_BIT_MASK(32),
  881. },
  882. .resource = pxa27x_resource_ssp3,
  883. .num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
  884. };
  885. struct platform_device pxa3xx_device_ssp4 = {
  886. .name = "pxa3xx-ssp",
  887. .id = 3,
  888. .dev = {
  889. .dma_mask = &pxa3xx_ssp4_dma_mask,
  890. .coherent_dma_mask = DMA_BIT_MASK(32),
  891. },
  892. .resource = pxa3xx_resource_ssp4,
  893. .num_resources = ARRAY_SIZE(pxa3xx_resource_ssp4),
  894. };
  895. #endif /* CONFIG_PXA3xx */
  896. struct resource pxa_resource_gpio[] = {
  897. {
  898. .start = 0x40e00000,
  899. .end = 0x40e0ffff,
  900. .flags = IORESOURCE_MEM,
  901. }, {
  902. .start = IRQ_GPIO0,
  903. .end = IRQ_GPIO0,
  904. .name = "gpio0",
  905. .flags = IORESOURCE_IRQ,
  906. }, {
  907. .start = IRQ_GPIO1,
  908. .end = IRQ_GPIO1,
  909. .name = "gpio1",
  910. .flags = IORESOURCE_IRQ,
  911. }, {
  912. .start = IRQ_GPIO_2_x,
  913. .end = IRQ_GPIO_2_x,
  914. .name = "gpio_mux",
  915. .flags = IORESOURCE_IRQ,
  916. },
  917. };
  918. struct platform_device pxa25x_device_gpio = {
  919. #ifdef CONFIG_CPU_PXA26x
  920. .name = "pxa26x-gpio",
  921. #else
  922. .name = "pxa25x-gpio",
  923. #endif
  924. .id = -1,
  925. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  926. .resource = pxa_resource_gpio,
  927. };
  928. struct platform_device pxa27x_device_gpio = {
  929. .name = "pxa27x-gpio",
  930. .id = -1,
  931. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  932. .resource = pxa_resource_gpio,
  933. };
  934. struct platform_device pxa3xx_device_gpio = {
  935. .name = "pxa3xx-gpio",
  936. .id = -1,
  937. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  938. .resource = pxa_resource_gpio,
  939. };
  940. struct platform_device pxa93x_device_gpio = {
  941. .name = "pxa93x-gpio",
  942. .id = -1,
  943. .num_resources = ARRAY_SIZE(pxa_resource_gpio),
  944. .resource = pxa_resource_gpio,
  945. };
  946. /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  947. * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
  948. void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_controller *info)
  949. {
  950. struct platform_device *pd;
  951. pd = platform_device_alloc("pxa2xx-spi", id);
  952. if (pd == NULL) {
  953. printk(KERN_ERR "pxa2xx-spi: failed to allocate device id %d\n",
  954. id);
  955. return;
  956. }
  957. pd->dev.platform_data = info;
  958. platform_device_add(pd);
  959. }
  960. static struct resource pxa_dma_resource[] = {
  961. [0] = {
  962. .start = 0x40000000,
  963. .end = 0x4000ffff,
  964. .flags = IORESOURCE_MEM,
  965. },
  966. [1] = {
  967. .start = IRQ_DMA,
  968. .end = IRQ_DMA,
  969. .flags = IORESOURCE_IRQ,
  970. },
  971. };
  972. static u64 pxadma_dmamask = 0xffffffffUL;
  973. static struct platform_device pxa2xx_pxa_dma = {
  974. .name = "pxa-dma",
  975. .id = 0,
  976. .dev = {
  977. .dma_mask = &pxadma_dmamask,
  978. .coherent_dma_mask = 0xffffffff,
  979. },
  980. .num_resources = ARRAY_SIZE(pxa_dma_resource),
  981. .resource = pxa_dma_resource,
  982. };
  983. void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata)
  984. {
  985. pxa_register_device(&pxa2xx_pxa_dma, dma_pdata);
  986. }
  987. void __init pxa_register_wdt(unsigned int reset_status)
  988. {
  989. struct resource res = DEFINE_RES_MEM(OST_PHYS, OST_LEN);
  990. reset_status &= RESET_STATUS_WATCHDOG;
  991. platform_device_register_resndata(NULL, "sa1100_wdt", -1, &res, 1,
  992. &reset_status, sizeof(reset_status));
  993. }