platsmp.c 2.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (C) 2016 Neil Armstrong <[email protected]>
  4. * Copyright (C) 2013 Ma Haijun <[email protected]>
  5. * Copyright (C) 2002 ARM Ltd.
  6. * All Rights Reserved
  7. */
  8. #include <linux/io.h>
  9. #include <linux/delay.h>
  10. #include <linux/of.h>
  11. #include <linux/of_address.h>
  12. #include <asm/cacheflush.h>
  13. #include <asm/cp15.h>
  14. #include <asm/smp_plat.h>
  15. #include <asm/smp_scu.h>
  16. extern void ox820_secondary_startup(void);
  17. static void __iomem *cpu_ctrl;
  18. static void __iomem *gic_cpu_ctrl;
  19. #define HOLDINGPEN_CPU_OFFSET 0xc8
  20. #define HOLDINGPEN_LOCATION_OFFSET 0xc4
  21. #define GIC_NCPU_OFFSET(cpu) (0x100 + (cpu)*0x100)
  22. #define GIC_CPU_CTRL 0x00
  23. #define GIC_CPU_CTRL_ENABLE 1
  24. static int __init ox820_boot_secondary(unsigned int cpu,
  25. struct task_struct *idle)
  26. {
  27. /*
  28. * Write the address of secondary startup into the
  29. * system-wide flags register. The BootMonitor waits
  30. * until it receives a soft interrupt, and then the
  31. * secondary CPU branches to this address.
  32. */
  33. writel(virt_to_phys(ox820_secondary_startup),
  34. cpu_ctrl + HOLDINGPEN_LOCATION_OFFSET);
  35. writel(cpu, cpu_ctrl + HOLDINGPEN_CPU_OFFSET);
  36. /*
  37. * Enable GIC cpu interface in CPU Interface Control Register
  38. */
  39. writel(GIC_CPU_CTRL_ENABLE,
  40. gic_cpu_ctrl + GIC_NCPU_OFFSET(cpu) + GIC_CPU_CTRL);
  41. /*
  42. * Send the secondary CPU a soft interrupt, thereby causing
  43. * the boot monitor to read the system wide flags register,
  44. * and branch to the address found there.
  45. */
  46. arch_send_wakeup_ipi_mask(cpumask_of(cpu));
  47. return 0;
  48. }
  49. static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
  50. {
  51. struct device_node *np;
  52. void __iomem *scu_base;
  53. np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-scu");
  54. scu_base = of_iomap(np, 0);
  55. of_node_put(np);
  56. if (!scu_base)
  57. return;
  58. /* Remap CPU Interrupt Interface Registers */
  59. np = of_find_compatible_node(NULL, NULL, "arm,arm11mp-gic");
  60. gic_cpu_ctrl = of_iomap(np, 1);
  61. of_node_put(np);
  62. if (!gic_cpu_ctrl)
  63. goto unmap_scu;
  64. np = of_find_compatible_node(NULL, NULL, "oxsemi,ox820-sys-ctrl");
  65. cpu_ctrl = of_iomap(np, 0);
  66. of_node_put(np);
  67. if (!cpu_ctrl)
  68. goto unmap_scu;
  69. scu_enable(scu_base);
  70. flush_cache_all();
  71. unmap_scu:
  72. iounmap(scu_base);
  73. }
  74. static const struct smp_operations ox820_smp_ops __initconst = {
  75. .smp_prepare_cpus = ox820_smp_prepare_cpus,
  76. .smp_boot_secondary = ox820_boot_secondary,
  77. };
  78. CPU_METHOD_OF_DECLARE(ox820_smp, "oxsemi,ox820-smp", &ox820_smp_ops);