vc.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * OMAP Voltage Controller (VC) interface
  4. *
  5. * Copyright (C) 2011 Texas Instruments, Inc.
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/delay.h>
  9. #include <linux/init.h>
  10. #include <linux/bug.h>
  11. #include <linux/io.h>
  12. #include <asm/div64.h>
  13. #include "iomap.h"
  14. #include "soc.h"
  15. #include "voltage.h"
  16. #include "vc.h"
  17. #include "prm-regbits-34xx.h"
  18. #include "prm-regbits-44xx.h"
  19. #include "prm44xx.h"
  20. #include "pm.h"
  21. #include "scrm44xx.h"
  22. #include "control.h"
  23. #define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14)
  24. #define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13)
  25. #define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12)
  26. #define OMAP4430_VDD_IVA_PRESENCE BIT(9)
  27. #define OMAP4430_VDD_MPU_PRESENCE BIT(8)
  28. #define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4)
  29. #define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2)
  30. #define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0)
  31. #define OMAP4430_AUTO_CTRL_VDD_RET 2
  32. #define OMAP4430_VDD_I2C_DISABLE_MASK \
  33. (OMAP4430_VDD_IVA_I2C_DISABLE | \
  34. OMAP4430_VDD_MPU_I2C_DISABLE | \
  35. OMAP4430_VDD_CORE_I2C_DISABLE)
  36. #define OMAP4_VDD_DEFAULT_VAL \
  37. (OMAP4430_VDD_I2C_DISABLE_MASK | \
  38. OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
  39. OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
  40. OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
  41. OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
  42. #define OMAP4_VDD_RET_VAL \
  43. (OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
  44. /**
  45. * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
  46. * @sa: bit for slave address
  47. * @rav: bit for voltage configuration register
  48. * @rac: bit for command configuration register
  49. * @racen: enable bit for RAC
  50. * @cmd: bit for command value set selection
  51. *
  52. * Channel configuration bits, common for OMAP3+
  53. * OMAP3 register: PRM_VC_CH_CONF
  54. * OMAP4 register: PRM_VC_CFG_CHANNEL
  55. * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
  56. */
  57. struct omap_vc_channel_cfg {
  58. u8 sa;
  59. u8 rav;
  60. u8 rac;
  61. u8 racen;
  62. u8 cmd;
  63. };
  64. static struct omap_vc_channel_cfg vc_default_channel_cfg = {
  65. .sa = BIT(0),
  66. .rav = BIT(1),
  67. .rac = BIT(2),
  68. .racen = BIT(3),
  69. .cmd = BIT(4),
  70. };
  71. /*
  72. * On OMAP3+, all VC channels have the above default bitfield
  73. * configuration, except the OMAP4 MPU channel. This appears
  74. * to be a freak accident as every other VC channel has the
  75. * default configuration, thus creating a mutant channel config.
  76. */
  77. static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
  78. .sa = BIT(0),
  79. .rav = BIT(2),
  80. .rac = BIT(3),
  81. .racen = BIT(4),
  82. .cmd = BIT(1),
  83. };
  84. static struct omap_vc_channel_cfg *vc_cfg_bits;
  85. /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
  86. static u32 sr_i2c_pcb_length = 63;
  87. #define CFG_CHANNEL_MASK 0x1f
  88. /**
  89. * omap_vc_config_channel - configure VC channel to PMIC mappings
  90. * @voltdm: pointer to voltagdomain defining the desired VC channel
  91. *
  92. * Configures the VC channel to PMIC mappings for the following
  93. * PMIC settings
  94. * - i2c slave address (SA)
  95. * - voltage configuration address (RAV)
  96. * - command configuration address (RAC) and enable bit (RACEN)
  97. * - command values for ON, ONLP, RET and OFF (CMD)
  98. *
  99. * This function currently only allows flexible configuration of the
  100. * non-default channel. Starting with OMAP4, there are more than 2
  101. * channels, with one defined as the default (on OMAP4, it's MPU.)
  102. * Only the non-default channel can be configured.
  103. */
  104. static int omap_vc_config_channel(struct voltagedomain *voltdm)
  105. {
  106. struct omap_vc_channel *vc = voltdm->vc;
  107. /*
  108. * For default channel, the only configurable bit is RACEN.
  109. * All others must stay at zero (see function comment above.)
  110. */
  111. if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
  112. vc->cfg_channel &= vc_cfg_bits->racen;
  113. voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
  114. vc->cfg_channel << vc->cfg_channel_sa_shift,
  115. vc->cfg_channel_reg);
  116. return 0;
  117. }
  118. /* Voltage scale and accessory APIs */
  119. int omap_vc_pre_scale(struct voltagedomain *voltdm,
  120. unsigned long target_volt,
  121. u8 *target_vsel, u8 *current_vsel)
  122. {
  123. struct omap_vc_channel *vc = voltdm->vc;
  124. u32 vc_cmdval;
  125. /* Check if sufficient pmic info is available for this vdd */
  126. if (!voltdm->pmic) {
  127. pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
  128. __func__, voltdm->name);
  129. return -EINVAL;
  130. }
  131. if (!voltdm->pmic->uv_to_vsel) {
  132. pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
  133. __func__, voltdm->name);
  134. return -ENODATA;
  135. }
  136. if (!voltdm->read || !voltdm->write) {
  137. pr_err("%s: No read/write API for accessing vdd_%s regs\n",
  138. __func__, voltdm->name);
  139. return -EINVAL;
  140. }
  141. *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
  142. *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
  143. /* Setting the ON voltage to the new target voltage */
  144. vc_cmdval = voltdm->read(vc->cmdval_reg);
  145. vc_cmdval &= ~vc->common->cmd_on_mask;
  146. vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
  147. voltdm->write(vc_cmdval, vc->cmdval_reg);
  148. voltdm->vc_param->on = target_volt;
  149. omap_vp_update_errorgain(voltdm, target_volt);
  150. return 0;
  151. }
  152. void omap_vc_post_scale(struct voltagedomain *voltdm,
  153. unsigned long target_volt,
  154. u8 target_vsel, u8 current_vsel)
  155. {
  156. u32 smps_steps = 0, smps_delay = 0;
  157. smps_steps = abs(target_vsel - current_vsel);
  158. /* SMPS slew rate / step size. 2us added as buffer. */
  159. smps_delay = ((smps_steps * voltdm->pmic->step_size) /
  160. voltdm->pmic->slew_rate) + 2;
  161. udelay(smps_delay);
  162. }
  163. /* vc_bypass_scale - VC bypass method of voltage scaling */
  164. int omap_vc_bypass_scale(struct voltagedomain *voltdm,
  165. unsigned long target_volt)
  166. {
  167. struct omap_vc_channel *vc = voltdm->vc;
  168. u32 loop_cnt = 0, retries_cnt = 0;
  169. u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
  170. u8 target_vsel, current_vsel;
  171. int ret;
  172. ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
  173. if (ret)
  174. return ret;
  175. vc_valid = vc->common->valid;
  176. vc_bypass_val_reg = vc->common->bypass_val_reg;
  177. vc_bypass_value = (target_vsel << vc->common->data_shift) |
  178. (vc->volt_reg_addr << vc->common->regaddr_shift) |
  179. (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
  180. voltdm->write(vc_bypass_value, vc_bypass_val_reg);
  181. voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
  182. vc_bypass_value = voltdm->read(vc_bypass_val_reg);
  183. /*
  184. * Loop till the bypass command is acknowledged from the SMPS.
  185. * NOTE: This is legacy code. The loop count and retry count needs
  186. * to be revisited.
  187. */
  188. while (!(vc_bypass_value & vc_valid)) {
  189. loop_cnt++;
  190. if (retries_cnt > 10) {
  191. pr_warn("%s: Retry count exceeded\n", __func__);
  192. return -ETIMEDOUT;
  193. }
  194. if (loop_cnt > 50) {
  195. retries_cnt++;
  196. loop_cnt = 0;
  197. udelay(10);
  198. }
  199. vc_bypass_value = voltdm->read(vc_bypass_val_reg);
  200. }
  201. omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
  202. return 0;
  203. }
  204. /* Convert microsecond value to number of 32kHz clock cycles */
  205. static inline u32 omap_usec_to_32k(u32 usec)
  206. {
  207. return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
  208. }
  209. struct omap3_vc_timings {
  210. u32 voltsetup1;
  211. u32 voltsetup2;
  212. };
  213. struct omap3_vc {
  214. struct voltagedomain *vd;
  215. u32 voltctrl;
  216. u32 voltsetup1;
  217. u32 voltsetup2;
  218. struct omap3_vc_timings timings[2];
  219. };
  220. static struct omap3_vc vc;
  221. void omap3_vc_set_pmic_signaling(int core_next_state)
  222. {
  223. struct voltagedomain *vd = vc.vd;
  224. struct omap3_vc_timings *c = vc.timings;
  225. u32 voltctrl, voltsetup1, voltsetup2;
  226. voltctrl = vc.voltctrl;
  227. voltsetup1 = vc.voltsetup1;
  228. voltsetup2 = vc.voltsetup2;
  229. switch (core_next_state) {
  230. case PWRDM_POWER_OFF:
  231. voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
  232. OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
  233. voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
  234. if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
  235. voltsetup2 = c->voltsetup2;
  236. else
  237. voltsetup1 = c->voltsetup1;
  238. break;
  239. case PWRDM_POWER_RET:
  240. default:
  241. c++;
  242. voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
  243. OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
  244. voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
  245. voltsetup1 = c->voltsetup1;
  246. break;
  247. }
  248. if (voltctrl != vc.voltctrl) {
  249. vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
  250. vc.voltctrl = voltctrl;
  251. }
  252. if (voltsetup1 != vc.voltsetup1) {
  253. vd->write(c->voltsetup1,
  254. OMAP3_PRM_VOLTSETUP1_OFFSET);
  255. vc.voltsetup1 = voltsetup1;
  256. }
  257. if (voltsetup2 != vc.voltsetup2) {
  258. vd->write(c->voltsetup2,
  259. OMAP3_PRM_VOLTSETUP2_OFFSET);
  260. vc.voltsetup2 = voltsetup2;
  261. }
  262. }
  263. void omap4_vc_set_pmic_signaling(int core_next_state)
  264. {
  265. struct voltagedomain *vd = vc.vd;
  266. u32 val;
  267. if (!vd)
  268. return;
  269. switch (core_next_state) {
  270. case PWRDM_POWER_RET:
  271. val = OMAP4_VDD_RET_VAL;
  272. break;
  273. default:
  274. val = OMAP4_VDD_DEFAULT_VAL;
  275. break;
  276. }
  277. vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
  278. }
  279. /*
  280. * Configure signal polarity for sys_clkreq and sys_off_mode pins
  281. * as the default values are wrong and can cause the system to hang
  282. * if any twl4030 scripts are loaded.
  283. */
  284. static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
  285. {
  286. u32 val;
  287. if (vc.vd)
  288. return;
  289. vc.vd = voltdm;
  290. val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
  291. if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
  292. (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) {
  293. val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
  294. val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
  295. pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
  296. val);
  297. voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
  298. }
  299. /*
  300. * By default let's use I2C4 signaling for retention idle
  301. * and sys_off_mode pin signaling for off idle. This way we
  302. * have sys_clk_req pin go down for retention and both
  303. * sys_clk_req and sys_off_mode pins will go down for off
  304. * idle. And we can also scale voltages to zero for off-idle.
  305. * Note that no actual voltage scaling during off-idle will
  306. * happen unless the board specific twl4030 PMIC scripts are
  307. * loaded. See also omap_vc_i2c_init for comments regarding
  308. * erratum i531.
  309. */
  310. val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
  311. if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
  312. val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
  313. pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
  314. val);
  315. voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
  316. }
  317. vc.voltctrl = val;
  318. omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
  319. }
  320. static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
  321. struct omap3_vc_timings *c, u32 idle)
  322. {
  323. unsigned long val;
  324. val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
  325. val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
  326. val <<= __ffs(voltdm->vfsm->voltsetup_mask);
  327. c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
  328. c->voltsetup1 |= val;
  329. }
  330. /**
  331. * omap3_set_i2c_timings - sets i2c sleep timings for a channel
  332. * @voltdm: channel to configure
  333. * @off_mode: select whether retention or off mode values used
  334. *
  335. * Calculates and sets up voltage controller to use I2C based
  336. * voltage scaling for sleep modes. This can be used for either off mode
  337. * or retention. Off mode has additionally an option to use sys_off_mode
  338. * pad, which uses a global signal to program the whole power IC to
  339. * off-mode.
  340. *
  341. * Note that pmic is not controlling the voltage scaling during
  342. * retention signaled over I2C4, so we can keep voltsetup2 as 0.
  343. * And the oscillator is not shut off over I2C4, so no need to
  344. * set clksetup.
  345. */
  346. static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
  347. {
  348. struct omap3_vc_timings *c = vc.timings;
  349. /* Configure PRWDM_POWER_OFF over I2C4 */
  350. omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
  351. c++;
  352. /* Configure PRWDM_POWER_RET over I2C4 */
  353. omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
  354. }
  355. /**
  356. * omap3_set_off_timings - sets off-mode timings for a channel
  357. * @voltdm: channel to configure
  358. *
  359. * Calculates and sets up off-mode timings for a channel. Off-mode
  360. * can use either I2C based voltage scaling, or alternatively
  361. * sys_off_mode pad can be used to send a global command to power IC.n,
  362. * sys_off_mode has the additional benefit that voltages can be
  363. * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
  364. * scale to 600mV.
  365. *
  366. * Note that omap is not controlling the voltage scaling during
  367. * off idle signaled by sys_off_mode, so we can keep voltsetup1
  368. * as 0.
  369. */
  370. static void omap3_set_off_timings(struct voltagedomain *voltdm)
  371. {
  372. struct omap3_vc_timings *c = vc.timings;
  373. u32 tstart, tshut, clksetup, voltoffset;
  374. if (c->voltsetup2)
  375. return;
  376. omap_pm_get_oscillator(&tstart, &tshut);
  377. if (tstart == ULONG_MAX) {
  378. pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
  379. clksetup = omap_usec_to_32k(10000);
  380. } else {
  381. clksetup = omap_usec_to_32k(tstart);
  382. }
  383. /*
  384. * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
  385. * switch from HFCLKIN to internal oscillator. That means timings
  386. * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
  387. * that means we can calculate the value based on the oscillator
  388. * start-up time since voltoffset2 = clksetup - voltoffset.
  389. */
  390. voltoffset = omap_usec_to_32k(488);
  391. c->voltsetup2 = clksetup - voltoffset;
  392. voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
  393. voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
  394. }
  395. static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
  396. {
  397. omap3_vc_init_pmic_signaling(voltdm);
  398. omap3_set_off_timings(voltdm);
  399. omap3_set_i2c_timings(voltdm);
  400. }
  401. /**
  402. * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
  403. * @voltdm: channel to calculate values for
  404. * @voltage_diff: voltage difference in microvolts
  405. *
  406. * Calculates voltage ramp prescaler + counter values for a voltage
  407. * difference on omap4. Returns a field value suitable for writing to
  408. * VOLTSETUP register for a channel in following format:
  409. * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
  410. */
  411. static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
  412. {
  413. u32 prescaler;
  414. u32 cycles;
  415. u32 time;
  416. time = voltage_diff / voltdm->pmic->slew_rate;
  417. cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
  418. cycles /= 64;
  419. prescaler = 0;
  420. /* shift to next prescaler until no overflow */
  421. /* scale for div 256 = 64 * 4 */
  422. if (cycles > 63) {
  423. cycles /= 4;
  424. prescaler++;
  425. }
  426. /* scale for div 512 = 256 * 2 */
  427. if (cycles > 63) {
  428. cycles /= 2;
  429. prescaler++;
  430. }
  431. /* scale for div 2048 = 512 * 4 */
  432. if (cycles > 63) {
  433. cycles /= 4;
  434. prescaler++;
  435. }
  436. /* check for overflow => invalid ramp time */
  437. if (cycles > 63) {
  438. pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
  439. voltdm->name);
  440. return 0;
  441. }
  442. cycles++;
  443. return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
  444. (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
  445. }
  446. /**
  447. * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
  448. * @usec: microseconds
  449. * @shift: number of bits to shift left
  450. * @mask: bitfield mask
  451. *
  452. * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
  453. * shifted to requested position, and checked agains the mask value.
  454. * If larger, forced to the max value of the field (i.e. the mask itself.)
  455. * Returns the SCRM bitfield value.
  456. */
  457. static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
  458. {
  459. u32 val;
  460. val = omap_usec_to_32k(usec) << shift;
  461. /* Check for overflow, if yes, force to max value */
  462. if (val > mask)
  463. val = mask;
  464. return val;
  465. }
  466. /**
  467. * omap4_set_timings - set voltage ramp timings for a channel
  468. * @voltdm: channel to configure
  469. * @off_mode: whether off-mode values are used
  470. *
  471. * Calculates and sets the voltage ramp up / down values for a channel.
  472. */
  473. static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
  474. {
  475. u32 val;
  476. u32 ramp;
  477. int offset;
  478. u32 tstart, tshut;
  479. if (off_mode) {
  480. ramp = omap4_calc_volt_ramp(voltdm,
  481. voltdm->vc_param->on - voltdm->vc_param->off);
  482. offset = voltdm->vfsm->voltsetup_off_reg;
  483. } else {
  484. ramp = omap4_calc_volt_ramp(voltdm,
  485. voltdm->vc_param->on - voltdm->vc_param->ret);
  486. offset = voltdm->vfsm->voltsetup_reg;
  487. }
  488. if (!ramp)
  489. return;
  490. val = voltdm->read(offset);
  491. val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
  492. val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
  493. voltdm->write(val, offset);
  494. omap_pm_get_oscillator(&tstart, &tshut);
  495. val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
  496. OMAP4_SETUPTIME_MASK);
  497. val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
  498. OMAP4_DOWNTIME_MASK);
  499. writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
  500. }
  501. static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
  502. {
  503. if (vc.vd)
  504. return;
  505. vc.vd = voltdm;
  506. voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
  507. }
  508. /* OMAP4 specific voltage init functions */
  509. static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
  510. {
  511. omap4_vc_init_pmic_signaling(voltdm);
  512. omap4_set_timings(voltdm, true);
  513. omap4_set_timings(voltdm, false);
  514. }
  515. struct i2c_init_data {
  516. u8 loadbits;
  517. u8 load;
  518. u8 hsscll_38_4;
  519. u8 hsscll_26;
  520. u8 hsscll_19_2;
  521. u8 hsscll_16_8;
  522. u8 hsscll_12;
  523. };
  524. static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = {
  525. {
  526. .load = 50,
  527. .loadbits = 0x3,
  528. .hsscll_38_4 = 13,
  529. .hsscll_26 = 11,
  530. .hsscll_19_2 = 9,
  531. .hsscll_16_8 = 9,
  532. .hsscll_12 = 8,
  533. },
  534. {
  535. .load = 25,
  536. .loadbits = 0x2,
  537. .hsscll_38_4 = 13,
  538. .hsscll_26 = 11,
  539. .hsscll_19_2 = 9,
  540. .hsscll_16_8 = 9,
  541. .hsscll_12 = 8,
  542. },
  543. {
  544. .load = 12,
  545. .loadbits = 0x1,
  546. .hsscll_38_4 = 11,
  547. .hsscll_26 = 10,
  548. .hsscll_19_2 = 9,
  549. .hsscll_16_8 = 9,
  550. .hsscll_12 = 8,
  551. },
  552. {
  553. .load = 0,
  554. .loadbits = 0x0,
  555. .hsscll_38_4 = 12,
  556. .hsscll_26 = 10,
  557. .hsscll_19_2 = 9,
  558. .hsscll_16_8 = 8,
  559. .hsscll_12 = 8,
  560. },
  561. };
  562. /**
  563. * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
  564. * @voltdm: voltagedomain pointer to get data from
  565. *
  566. * Use PMIC + board supplied settings for calculating the total I2C
  567. * channel capacitance and set the timing parameters based on this.
  568. * Pre-calculated values are provided in data tables, as it is not
  569. * too straightforward to calculate these runtime.
  570. */
  571. static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
  572. {
  573. u32 capacitance;
  574. u32 val;
  575. u16 hsscll;
  576. const struct i2c_init_data *i2c_data;
  577. if (!voltdm->pmic->i2c_high_speed) {
  578. pr_info("%s: using bootloader low-speed timings\n", __func__);
  579. return;
  580. }
  581. /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
  582. capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
  583. /* OMAP pad capacitance */
  584. capacitance += 4;
  585. /* PMIC pad capacitance */
  586. capacitance += voltdm->pmic->i2c_pad_load;
  587. /* Search for capacitance match in the table */
  588. i2c_data = omap4_i2c_timing_data;
  589. while (i2c_data->load > capacitance)
  590. i2c_data++;
  591. /* Select proper values based on sysclk frequency */
  592. switch (voltdm->sys_clk.rate) {
  593. case 38400000:
  594. hsscll = i2c_data->hsscll_38_4;
  595. break;
  596. case 26000000:
  597. hsscll = i2c_data->hsscll_26;
  598. break;
  599. case 19200000:
  600. hsscll = i2c_data->hsscll_19_2;
  601. break;
  602. case 16800000:
  603. hsscll = i2c_data->hsscll_16_8;
  604. break;
  605. case 12000000:
  606. hsscll = i2c_data->hsscll_12;
  607. break;
  608. default:
  609. pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
  610. voltdm->sys_clk.rate);
  611. return;
  612. }
  613. /* Loadbits define pull setup for the I2C channels */
  614. val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
  615. /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
  616. writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
  617. OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
  618. /* HSSCLH can always be zero */
  619. val = hsscll << OMAP4430_HSSCLL_SHIFT;
  620. val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
  621. /* Write setup times to I2C config register */
  622. voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
  623. }
  624. /**
  625. * omap_vc_i2c_init - initialize I2C interface to PMIC
  626. * @voltdm: voltage domain containing VC data
  627. *
  628. * Use PMIC supplied settings for I2C high-speed mode and
  629. * master code (if set) and program the VC I2C configuration
  630. * register.
  631. *
  632. * The VC I2C configuration is common to all VC channels,
  633. * so this function only configures I2C for the first VC
  634. * channel registers. All other VC channels will use the
  635. * same configuration.
  636. */
  637. static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
  638. {
  639. struct omap_vc_channel *vc = voltdm->vc;
  640. static bool initialized;
  641. static bool i2c_high_speed;
  642. u8 mcode;
  643. if (initialized) {
  644. if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
  645. pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
  646. __func__, voltdm->name, i2c_high_speed);
  647. return;
  648. }
  649. /*
  650. * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
  651. * erratum i531 "Extra Power Consumed When Repeated Start Operation
  652. * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
  653. * Otherwise I2C4 eventually leads into about 23mW extra power being
  654. * consumed even during off idle using VMODE.
  655. */
  656. i2c_high_speed = voltdm->pmic->i2c_high_speed;
  657. if (i2c_high_speed)
  658. voltdm->rmw(vc->common->i2c_cfg_clear_mask,
  659. vc->common->i2c_cfg_hsen_mask,
  660. vc->common->i2c_cfg_reg);
  661. mcode = voltdm->pmic->i2c_mcode;
  662. if (mcode)
  663. voltdm->rmw(vc->common->i2c_mcode_mask,
  664. mcode << __ffs(vc->common->i2c_mcode_mask),
  665. vc->common->i2c_cfg_reg);
  666. if (cpu_is_omap44xx())
  667. omap4_vc_i2c_timing_init(voltdm);
  668. initialized = true;
  669. }
  670. /**
  671. * omap_vc_calc_vsel - calculate vsel value for a channel
  672. * @voltdm: channel to calculate value for
  673. * @uvolt: microvolt value to convert to vsel
  674. *
  675. * Converts a microvolt value to vsel value for the used PMIC.
  676. * This checks whether the microvolt value is out of bounds, and
  677. * adjusts the value accordingly. If unsupported value detected,
  678. * warning is thrown.
  679. */
  680. static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
  681. {
  682. if (voltdm->pmic->vddmin > uvolt)
  683. uvolt = voltdm->pmic->vddmin;
  684. if (voltdm->pmic->vddmax < uvolt) {
  685. WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
  686. __func__, uvolt, voltdm->pmic->vddmax);
  687. /* Lets try maximum value anyway */
  688. uvolt = voltdm->pmic->vddmax;
  689. }
  690. return voltdm->pmic->uv_to_vsel(uvolt);
  691. }
  692. #ifdef CONFIG_PM
  693. /**
  694. * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
  695. * @mm: length of the PCB trace in millimetres
  696. *
  697. * Sets the PCB trace length for the I2C channel. By default uses 63mm.
  698. * This is needed for properly calculating the capacitance value for
  699. * the PCB trace, and for setting the SR I2C channel timing parameters.
  700. */
  701. void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
  702. {
  703. sr_i2c_pcb_length = mm;
  704. }
  705. #endif
  706. void __init omap_vc_init_channel(struct voltagedomain *voltdm)
  707. {
  708. struct omap_vc_channel *vc = voltdm->vc;
  709. u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
  710. u32 val;
  711. if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
  712. pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
  713. return;
  714. }
  715. if (!voltdm->read || !voltdm->write) {
  716. pr_err("%s: No read/write API for accessing vdd_%s regs\n",
  717. __func__, voltdm->name);
  718. return;
  719. }
  720. vc->cfg_channel = 0;
  721. if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
  722. vc_cfg_bits = &vc_mutant_channel_cfg;
  723. else
  724. vc_cfg_bits = &vc_default_channel_cfg;
  725. /* get PMIC/board specific settings */
  726. vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
  727. vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
  728. vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
  729. /* Configure the i2c slave address for this VC */
  730. voltdm->rmw(vc->smps_sa_mask,
  731. vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
  732. vc->smps_sa_reg);
  733. vc->cfg_channel |= vc_cfg_bits->sa;
  734. /*
  735. * Configure the PMIC register addresses.
  736. */
  737. voltdm->rmw(vc->smps_volra_mask,
  738. vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
  739. vc->smps_volra_reg);
  740. vc->cfg_channel |= vc_cfg_bits->rav;
  741. if (vc->cmd_reg_addr) {
  742. voltdm->rmw(vc->smps_cmdra_mask,
  743. vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
  744. vc->smps_cmdra_reg);
  745. vc->cfg_channel |= vc_cfg_bits->rac;
  746. }
  747. if (vc->cmd_reg_addr == vc->volt_reg_addr)
  748. vc->cfg_channel |= vc_cfg_bits->racen;
  749. /* Set up the on, inactive, retention and off voltage */
  750. on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
  751. onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
  752. ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
  753. off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
  754. val = ((on_vsel << vc->common->cmd_on_shift) |
  755. (onlp_vsel << vc->common->cmd_onlp_shift) |
  756. (ret_vsel << vc->common->cmd_ret_shift) |
  757. (off_vsel << vc->common->cmd_off_shift));
  758. voltdm->write(val, vc->cmdval_reg);
  759. vc->cfg_channel |= vc_cfg_bits->cmd;
  760. /* Channel configuration */
  761. omap_vc_config_channel(voltdm);
  762. omap_vc_i2c_init(voltdm);
  763. if (cpu_is_omap34xx())
  764. omap3_vc_init_channel(voltdm);
  765. else if (cpu_is_omap44xx())
  766. omap4_vc_init_channel(voltdm);
  767. }